On Monday, May 30, 2022 at 2:26:35 PM UTC-5, Michael S wrote:
> On Monday, May 30, 2022 at 9:05:22 PM UTC+3, Stephen Fuld wrote:
> > On 5/27/2022 1:54 PM, MitchAlsup wrote:
> > > On Friday, May 27, 2022 at 11:58:14 AM UTC-5, Stephen Fuld wrote:
> > >> On 5/27/2022 9:11 AM, Michael S wrote:
> > >>> On Friday, May 27, 2022 at 3:15:03 PM UTC+3, Anton Ertl wrote:
> > >>>> Michael S <already...@yahoo.com> writes:
> > >>>>> On Friday, May 27, 2022 at 10:53:05 AM UTC+3, Anton Ertl wrote:
> > >>>>>> In the long run, the (sub)channels are going to become narrower,=20
> > >>>>>
> > >>>>> You still assume that we are ahead of long run [of Moore law].
> > >>>>> I am less optimistic. I seems plausible that provisions for 64gb devices
> > >>>>> that is already in DDR5 will suffice for more than decade.
> > >>>>> May be, close to 2 decades.
> > >>>> Newer DDR standards are not primarily about chip capacity (currently
> > >>>> the largest DDR5 chips are not larger than supported by DDR4: 16Gb),
> > >>>> but about transfer rate. I.e., if the transfer rate becomes faster
> > >>>> than 16x the internal cycle time of DRAM, they have to increase the
> > >>>> minimum burst length (and decrease the (sub)channel width) to benefit
> > >>>> from that increase. And currently I see no sign that the transfer
> > >>>> rate increases are slowing down. DDR4 was released 7 years after
> > >>>> DDR3; DDR5 was released 6 years after DDR4. On the PCIe front, the
> > >>>> release cadence seems to be even higher.
> > >>>> - anton
> > >>>> --
> > >>>> 'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
> > >>>> Mitch Alsup, <c17fcd89-f024-40e7...@googlegroups.com>
> > >>>
> > >>> I can not formulate it with sufficient rigor, but my opinion is that need
> > >>> in new DDR standards is very much a function of non-stability (hopefully growth)
> > >>> of the market in term of average capacity.
> > > <
> > >> I disagree. If it were true, then newer generations of the standard
> > >> would be much simpler; just add an address bit or two. The fact that
> > >> each standard provides a substantial increase in data rate/bandwidth
> > >> over the previous one, which is harder than adding an address pin, says
> > >> that data rate/bandwidth is the driving factor, and capacity comes in
> > >> second. Unfortunately, latency has proven resistant to substantial
> > >> improvements :-(
> > > <
> > > DRAM chips have rather constant area. Passing over a linear amount of
> > > real-estate is a wire delay problem. So that transistors are getting faster
> > > and wire is getting slower has finally become manifest in DRAM. {actually
> > > DRAM bank access to pin drivers has stayed rather constant since DDR2.}
> > While all of that is true, I think it is only a part of the reason for
> > the long latency. Consider a hypothetical chip of the same physical
> > size as a current DRAM, but instead uses SRAM. Of course, it will have
> > smaller capacity and perhaps require more pins than the DRAM, but I
> > expect it will have lower latency. Is that correct?
> >
> > I think that the original DRAM designers made the (IMO correct) tradeoff
> > to gain lower cost (fewer pins), at the cost of higher latency. This
> > was reinforced by the introduction of CPU caches, which are essentially
> > average latency reducers, hiding much of the longer latency. These
> > allowed DRAMS to successfully dominate the market.
> >
> > However, cache is a diminishing returns game. Adding more improves
> > performance, but not as much as the last time you increased it. So it
> > may be true that reducing DRAM latency may become more important.
> >
> > So what could be done? A lower overhead (fewer transfers) protocol
> > coupled with a different internal design and more pins (i.e. higher
> > cost) might be achievable. It is way out of my area of expertise, but I
> > just want to stimulate thoughts on this.
> >
> > Of course, the marketability of such a design, even if achievable, is a
> > different question. :-(
> > --
> > - Stephen Fuld
> > (e-mail address disguised to prevent spam)
> What you described exists:
> https://www.micron.com/products/dram/rldram-memory
> It is very very very niche, but its existence proves that it is not absolutely non-marketable.
<
This data sheet reminds me a lot of the Psuedostatic DRAM from around 1991.
{Which I used as/for the DRAM timing parameters of Mc 88120 design simulation.}

Anton Ertl <anton@mips.complang.tuwien.ac.at> wrote:
> Michael S <already5chosen@yahoo.com> writes:
>> On Sunday, May 29, 2022 at 7:06:16 PM UTC+3, Anton Ertl wrote:
>>> Michael S <already...@yahoo.com> writes:
>>>> On Sunday, May 29, 2022 at 1:14:20 PM UTC+3, Anton Ertl wrote:
>>>>> Looking at the "RAM type" category in <https://geizhals.eu/?cat=nb>:
>>>>>
>>>>> models
>>>>> 5235 DDR4
>>>>> 1578 LPDDR4
>>>>> 154 DDR5
>>>>> 255 LPDDR5
>>>>>
>>>>> So there are certainly many more models with DDR4/5 than with LPDDR4,
>>>>> and this probably also means more sales.
>>>>>
>>>>
>>>> I'm not sure that it follows.
>>>> Simple models like Dell Latitude 3320 probably outsel more advanced
>>>> models by significant factor.
>>> Maybe. And maybe even cheaper models like, say, the ASUS Business P1
>>> P1511CEA-BQ749 (offered by 81 dealers vs. 57 for the most-offered Dell
>>> Latitude 3320 variant)
>>
>> Or. may be, even lower end ASUS VivoBook E12
>
> Unlikely at the moment, because none are offered. Looking at one
> model, I see that it was last offered in February 2019.
>
>> At very least, we know that according to Gartner estimates Dell PC division
>> as a whole outsells ASUS PC division as whole, 2.5 to 1. So, fewer dealers,
>> but more PCs sold by each dealer.
>> Also, I would think that [at retail] ASUS has many more models than Dell.
>
> ASUS Dell
> 662 468 <https://geizhals.eu/?cat=nb> (Laptops).
> 61 227 <https://geizhals.eu/?cat=sysdiv> (Systems)
>
>> By the way, I don't know how it works in your country, but here Latitude is not
>> seen in shops at all. Only Inspiron , Vostro and occasional Alienware.
>> But at work Latitude is everywhere.
>
> I don't know how it works in my country, and I don't go to shops
> looking what brands of laptops they have, but I don't see that many
> Dells overall when I see other people's laptops. For those that I
> see, I have no idea what models they are. There's a central
> laptop/tablet ordering system two times per year from the University
> of Vienna that my university participates in, and I guess that many
> people buy laptops through this system; the most recent one was
> <https://ubook.at/fileadmin/content/broschueren/ubook_sose2022.pdf>.
> The only Dell Latitude there cost EUR 2239, and I doubt that many
> people bought it.
>
> Anyway, if we assume that Dell sells particularly many laptops, and
> that we need to study them separately, there the RAM type statistics
> is:
>
> models
> 362 DDR4
> 57 LPDDR4
> 17 DDR5
> 4 LPDDR5
>
> So for Dell laptops the balance is even less in favour of LPDDR4. Do
> people all buy these 57 LPDDR4 models, and Dell offers the other
> models just for fun?
>
>>>>> [CXL]
>>>>>> But my point is that people that build this boxen don't need new memory standard
>>>>>> every 5-7 years. Esp. when capacity does not go up. Even with DDR4 they likely
>>>>>> have internal bandwidth that easily exceeds bandwidth of their external COMM
>>>>>> channels, because there is no other way to get required capacity.
>>>>>> So, if they need DDR5 then only because of promised extra capacity.
>>>>> A pure memory box with bandwidth that cannot even compete with DDR4 in
>>>>> bandwidth (and certainly not latency) does not look to me like something
>>>>> that many people would buy. I doubt that we will see such products.
>>>>
>>>> Who says it does not compete with DDR4 in bandwidth?
>>> You do: "Even with DDR4 they likely have internal bandwidth that
>>> easily exceeds bandwidth of their external COMM channels".
>>>
>>
>> Hopefully, now you paid attention to qualifiers "internal and "external".
>>
>>> As for the rest: A box with more memory than supported by LRDIMMs on,
>>> e.g., EPYC boards will probably find a market, but I doubt that it
>>> will replace LRDIMMs.
>>
>> It does not have to replace LR-DIMM in order to make DDR6 unnecessary or,
>> at least, to delay its introduction.
>
> Like DDR5, DDR6 will probably be about bandwidth, not capacity. The
> fact that the largest DDR5 UDIMMs and RDIMMs at the moment are not
> bigger than the largest DDR4 UDIMMs and RDIMMs, respectively, shows
> that DDR5 is not about capacity (no DDR5 LRDIMMs yet, probably for
> lack of corresponding servers).
>
> If they can improve signaling speed enough that DDR5 is insufficient,
> there will be DDR6, offering improved bandwidth. It will be there for
> those who use UDIMMs, those who use RDIMMs, and those who use LRDIMMs.
> And the box you have in mind will have to compete with that.

DRAM stopped scaling a decade ago, RAM will move onto the CPU by the time
DDR6 is out. On CPU RAM will give 10x the RAM bandwidth or more. Look at
the Apple M1 for the future.

>> I rather see it as an opposite - LR-DIMM are in the same boat with those future
>> external boxes. Both serve to extend the usefulness of given generation of
>> DDRn, helping to reduce the necessity of the next generation.
>
> LRDIMMs increase the capacity, but not the bandwidth. But bandwidth
> is the main reason for the next DDR generation.
>
> - anton

On Monday, May 30, 2022 at 7:27:00 PM UTC-5, gg...@yahoo.com wrote:
> Anton Ertl <an...@mips.complang.tuwien.ac.at> wrote:
> > Michael S <already...@yahoo.com> writes:
> >> On Sunday, May 29, 2022 at 7:06:16 PM UTC+3, Anton Ertl wrote:
> >>> Michael S <already...@yahoo.com> writes:
> >>>> On Sunday, May 29, 2022 at 1:14:20 PM UTC+3, Anton Ertl wrote:
> >>>>> Looking at the "RAM type" category in <https://geizhals.eu/?cat=nb>:
> >>>>>
> >>>>> models
> >>>>> 5235 DDR4
> >>>>> 1578 LPDDR4
> >>>>> 154 DDR5
> >>>>> 255 LPDDR5
> >>>>>
> >>>>> So there are certainly many more models with DDR4/5 than with LPDDR4,
> >>>>> and this probably also means more sales.
> >>>>>
> >>>>
> >>>> I'm not sure that it follows.
> >>>> Simple models like Dell Latitude 3320 probably outsel more advanced
> >>>> models by significant factor.
> >>> Maybe. And maybe even cheaper models like, say, the ASUS Business P1
> >>> P1511CEA-BQ749 (offered by 81 dealers vs. 57 for the most-offered Dell
> >>> Latitude 3320 variant)
> >>
> >> Or. may be, even lower end ASUS VivoBook E12
> >
> > Unlikely at the moment, because none are offered. Looking at one
> > model, I see that it was last offered in February 2019.
> >
> >> At very least, we know that according to Gartner estimates Dell PC division
> >> as a whole outsells ASUS PC division as whole, 2.5 to 1. So, fewer dealers,
> >> but more PCs sold by each dealer.
> >> Also, I would think that [at retail] ASUS has many more models than Dell.
> >
> > ASUS Dell
> > 662 468 <https://geizhals.eu/?cat=nb> (Laptops).
> > 61 227 <https://geizhals.eu/?cat=sysdiv> (Systems)
> >
> >> By the way, I don't know how it works in your country, but here Latitude is not
> >> seen in shops at all. Only Inspiron , Vostro and occasional Alienware.
> >> But at work Latitude is everywhere.
> >
> > I don't know how it works in my country, and I don't go to shops
> > looking what brands of laptops they have, but I don't see that many
> > Dells overall when I see other people's laptops. For those that I
> > see, I have no idea what models they are. There's a central
> > laptop/tablet ordering system two times per year from the University
> > of Vienna that my university participates in, and I guess that many
> > people buy laptops through this system; the most recent one was
> > <https://ubook.at/fileadmin/content/broschueren/ubook_sose2022.pdf>.
> > The only Dell Latitude there cost EUR 2239, and I doubt that many
> > people bought it.
> >
> > Anyway, if we assume that Dell sells particularly many laptops, and
> > that we need to study them separately, there the RAM type statistics
> > is:
> >
> > models
> > 362 DDR4
> > 57 LPDDR4
> > 17 DDR5
> > 4 LPDDR5
> >
> > So for Dell laptops the balance is even less in favour of LPDDR4. Do
> > people all buy these 57 LPDDR4 models, and Dell offers the other
> > models just for fun?
> >
> >>>>> [CXL]
> >>>>>> But my point is that people that build this boxen don't need new memory standard
> >>>>>> every 5-7 years. Esp. when capacity does not go up. Even with DDR4 they likely
> >>>>>> have internal bandwidth that easily exceeds bandwidth of their external COMM
> >>>>>> channels, because there is no other way to get required capacity.
> >>>>>> So, if they need DDR5 then only because of promised extra capacity.
> >>>>> A pure memory box with bandwidth that cannot even compete with DDR4 in
> >>>>> bandwidth (and certainly not latency) does not look to me like something
> >>>>> that many people would buy. I doubt that we will see such products.
> >>>>
> >>>> Who says it does not compete with DDR4 in bandwidth?
> >>> You do: "Even with DDR4 they likely have internal bandwidth that
> >>> easily exceeds bandwidth of their external COMM channels".
> >>>
> >>
> >> Hopefully, now you paid attention to qualifiers "internal and "external".
> >>
> >>> As for the rest: A box with more memory than supported by LRDIMMs on,
> >>> e.g., EPYC boards will probably find a market, but I doubt that it
> >>> will replace LRDIMMs.
> >>
> >> It does not have to replace LR-DIMM in order to make DDR6 unnecessary or,
> >> at least, to delay its introduction.
> >
> > Like DDR5, DDR6 will probably be about bandwidth, not capacity. The
> > fact that the largest DDR5 UDIMMs and RDIMMs at the moment are not
> > bigger than the largest DDR4 UDIMMs and RDIMMs, respectively, shows
> > that DDR5 is not about capacity (no DDR5 LRDIMMs yet, probably for
> > lack of corresponding servers).
> >
> > If they can improve signaling speed enough that DDR5 is insufficient,
> > there will be DDR6, offering improved bandwidth. It will be there for
> > those who use UDIMMs, those who use RDIMMs, and those who use LRDIMMs.
> > And the box you have in mind will have to compete with that.
<
> DRAM stopped scaling a decade ago, RAM will move onto the CPU by the time
> DDR6 is out. On CPU RAM will give 10x the RAM bandwidth or more. Look at
> the Apple M1 for the future.
<
DRAM stopped latency scaling a decade ago (or a bit more) density scaling
continues.
<
For most design point, (low) latency is more important than (high) Bandwidth
Which is why DDR[k] is out pf phase with desire.

On 5/30/2022 12:02 PM, MitchAlsup wrote:
> On Monday, May 30, 2022 at 1:05:22 PM UTC-5, Stephen Fuld wrote:
>> On 5/27/2022 1:54 PM, MitchAlsup wrote:
>>> On Friday, May 27, 2022 at 11:58:14 AM UTC-5, Stephen Fuld wrote:
>>>> On 5/27/2022 9:11 AM, Michael S wrote:
>>>>> On Friday, May 27, 2022 at 3:15:03 PM UTC+3, Anton Ertl wrote:
>>>>>> Michael S <already...@yahoo.com> writes:
>>>>>>> On Friday, May 27, 2022 at 10:53:05 AM UTC+3, Anton Ertl wrote:
>>>>>>>> In the long run, the (sub)channels are going to become narrower,=20
>>>>>>>
>>>>>>> You still assume that we are ahead of long run [of Moore law].
>>>>>>> I am less optimistic. I seems plausible that provisions for 64gb devices
>>>>>>> that is already in DDR5 will suffice for more than decade.
>>>>>>> May be, close to 2 decades.
>>>>>> Newer DDR standards are not primarily about chip capacity (currently
>>>>>> the largest DDR5 chips are not larger than supported by DDR4: 16Gb),
>>>>>> but about transfer rate. I.e., if the transfer rate becomes faster
>>>>>> than 16x the internal cycle time of DRAM, they have to increase the
>>>>>> minimum burst length (and decrease the (sub)channel width) to benefit
>>>>>> from that increase. And currently I see no sign that the transfer
>>>>>> rate increases are slowing down. DDR4 was released 7 years after
>>>>>> DDR3; DDR5 was released 6 years after DDR4. On the PCIe front, the
>>>>>> release cadence seems to be even higher.
>>>>>> - anton
>>>>>> --
>>>>>> 'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
>>>>>> Mitch Alsup, <c17fcd89-f024-40e7...@googlegroups.com>
>>>>>
>>>>> I can not formulate it with sufficient rigor, but my opinion is that need
>>>>> in new DDR standards is very much a function of non-stability (hopefully growth)
>>>>> of the market in term of average capacity.
>>> <
>>>> I disagree. If it were true, then newer generations of the standard
>>>> would be much simpler; just add an address bit or two. The fact that
>>>> each standard provides a substantial increase in data rate/bandwidth
>>>> over the previous one, which is harder than adding an address pin, says
>>>> that data rate/bandwidth is the driving factor, and capacity comes in
>>>> second. Unfortunately, latency has proven resistant to substantial
>>>> improvements :-(
>>> <
>>> DRAM chips have rather constant area. Passing over a linear amount of
>>> real-estate is a wire delay problem. So that transistors are getting faster
>>> and wire is getting slower has finally become manifest in DRAM. {actually
>>> DRAM bank access to pin drivers has stayed rather constant since DDR2.}
> <
>> While all of that is true, I think it is only a part of the reason for
>> the long latency. Consider a hypothetical chip of the same physical
>> size as a current DRAM, but instead uses SRAM. Of course, it will have
>> smaller capacity and perhaps require more pins than the DRAM, but I
>> expect it will have lower latency. Is that correct?
> <
> Back in 1998, I designed a DRAM macro for a logic process. The DRAM
> macro had 4× the density of SRAM and only a few picoseconds longer
> access time (in the era of 250-500 MHz processors (4ns-2ns)). So, I take
> issue that DRAM is inherently slower than SRAM. DRAM implemented in
> a DRAM process (moderate P-channels slow N-channels) would not be
> as fast a DRAM implemented in a logic process.

For a while, IBM used embedded DRAM as an L3 cache in some of their
Power and Z series systems, but I think have abandoned it. It always
seemed like a good idea to me, but I wonder why they stopped using it.

--
- Stephen Fuld
(e-mail address disguised to prevent spam)

Brett <ggtgp@yahoo.com> writes:
>DRAM stopped scaling a decade ago,

In 2012 we had DDR3 RAM with up to 8GB/UDIMM (with 4Gb chips) and at
most 2133 MT/s. Today we are switching to DDR5 RAM with currently up
to 32GB/UDIMM (with 16Gb chips) and 4800MT/s or more. What do you
mean with "stop scaling"?

>RAM will move onto the CPU by the time
>DDR6 is out.

Unlikely, because logic processes are different from DRAM processes.

>On CPU RAM will give 10x the RAM bandwidth or more. Look at
>the Apple M1 for the future.

The Apple M1 uses regular LPDDR4X memory; M1 Pro, M1 Max, and M1 Ultra
use regular LPDDR5 memory.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

On Tuesday, May 31, 2022 at 9:02:43 AM UTC+3, Stephen Fuld wrote:
>
> For a while, IBM used embedded DRAM as an L3 cache in some of their
> Power and Z series systems,

One z14 description (IBM z14 Model ZR1 Technical Guide) claims that even L1
cache is eDRAM. I am not sure if it is mistake or true.

> but I think have abandoned it. It always
> seemed like a good idea to me, but I wonder why they stopped using it.
> --
> - Stephen Fuld
> (e-mail address disguised to prevent spam)

The answer to this question is simple: because they no longer make POWER and Z on their own fabs.
Without their specialty trench capacitors on-die eDRAM caches are less attractive.

On Tuesday, May 31, 2022 at 11:02:49 AM UTC+3, Anton Ertl wrote:
> Brett <gg...@yahoo.com> writes:
> >DRAM stopped scaling a decade ago,
> In 2012 we had DDR3 RAM with up to 8GB/UDIMM (with 4Gb chips) and at
> most 2133 MT/s. Today we are switching to DDR5 RAM with currently up
> to 32GB/UDIMM (with 16Gb chips) and 4800MT/s or more. What do you
> mean with "stop scaling"?

While I agree that DRAM scaling didn't stop in last decade (although
it did slowed down) your example does not prove it.
32GB DDR5 UDIMM of today is not an equivalent of 8GB DDR3 UDIMM of 10 years ago.
There is very big (5x ?) price difference between the two which leads to
targeting different segments of the market.
8GB DDR3 UDIMM of 2012 was not exactly a market leader (4 GB UDIMMs were more\
common), but it was sold and bought widely. Unlike 32 GB DDR5 UDIMM today which
is tiny part of the market.

Marcus wrote:
> A few things that I have learned about CPU cores and memory consumption:
>
> 1. With every extra core you want more RAM. Twice the number of cores
> roughly translates to twice the memory requirements. My typical use case
> is parallel compilation (e.g. building LLVM), where each CPU core gets
> its own compiler process, and each process consumes RAM independently of
> the other. For embarrassingly parallel tasks multi-core CPUs are king.
>
> 2. I regularly enough run virtual machines to care about having enough
> RAM to support both a fully working host environment and a working VM
> environment. Usually the VM uses 25-50% of the host RAM, so out of my
> 32 GB RAM I sometimes have to do with 16 GB available RAM when the VM
> is running.

100% agree.

I have had 32 GB RAM (+ 2TB disk, originally spinning rust, now SSD) as
my default laptop size for well over a decade now (4 or 5 different PCs,
from 4 different employers), and I'm only going to change that up, not down.

Terje

--
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"

On 5/31/2022 1:43 AM, Michael S wrote:
> On Tuesday, May 31, 2022 at 9:02:43 AM UTC+3, Stephen Fuld wrote:
>>
>> For a while, IBM used embedded DRAM as an L3 cache in some of their
>> Power and Z series systems,
>
> One z14 description (IBM z14 Model ZR1 Technical Guide) claims that even L1
> cache is eDRAM. I am not sure if it is mistake or true.
>
>> but I think have abandoned it. It always
>> seemed like a good idea to me, but I wonder why they stopped using it.
>> --
>> - Stephen Fuld
>> (e-mail address disguised to prevent spam)
>
> The answer to this question is simple: because they no longer make POWER and Z on their own fabs.
> Without their specialty trench capacitors on-die eDRAM caches are less attractive.

That makes sense. Thanks.

--
- Stephen Fuld
(e-mail address disguised to prevent spam)

Michael S <already5chosen@yahoo.com> writes:
>On Tuesday, May 31, 2022 at 11:02:49 AM UTC+3, Anton Ertl wrote:
>> Brett <gg...@yahoo.com> writes:
>> >DRAM stopped scaling a decade ago,
>> In 2012 we had DDR3 RAM with up to 8GB/UDIMM (with 4Gb chips) and at
>> most 2133 MT/s. Today we are switching to DDR5 RAM with currently up
>> to 32GB/UDIMM (with 16Gb chips) and 4800MT/s or more. What do you
>> mean with "stop scaling"?
>
>While I agree that DRAM scaling didn't stop in last decade (although
>it did slowed down) your example does not prove it.
>32GB DDR5 UDIMM of today is not an equivalent of 8GB DDR3 UDIMM of 10 years ago.
>There is very big (5x ?) price difference between the two which leads to
>targeting different segments of the market.

I found an 8GB DDR-2133 DIMM that was on the market in 2012:

<https://geizhals.eu/?phist=659067&age=9999>

A 32GB DDR5-4800 DIMM is about 3 times more expensive.

I don't think they target different segments of the markets. If you
wanted a top DIMM in 2012, you bought something like that (no bigger
and faster UDIMMs were available), and if you want to buy a big and
fast UDIMM today, you buy a 32GB DIMM, and if you want it for an Alder
Lake system, you probably go for DDR5 instead of DDR4. If you are
really going for the top, DDR5-4800 may be too slow for you despite
its high price.

>8GB DDR3 UDIMM of 2012 was not exactly a market leader (4 GB UDIMMs were more\
>common), but it was sold and bought widely. Unlike 32 GB DDR5 UDIMM today which
>is tiny part of the market.

Given the price difference, sure. Supposedly the retail price of DDR5
DIMMs reflects the current scarcity of the power management chips on
these DIMMs, the price of 32GB DDR4 may better reflect the fundamental
costs; looking at

<https://geizhals.eu/?cat=ramddr3&xf=15903_DDR4&sort=r#productlist>

the second-cheapest (EUR/GB) DIMM is a 32GB DDR4-2666 DIMM, and the
cheapest DDR4-3200 DIMM is 32GB in size, so 16Gb chips/32GB DIMMs seem
to have the lowest cost/bit.

So in terms of Moore's law, the 16Gb DDR4 chips are the relevant chips
at this point in time. However, ten years ago it was more than 0.5Gb,
so the scaling was slower than the 2 years per doubling that has
occasionally been claimed to be Moore's law, and certainly slower than
the 18 months per doubling that Moore stated in his 1975 paper.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>