THEGODDESSOFTHENETHASTWISTINGFINGERSANDHERVOICEISLIKEAJAVELININTHENIGHTDUDE
Subject: Bit Swizzling
From: Rick C. HodginNewsgroups: comp.lang.c, comp.arch, comp.arch.fpga, comp.lang.asm.x86
Organization: Liberty Software Foundation
Date: Sat, 5 Sep 2020 00:33 UTC
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I'm not sure where to ask this question, so I pushed it out to several
groups. You need not reply to all of them if you don't think it is a
topical subject.
I included comp.compilers in a previous message, but it apparently holds
the message until it passes moderation. So, I've not included it here.
A duplicate message may post if/when the comp.compilers moderator John
Levine approves it.

Are there any algorithms which take a knownatcompiletime sequence
of bitwise operations on an 8bit to 64bit quantity, and optimize
them down to their minimal set of operations?
For example, if I have an 8bit byte and I want to swizzle the bits
thusly:
Input: 07 06 05 04 03 02 01 00
Output: 05 04 07 02 01 03 00 06
I can easily swizzle the data using a brute force method:
v = get_value();
o = 0;
swizzle1(o, v, 0, 6);
swizzle1(o, v, 1, 0);
swizzle1(o, v, 2, 3);
swizzle1(o, v, 3, 1);
swizzle1(o, v, 4, 2);
swizzle1(o, v, 5, 7);
swizzle1(o, v, 6, 4);
swizzle1(o, v, 7, 5);
// Untested, off the top of my head
void swizzle(unsigned char& o, unsigned char v, int s, int d)
{
o = (((v & (1 << s)) >> s) << d);
}
And, of course, that algorithm can be optimized based on relative
values of s and d, and if s is 0, etc.
However, there also exists a minimal set of steps to complete that
swizzling because in the operation above, bits 5 and 4 are used in
sequence. It could be done using a swizzle2() operation, for example
and handle 2 bits at a time.
Are there any existing algorithms which examine the operations that
must be conducted and the optimized / minimal sequence of steps to
conduct it?
Thank you in advance.

Rick C. Hodgin
Subject: Re: Bit Swizzling
From: MitchAlsupNewsgroups: comp.arch
Date: Sat, 5 Sep 2020 01:26 UTC
References: 1
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On Friday, September 4, 2020 at 7:44:20 PM UTC5, Rick C. Hodgin wrote:
I'm not sure where to ask this question, so I pushed it out to several
groups. You need not reply to all of them if you don't think it is a
topical subject.
I included comp.compilers in a previous message, but it apparently holds
the message until it passes moderation. So, I've not included it here.
A duplicate message may post if/when the comp.compilers moderator John
Levine approves it.

Are there any algorithms which take a knownatcompiletime sequence
of bitwise operations on an 8bit to 64bit quantity, and optimize
them down to their minimal set of operations?
For example, if I have an 8bit byte and I want to swizzle the bits
thusly:
Input: 07 06 05 04 03 02 01 00
Output: 05 04 07 02 01 03 00 06
I can easily swizzle the data using a brute force method:
v = get_value();
o = 0;
swizzle1(o, v, 0, 6);
swizzle1(o, v, 1, 0);
swizzle1(o, v, 2, 3);
swizzle1(o, v, 3, 1);
swizzle1(o, v, 4, 2);
swizzle1(o, v, 5, 7);
swizzle1(o, v, 6, 4);
swizzle1(o, v, 7, 5);
// Untested, off the top of my head
void swizzle(unsigned char& o, unsigned char v, int s, int d)
The input variable s should be a for loop inside of the swizzle function.
The input variable d should be consumed as part of running the for loop.
The constant 1 I think should be 15 or 0xF
{
o = (((v & (1 << s)) >> s) << d);
}
And, of course, that algorithm can be optimized based on relative
values of s and d, and if s is 0, etc.
However, there also exists a minimal set of steps to complete that
swizzling because in the operation above, bits 5 and 4 are used in
sequence. It could be done using a swizzle2() operation, for example
and handle 2 bits at a time.
Are there any existing algorithms which examine the operations that
must be conducted and the optimized / minimal sequence of steps to
conduct it?
Thank you in advance.

Rick C. Hodgin
The Hardware answer is that swizzle is simply a multiplexer with k inputs
of size j such that j×k = bitsinregister. With the number of bits in a
register a power of 2, K will also be a power of 2, and j a logarithm of
a power of 2.
For a 64bit register and a byte swizzler, one needs eight 8bit multiplexers
and eight 3bit multiplex indexes (or a 8×3 = 24bit constant)
The One I put in the Samsung GPU ISA used 32bit registers and 4bit swizzle
sizes; so we still had 8 multiplexers and the index count was still 3bits.
The inputs could be from a constant field or from a register.
In both cases any given multiplexer produces a fixed number of bits at a
fixed position in the output. This is actually faster than a shift or
add (because the depth of the multiplexer is thinner at 2gates of delay).
Swizzle can also be used to perform various SMEAR activities:
0404040404040404 = SWIZZLE( 0706050403020100, 44444444 );
The problem in SW is that the native register sizes are "all wrong" so
on has to compute and paste.
unit64_t swizzle( uint64_t container, uint32_t indexer )
{
uint64_t out = 0;
for( uint64_t i = 0; i < 64; i += 8, indexer >>= 4 )
out = ((container >> (indexer & 15)) & 256) << i;
return out;
}
Subject: Re: Bit Swizzling
From: MitchAlsupNewsgroups: comp.arch
Date: Sat, 5 Sep 2020 01:27 UTC
References: 1 2
View all headers
On Friday, September 4, 2020 at 8:26:30 PM UTC5, MitchAlsup wrote:
On Friday, September 4, 2020 at 7:44:20 PM UTC5, Rick C. Hodgin wrote:
I'm not sure where to ask this question, so I pushed it out to several
groups. You need not reply to all of them if you don't think it is a
topical subject.
I included comp.compilers in a previous message, but it apparently holds
the message until it passes moderation. So, I've not included it here.
A duplicate message may post if/when the comp.compilers moderator John
Levine approves it.

Are there any algorithms which take a knownatcompiletime sequence
of bitwise operations on an 8bit to 64bit quantity, and optimize
them down to their minimal set of operations?
For example, if I have an 8bit byte and I want to swizzle the bits
thusly:
Input: 07 06 05 04 03 02 01 00
Output: 05 04 07 02 01 03 00 06
I can easily swizzle the data using a brute force method:
v = get_value();
o = 0;
swizzle1(o, v, 0, 6);
swizzle1(o, v, 1, 0);
swizzle1(o, v, 2, 3);
swizzle1(o, v, 3, 1);
swizzle1(o, v, 4, 2);
swizzle1(o, v, 5, 7);
swizzle1(o, v, 6, 4);
swizzle1(o, v, 7, 5);
// Untested, off the top of my head
void swizzle(unsigned char& o, unsigned char v, int s, int d)
The input variable s should be a for loop inside of the swizzle function.
The input variable d should be consumed as part of running the for loop.
The constant 1 I think should be 15 or 0xF
{
o = (((v & (1 << s)) >> s) << d);
}
And, of course, that algorithm can be optimized based on relative
values of s and d, and if s is 0, etc.
However, there also exists a minimal set of steps to complete that
swizzling because in the operation above, bits 5 and 4 are used in
sequence. It could be done using a swizzle2() operation, for example
and handle 2 bits at a time.
Are there any existing algorithms which examine the operations that
must be conducted and the optimized / minimal sequence of steps to
conduct it?
Thank you in advance.

Rick C. Hodgin
The Hardware answer is that swizzle is simply a multiplexer with k inputs
of size j such that j×k = bitsinregister. With the number of bits in a
register a power of 2, K will also be a power of 2, and j a logarithm of
a power of 2.
For a 64bit register and a byte swizzler, one needs eight 8bit multiplexers
and eight 3bit multiplex indexes (or a 8×3 = 24bit constant)
The One I put in the Samsung GPU ISA used 32bit registers and 4bit swizzle
sizes; so we still had 8 multiplexers and the index count was still 3bits.
The inputs could be from a constant field or from a register.
In both cases any given multiplexer produces a fixed number of bits at a
fixed position in the output. This is actually faster than a shift or
add (because the depth of the multiplexer is thinner at 2gates of delay)..
Swizzle can also be used to perform various SMEAR activities:
0404040404040404 = SWIZZLE( 0706050403020100, 44444444 );
The problem in SW is that the native register sizes are "all wrong" so
on has to compute and paste.
unit64_t swizzle( uint64_t container, uint32_t indexer )
{
uint64_t out = 0;
for( uint64_t i = 0; i < 64; i += 8, indexer >>= 4 )
out = ((container >> (indexer & 15)) & 256) << i;
return out;
}
Make that 255 instead of 256.......
Subject: Re: Bit Swizzling
From: Joshua LandauNewsgroups: comp.arch
Date: Sat, 5 Sep 2020 03:32 UTC
References: 1
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On Saturday, 5 September 2020 at 01:44:20 UTC+1, Rick C. Hodgin wrote:
I'm not sure where to ask this question, so I pushed it out to several
groups. You need not reply to all of them if you don't think it is a
topical subject.
I included comp.compilers in a previous message, but it apparently holds
the message until it passes moderation. So, I've not included it here.
A duplicate message may post if/when the comp.compilers moderator John
Levine approves it.

Are there any algorithms which take a knownatcompiletime sequence
of bitwise operations on an 8bit to 64bit quantity, and optimize
them down to their minimal set of operations?
For example, if I have an 8bit byte and I want to swizzle the bits
thusly:
Input: 07 06 05 04 03 02 01 00
Output: 05 04 07 02 01 03 00 06
I can easily swizzle the data using a brute force method:
v = get_value();
o = 0;
swizzle1(o, v, 0, 6);
swizzle1(o, v, 1, 0);
swizzle1(o, v, 2, 3);
swizzle1(o, v, 3, 1);
swizzle1(o, v, 4, 2);
swizzle1(o, v, 5, 7);
swizzle1(o, v, 6, 4);
swizzle1(o, v, 7, 5);
// Untested, off the top of my head
void swizzle(unsigned char& o, unsigned char v, int s, int d)
{
o = (((v & (1 << s)) >> s) << d);
}
And, of course, that algorithm can be optimized based on relative
values of s and d, and if s is 0, etc.
However, there also exists a minimal set of steps to complete that
swizzling because in the operation above, bits 5 and 4 are used in
sequence. It could be done using a swizzle2() operation, for example
and handle 2 bits at a time.
Are there any existing algorithms which examine the operations that
must be conducted and the optimized / minimal sequence of steps to
conduct it?
For an 8 bit value there's a quick method.
Start with abcdefgh
PDEP to get 0000000a0000000b0000000c0000000d0000000e0000000f0000000g0000000h
Multiply by an appropriate 64 bit constant to get the values in the high bits; in your example 0x20_01_80_40_04_10_08_02
Shift down by 56.
If your value is 64 bit, you can instead do
(x >> 0) & 0x0101010101010101
(x >> 1) & 0x0101010101010101
....
(x >> 7) & 0x0101010101010101
to get your strided inputs, perform a multiplication on each to get the wanted ordering of those 8 bits,
and then PDEP each into place. The overall cost is 15 shifts, 8 ands, 8 muls, 8 PDEPs and 7 ors,
with a critical path of shiftandmulshiftpdepororor.
I can think of more optimal sequences for specialcases.
Subject: Re: Bit Swizzling
From: BartNewsgroups: comp.lang.c, comp.arch, comp.arch.fpga, comp.lang.asm.x86
Organization: virginmedia.com
Date: Sat, 5 Sep 2020 11:33 UTC
References: 1
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On 05/09/2020 01:33, Rick C. Hodgin wrote:

Are there any algorithms which take a knownatcompiletime sequence
of bitwise operations on an 8bit to 64bit quantity, and optimize
them down to their minimal set of operations?
For example, if I have an 8bit byte and I want to swizzle the bits
thusly:
Input: 07 06 05 04 03 02 01 00
Output: 05 04 07 02 01 03 00 06
If it's just 8bit bytes, then it's easy: use any method to build a map that translates one 8bit value to its swizzled version. I assume it will be used many millions of times.
I can easily swizzle the data using a brute force method:
v = get_value();
o = 0;
swizzle1(o, v, 0, 6);
swizzle1(o, v, 1, 0);
swizzle1(o, v, 2, 3);
swizzle1(o, v, 3, 1);
swizzle1(o, v, 4, 2);
swizzle1(o, v, 5, 7);
swizzle1(o, v, 6, 4);
swizzle1(o, v, 7, 5);
// Untested, off the top of my head
void swizzle(unsigned char& o, unsigned char v, int s, int d)
{
o = (((v & (1 << s)) >> s) << d);
}
It took me a while to figure out what this means, which appears to be take bit s of v, and store it as bit d of o. (But o has to start at 0 since = means it can't change a 1 in o to 0.)
In my language it would be simply this:
o.[d] := v.[s]
although there, it can write both 1s and 0s into o.
And, of course, that algorithm can be optimized based on relative
values of s and d, and if s is 0, etc.
However, there also exists a minimal set of steps to complete that
swizzling because in the operation above, bits 5 and 4 are used in
sequence. It could be done using a swizzle2() operation, for example
and handle 2 bits at a time.
Are there any existing algorithms which examine the operations that
must be conducted and the optimized / minimal sequence of steps to
conduct it?
The algorithm that works on what, bits of C++ code? What is its input? What are the aims: to make it fast? Will the mapping always be known constants, or variables? Will all bits be translated or just some?
And, what would be its output?
If it's just reordering the bits in a word (where you don't map, for example, both bits 5 and 7 to bit 3), that doesn't sound too hard (although it probably is!). But importantly, this isn't done inplace.
Up to 8 or 16 bits, probably you can use tables, but the tables need to be set up.
Otherwise the simplest thing I can think of, for an Nbit word, is a table of translation pairs. For your 8bit example this will just be the parameters to your swizzle function, but as data:
(0,6)
(1,0)
(2,3)
(3,1)
(4,2)
(5,7)
(6,4)
(7,5)
This be input to a routine that will do the job, or it can be the input to an algorithem that generates, for example, one giant logical expression.
I can probably just about do that last part, if it doesn't need to be optimised, example:
y = ((x&1)<<6)((x&2)>>1)((x&4)<<1)((x&8)>>2)
((x&16)>>2)((x&32)<<2)((x&64)>>2)((x&128)>>2);
where x is the input word, and y is the output word. I did this with a 12line script based on that data input. (Not tested; may need extra parens.)
I'm sure gccO3 will find some optimisations in there if there are any.
Subject: Re: Bit Swizzling
From: ChrisNewsgroups: comp.arch
Organization: Aioe.org NNTP Server
Date: Sat, 5 Sep 2020 12:12 UTC
References: 1
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On 09/05/20 01:33, Rick C. Hodgin wrote:
I'm not sure where to ask this question, so I pushed it out to several
groups. You need not reply to all of them if you don't think it is a
topical subject.
I included comp.compilers in a previous message, but it apparently holds
the message until it passes moderation. So, I've not included it here.
A duplicate message may post if/when the comp.compilers moderator John
Levine approves it.

Are there any algorithms which take a knownatcompiletime sequence
of bitwise operations on an 8bit to 64bit quantity, and optimize
them down to their minimal set of operations?
For example, if I have an 8bit byte and I want to swizzle the bits
thusly:
Input: 07 06 05 04 03 02 01 00
Output: 05 04 07 02 01 03 00 06
I can easily swizzle the data using a brute force method:
v = get_value();
o = 0;
swizzle1(o, v, 0, 6);
swizzle1(o, v, 1, 0);
swizzle1(o, v, 2, 3);
swizzle1(o, v, 3, 1);
swizzle1(o, v, 4, 2);
swizzle1(o, v, 5, 7);
swizzle1(o, v, 6, 4);
swizzle1(o, v, 7, 5);
// Untested, off the top of my head
void swizzle(unsigned char& o, unsigned char v, int s, int d)
{
o = (((v & (1 << s)) >> s) << d);
}
And, of course, that algorithm can be optimized based on relative
values of s and d, and if s is 0, etc.
However, there also exists a minimal set of steps to complete that
swizzling because in the operation above, bits 5 and 4 are used in
sequence. It could be done using a swizzle2() operation, for example
and handle 2 bits at a time.
Are there any existing algorithms which examine the operations that
must be conducted and the optimized / minimal sequence of steps to
conduct it?
Thank you in advance.
Why not just use a lookup table ?. Minimum ops and fast...
Chris
Subject: Re: Bit Swizzling
From: Rick C. HodginNewsgroups: comp.arch
Organization: Liberty Software Foundation
Date: Sat, 5 Sep 2020 13:16 UTC
References: 1 2
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On 9/4/20 11:32 PM, Joshua Landau wrote:
For an 8 bit value there's a quick method.
Start with abcdefgh
PDEP to get 0000000a0000000b0000000c0000000d0000000e0000000f0000000g0000000h
Multiply by an appropriate 64 bit constant to get the values in the high bits; in your example 0x20_01_80_40_04_10_08_02
Shift down by 56.
That's a good one when parallel ops are available. Fast, and it doesn't
require much overhead. I like it.
If your value is 64 bit, you can instead do
(x >> 0) & 0x0101010101010101
(x >> 1) & 0x0101010101010101
...
(x >> 7) & 0x0101010101010101
to get your strided inputs, perform a multiplication on each to get the wanted ordering of those 8 bits,
and then PDEP each into place. The overall cost is 15 shifts, 8 ands, 8 muls, 8 PDEPs and 7 ors,
with a critical path of shiftandmulshiftpdepororor.
I can think of more optimal sequences for specialcases.
For an optimal software algorithm where only logical bitwise operators
are available on 8bit, 16bit, 32bit, or 64bit quantities, I'm going
to have to bruteforce the logic through using bit identifiers in bytes,
and then do an analysis to see if any sequences exist in the destination
which match the source, and then extract out those components and
iteratively resolve down until the operation is exhausted with other
manual steps.
I was hoping this was a solved problem that is wellknown with easyto
read C code taught in CS 351 or something where I could garner and
adapt their welldocumented code. :)

Rick C. Hodgin
Subject: Re: Bit Swizzling
From: John LevineNewsgroups: comp.arch, comp.compilers
Organization: Taughannock Networks
Date: Sat, 5 Sep 2020 18:50 UTC
References: 1 2 3 View all headers
In article <rivvah$1neg$2@gioia.aioe.org>,

Are there any algorithms which take a knownatcompiletime sequence
of bitwise operations on an 8bit to 64bit quantity, and optimize
them down to their minimal set of operations?
Why not just use a lookup table ?. Minimum ops and fast...
Assuming you're looking for something you can implement in logic
rather than by table lookup, it sounds like a set of Karnaugh maps.

Regards,
John Levine, johnl@taugh.com, Primary Perpetrator of "The Internet for Dummies",
Please consider the environment before reading this email.
https://jl.ly
Subject: Re: Bit Swizzling
From: Rick C. HodginNewsgroups: comp.arch
Organization: Liberty Software Foundation
Date: Sun, 6 Sep 2020 15:01 UTC
References: 1 2 3 4
View all headers
On 9/5/20 2:50 PM, John Levine wrote:
> Assuming you're looking for something you can implement in logic
> rather than by table lookup...
Correct.
I'm looking for an algorithm to analyze bit swizzling requirements and
generate optimal code for them given the capabilities and constraints of
various ISAs.
> it sounds like a set of Karnaugh maps
This is part of my CAlive project. I'm looking for an algorithm which
already has the logic worked out, rather than (re)inventing myself.
Note: I originally crossposted this to comp.compilers yesterday, but
John Levine did not allow it to post. I reply here only to the
other group he crossposted to originally, comp.arch.

Rick C. Hodgin
Subject: Re: Bit Swizzling
From: ChrisNewsgroups: comp.arch, comp.compilers
Organization: Aioe.org NNTP Server
Date: Sun, 6 Sep 2020 16:48 UTC
References: 1 2 3 4 View all headers
On 09/05/20 19:50, John Levine wrote:
In article<rivvah$1neg$2@gioia.aioe.org>,

Are there any algorithms which take a knownatcompiletime sequence
of bitwise operations on an 8bit to 64bit quantity, and optimize
them down to their minimal set of operations?
Why not just use a lookup table ?. Minimum ops and fast...
Assuming you're looking for something you can implement in logic
rather than by table lookup, it sounds like a set of Karnaugh maps.
Unless this is just an intellectual exercise for the fun of it, an
engineer would choose the minimal design at lowest cost to
satisfy the requirements. Table methods don't have to be in
software as a single eprom or gate array could do it in hardware.
8 inputs to address lines, then 8 bits of output, scale as required,
so why make life more difficult than necessary ?.
Old project here, where a programmer spent nearly 5 pages of 6800
asm to translate an input connect pin layout to that required for
the internal functions. Code was impenetrable, so substituted a
256 byte lookup table. Less space that the code and easily
modified for new requirements...
Chris
[I think the question is whether there is a way to mechanically
generate a version of the opaque assembler. John]
Subject: Re: Operand forwarding: complexity and limits
From: EricPNewsgroups: comp.arch
Date: Tue, 8 Sep 2020 16:12 UTC
References: 1 2 3 4
View all headers
Ivan Godard wrote:
On 9/7/2020 6:25 PM, EricP wrote:
 operand_bus

 
v v 
mux 
v 
Res_Stn_FF 
v 
tristate_bus 
v v ^
fast_path_mux 
 
v 
FU_operand 
v 
FU_result_FF 
v 
 result_bus
How is this different from an accumulator? (said by an ignorant software type)
Ideally you want dependent operations performed on the same or separate
function units to not stall for 1 clock because of the delay
in propagating a prior result all the way through all that logic.
Not shown on the diagram are multiple result/bypass buses,
multiple function units each with multiple reservation stations.
So there is more logic in the paths than shown.
This was me looking for a way to have my cake and eat it too,
having the operand muxes and reservation station logic be present,
but not totally paying for it in critical path delay.
Ultimately it may not be possible to avoid since wire delay would dominate.
Or maybe its only possible for operations within a single FU like ALU.
So A+B+C can be backtoback but A*B+C has to stall 1 extra clock while
the result moves from the MUL unit to ALU unit. But that could also
impact loads and stores so the cost is going to add up quick.
Subject: Re: Bit Swizzling
From: olcottNewsgroups: comp.lang.c, comp.arch, comp.arch.fpga, comp.lang.asm.x86
Organization: A noiseless patient Spider
Date: Tue, 8 Sep 2020 16:50 UTC
References: 1 2
View all headers
On 9/8/2020 11:25 AM, olcott wrote:
On 9/4/2020 7:33 PM, Rick C. Hodgin wrote:
I'm not sure where to ask this question, so I pushed it out to several
groups. You need not reply to all of them if you don't think it is a
topical subject.
I included comp.compilers in a previous message, but it apparently holds
the message until it passes moderation. So, I've not included it here.
A duplicate message may post if/when the comp.compilers moderator John
Levine approves it.

Are there any algorithms which take a knownatcompiletime sequence
of bitwise operations on an 8bit to 64bit quantity, and optimize
them down to their minimal set of operations?
For example, if I have an 8bit byte and I want to swizzle the bits
thusly:
Input: 07 06 05 04 03 02 01 00
Output: 05 04 07 02 01 03 00 06
I can easily swizzle the data using a brute force method:
v = get_value();
o = 0;
swizzle1(o, v, 0, 6);
swizzle1(o, v, 1, 0);
swizzle1(o, v, 2, 3);
swizzle1(o, v, 3, 1);
swizzle1(o, v, 4, 2);
swizzle1(o, v, 5, 7);
swizzle1(o, v, 6, 4);
swizzle1(o, v, 7, 5);
// Untested, off the top of my head
void swizzle(unsigned char& o, unsigned char v, int s, int d)
{
o = (((v & (1 << s)) >> s) << d);
}
And, of course, that algorithm can be optimized based on relative
values of s and d, and if s is 0, etc.
However, there also exists a minimal set of steps to complete that
swizzling because in the operation above, bits 5 and 4 are used in
sequence. It could be done using a swizzle2() operation, for example
and handle 2 bits at a time.
Are there any existing algorithms which examine the operations that
must be conducted and the optimized / minimal sequence of steps to
conduct it?
Thank you in advance.
https://www.techopedia.com/definition/22413/swizzling
glTexParameteri(Target, GL_TEXTURE_SWIZZLE_R, Format.Swizzle[0]);
glTexParameteri(Target, GL_TEXTURE_SWIZZLE_G, Format.Swizzle[1]);
glTexParameteri(Target, GL_TEXTURE_SWIZZLE_B, Format.Swizzle[2]);
glTexParameteri(Target, GL_TEXTURE_SWIZZLE_A, Format.Swizzle[3]);
https://gli.gtruc.net/0.7.0/index.html

Copyright 2020 Pete Olcott
rocksolid light 0.7.2
clearneti2ptor