Hi,
Intel ModelSim Starter Edition is available free now!

https://fpgasoftware.intel.com/

10,000 line code limit, VHDL-2002 version, running speed is very very slow, but it is enough for debugging grammars. It needs to take 3 hours to download Starter Edition part 1 and part 2 of 7.3G, regardless of how your download speed is.

Weng

On 24/05/2021 12:21, W TX wrote:

Hi Weng,

> Hi,
> Intel ModelSim Starter Edition is available free now!

The starter edition has always been free, this is not the same as the
FPGA edition which cost $1995.

>
> https://fpgasoftware.intel.com/
>
> 10,000 line code limit, VHDL-2002 version, running speed is very very slow, but it is enough for debugging grammars. It needs to take 3 hours to download Starter Edition part 1 and part 2 of 7.3G, regardless of how your download speed is.

It also supports VHDL2008. The speed is about 40% of the full Modelsim
PE/DE edition until you hit the instance limit then the simulation
grinds to a halt (1% speed of PE/DE).

There are other OEM releases which might give you some extra capacity if
you don't care about the vendor libraries, check out the Lattice and
MicroChip versions.

Hans
www.ht-lab.com

>
> Weng
>

On Monday, May 24, 2021 at 5:37:24 AM UTC-7, HT-Lab wrote:
> On 24/05/2021 12:21, W TX wrote:
>
> Hi Weng,
> > Hi,
> > Intel ModelSim Starter Edition is available free now!
> The starter edition has always been free, this is not the same as the
> FPGA edition which cost $1995.
> >
> > https://fpgasoftware.intel.com/
> >
> > 10,000 line code limit, VHDL-2002 version, running speed is very very slow, but it is enough for debugging grammars. It needs to take 3 hours to download Starter Edition part 1 and part 2 of 7.3G, regardless of how your download speed is.
> It also supports VHDL2008. The speed is about 40% of the full Modelsim
> PE/DE edition until you hit the instance limit then the simulation
> grinds to a halt (1% speed of PE/DE).
>
> There are other OEM releases which might give you some extra capacity if
> you don't care about the vendor libraries, check out the Lattice and
> MicroChip versions.
>
> Hans
> www.ht-lab.com
>
>
> >
> > Weng
> >
Hi Hans,

How to set up for VHDL-2008 for the Intel Starter edition? If it can be used for VHDL-2008, it will be great! Your information has great value to me.

I don't care about the vendor library. What their enhancement is?

Weng

On 24/05/2021 15:43, W TX wrote:
> On Monday, May 24, 2021 at 5:37:24 AM UTC-7, HT-Lab wrote:
>> On 24/05/2021 12:21, W TX wrote:
>>
...snip
>>>
> Hi Hans,

Hi Weng
>
> How to set up for VHDL-2008 for the Intel Starter edition? If it can be used for VHDL-2008, it will be great! Your information has great value to me.

There is documentation ;-)

vcom -help all
vcom -2008

> I don't care about the vendor library. What their enhancement is?

You need these if you want to instantiate primitives(buffer, PLL,..) in
your design and if you want to use pre-generated optimised IP block
(FIFO, Cordic,..).

>
> Weng
>
,

Regards,
Hans.
www.ht-lab.com

On Monday, May 24, 2021 at 11:10:42 AM UTC-7, HT-Lab wrote:
> On 24/05/2021 15:43, W TX wrote:
> > On Monday, May 24, 2021 at 5:37:24 AM UTC-7, HT-Lab wrote:
> >> On 24/05/2021 12:21, W TX wrote:
> >>
> ..snip
> >>>
> > Hi Hans,
>
> Hi Weng
> >
> > How to set up for VHDL-2008 for the Intel Starter edition? If it can be used for VHDL-2008, it will be great! Your information has great value to me.
> There is documentation ;-)
>
> vcom -help all
> vcom -2008
> > I don't care about the vendor library. What their enhancement is?
> You need these if you want to instantiate primitives(buffer, PLL,..) in
> your design and if you want to use pre-generated optimised IP block
> (FIFO, Cordic,..).
>
> >
> > Weng
> >
> ,
>
>
> Regards,
> Hans.
> www.ht-lab.com

Hi Hans,
Even I have used ModelSim for more than 20 years, but I never know and use any command lines. Your information is of great value to me.

I entered vcom -2008 before synthesizing everything, but it still failed to show 2008 features (an output port cannot be used internally.

How can I compile all or selective parts with -2008? Please list a few command lines for me.

Than you.

Weng

On Monday, May 24, 2021 at 3:28:28 PM UTC-7, Tianxiang Weng wrote:
> On Monday, May 24, 2021 at 11:10:42 AM UTC-7, HT-Lab wrote:
> > On 24/05/2021 15:43, W TX wrote:
> > > On Monday, May 24, 2021 at 5:37:24 AM UTC-7, HT-Lab wrote:
> > >> On 24/05/2021 12:21, W TX wrote:
> > >>
> > ..snip
> > >>>
> > > Hi Hans,
> >
> > Hi Weng
> > >
> > > How to set up for VHDL-2008 for the Intel Starter edition? If it can be used for VHDL-2008, it will be great! Your information has great value to me.
> > There is documentation ;-)
> >
> > vcom -help all
> > vcom -2008
> > > I don't care about the vendor library. What their enhancement is?
> > You need these if you want to instantiate primitives(buffer, PLL,..) in
> > your design and if you want to use pre-generated optimised IP block
> > (FIFO, Cordic,..).
> >
> > >
> > > Weng
> > >
> > ,
> >
> >
> > Regards,
> > Hans.
> > www.ht-lab.com
> Hi Hans,
> Even I have used ModelSim for more than 20 years, but I never know and use any command lines. Your information is of great value to me.
>
> I entered vcom -2008 before synthesizing everything, but it still failed to show 2008 features (an output port cannot be used internally.
>
> How can I compile all or selective parts with -2008? Please list a few command lines for me.
>
> Than you.
>
> Weng

Hi Hans,

I changed the file parameter from VHDL93 = 2002 to VHDL93 = 2008 at *.mpf, it still shows errors related to VHDL-2008: cannot read output port "Error_O". I used the feather of 2008 to test if I can use 2008. It seems that Starter Edition has shut down the 2008 functions.

I think you may not really use Starter Edition once. It is natural for the Starter Edition not to include 2008 advanced features.

I tried to change another feature at *mpf file:

; Show source line containing error. Default is off.
Show_source = 1

After the change, It still does not show the source code.

I am waiting for your answer. I write all my code in VHDL-2008, and I spent the last several days changing it back to VHDL-2002, and the work is half-finished now. It seems to me that I have to continue my coding in agreement with VHDL-2002.

Thank you.

Weng

On Monday, May 24, 2021 at 4:15:35 PM UTC-7, Tianxiang Weng wrote:
> On Monday, May 24, 2021 at 3:28:28 PM UTC-7, Tianxiang Weng wrote:
> > On Monday, May 24, 2021 at 11:10:42 AM UTC-7, HT-Lab wrote:
> > > On 24/05/2021 15:43, W TX wrote:
> > > > On Monday, May 24, 2021 at 5:37:24 AM UTC-7, HT-Lab wrote:
> > > >> On 24/05/2021 12:21, W TX wrote:
> > > >>
> > > ..snip
> > > >>>
> > > > Hi Hans,
> > >
> > > Hi Weng
> > > >
> > > > How to set up for VHDL-2008 for the Intel Starter edition? If it can be used for VHDL-2008, it will be great! Your information has great value to me.
> > > There is documentation ;-)
> > >
> > > vcom -help all
> > > vcom -2008
> > > > I don't care about the vendor library. What their enhancement is?
> > > You need these if you want to instantiate primitives(buffer, PLL,..) in
> > > your design and if you want to use pre-generated optimised IP block
> > > (FIFO, Cordic,..).
> > >
> > > >
> > > > Weng
> > > >
> > > ,
> > >
> > >
> > > Regards,
> > > Hans.
> > > www.ht-lab.com
> > Hi Hans,
> > Even I have used ModelSim for more than 20 years, but I never know and use any command lines. Your information is of great value to me.
> >
> > I entered vcom -2008 before synthesizing everything, but it still failed to show 2008 features (an output port cannot be used internally.
> >
> > How can I compile all or selective parts with -2008? Please list a few command lines for me.
> >
> > Than you.
> >
> > Weng
> Hi Hans,
>
> I changed the file parameter from VHDL93 = 2002 to VHDL93 = 2008 at *..mpf, it still shows errors related to VHDL-2008: cannot read output port "Error_O". I used the feather of 2008 to test if I can use 2008. It seems that Starter Edition has shut down the 2008 functions.
>
> I think you may not really use Starter Edition once. It is natural for the Starter Edition not to include 2008 advanced features.
>
> I tried to change another feature at *mpf file:
>
> ; Show source line containing error. Default is off.
> Show_source = 1
>
> After the change, It still does not show the source code.
>
> I am waiting for your answer. I write all my code in VHDL-2008, and I spent the last several days changing it back to VHDL-2002, and the work is half-finished now. It seems to me that I have to continue my coding in agreement with VHDL-2002.
>
> Thank you.
>
> Weng

Sorry,

I found an error in my last post:

I changed another feature at *mpf file:
Show source line containing error. Default is off.
> Show_source = 1

After the change, It does show the source code.

Weng

On 25/05/2021 06:18, Tianxiang Weng wrote:
...
>>
>> Thank you.
>>
>> Weng
>
> Sorry,
>
> I found an error in my last post:
>
> I changed another feature at *mpf file:
> Show source line containing error. Default is off.
>> Show_source = 1
>
> After the change, It does show the source code.
>
> Weng
>

Hi Weng,

VHDL2008 is definitely supported. The OEM versions are restricted in
speed and lack some advance features like Code Coverage, Waveform
compare, assertions etc but the language support is the same as the full
version.

If I may give you some advice, ditch the project option in Modelsim as
it will start to work against you at some time....now. Just create a .do
or .tcl file and you will get much better control and you can see
exactly what is happening.

Good luck,

Hans
www.ht-lab.com

On Tuesday, May 25, 2021 at 12:07:37 AM UTC-7, HT-Lab wrote:
> On 25/05/2021 06:18, Tianxiang Weng wrote:
> ..
> >>
> >> Thank you.
> >>
> >> Weng
> >
> > Sorry,
> >
> > I found an error in my last post:
> >
> > I changed another feature at *mpf file:
> > Show source line containing error. Default is off.
> >> Show_source = 1
> >
> > After the change, It does show the source code.
> >
> > Weng
> >
> Hi Weng,
>
> VHDL2008 is definitely supported. The OEM versions are restricted in
> speed and lack some advance features like Code Coverage, Waveform
> compare, assertions etc but the language support is the same as the full
> version.
>
> If I may give you some advice, ditch the project option in Modelsim as
> it will start to work against you at some time....now. Just create a .do
> or .tcl file and you will get much better control and you can see
> exactly what is happening.
>
> Good luck,
>
> Hans
> www.ht-lab.com

Hans,
I copy the file generated by the command vcom -help all.

I search "do", 18 hits, there is no do file format; I searched "tcl", there is no-hit.

What should I do?

On 25/05/2021 10:47, Tianxiang Weng wrote:
> On Tuesday, May 25, 2021 at 12:07:37 AM UTC-7, HT-Lab wrote:
>> On 25/05/2021 06:18, Tianxiang Weng wrote:
>> ..
>>>>
..
>
> Hans,
> I copy the file generated by the command vcom -help all.
>
> I search "do", 18 hits, there is no do file format; I searched "tcl", there is no-hit.
>
> What should I do?
>

start reading:

<your_modelsim_installation_dir>/docs/pdfdocs/modelsim_tut.pdf

Regards,
Hans
www.ht-lab.com

On Tuesday, May 25, 2021 at 9:33:13 AM UTC-7, HT-Lab wrote:
> On 25/05/2021 10:47, Tianxiang Weng wrote:
> > On Tuesday, May 25, 2021 at 12:07:37 AM UTC-7, HT-Lab wrote:
> >> On 25/05/2021 06:18, Tianxiang Weng wrote:
> >> ..
> >>>>
> .
> >
> > Hans,
> > I copy the file generated by the command vcom -help all.
> >
> > I search "do", 18 hits, there is no do file format; I searched "tcl", there is no-hit.
> >
> > What should I do?
> >
> start reading:
>
> <your_modelsim_installation_dir>/docs/pdfdocs/modelsim_tut.pdf
>
> Regards,
> Hans
> www.ht-lab.com

Hans,

Thank you for your guide.

I have downloaded the files, the version is 2012, 10.c.
Is it the latest version available from the web?

Weng

On Tuesday, May 25, 2021 at 12:32:55 PM UTC-7, Tianxiang Weng wrote:
> On Tuesday, May 25, 2021 at 9:33:13 AM UTC-7, HT-Lab wrote:
> > On 25/05/2021 10:47, Tianxiang Weng wrote:
> > > On Tuesday, May 25, 2021 at 12:07:37 AM UTC-7, HT-Lab wrote:
> > >> On 25/05/2021 06:18, Tianxiang Weng wrote:
> > >> ..
> > >>>>
> > .
> > >
> > > Hans,
> > > I copy the file generated by the command vcom -help all.
> > >
> > > I search "do", 18 hits, there is no do file format; I searched "tcl", there is no-hit.
> > >
> > > What should I do?
> > >
> > start reading:
> >
> > <your_modelsim_installation_dir>/docs/pdfdocs/modelsim_tut.pdf
> >
> > Regards,
> > Hans
> > www.ht-lab.com
> Hans,
>
> Thank you for your guide.
>
> I have downloaded the files, the version is 2012, 10.c.
> Is it the latest version available from the web?
>
> Weng

Hi Hans,
After reading 6 pages of MIT ModelSim/Verilog Tutorial at file:///E:/Weng/00-Claim/00-Sorting/00-Simulation/ModelSim%20Files/ModelSim_tutorial.pdf, I decided to abandon any attempt to use the command-line method.

The reason is very simple: if the Starter Edition ignores the -2008 parameter in using the icon method, it will ignore it in a command-line method. There is no good luck with it.

Thank you.

Weng

On 25/05/2021 20:32, Tianxiang Weng wrote:
> On Tuesday, May 25, 2021 at 9:33:13 AM UTC-7, HT-Lab wrote:
...
>
> Thank you for your guide.
>
> I have downloaded the files, the version is 2012, 10.c.
> Is it the latest version available from the web?

No it should be 2020.3,

Regards,
Hans.

>
> Weng
>

On Tuesday, May 25, 2021 at 11:17:10 PM UTC-7, HT-Lab wrote:
> On 25/05/2021 20:32, Tianxiang Weng wrote:
> > On Tuesday, May 25, 2021 at 9:33:13 AM UTC-7, HT-Lab wrote:
> ..
> >
> > Thank you for your guide.
> >
> > I have downloaded the files, the version is 2012, 10.c.
> > Is it the latest version available from the web?
> No it should be 2020.3,
>
> Regards,
> Hans.
>
> >
> > Weng
> >

Hans,

Could you give a link to 2020.3?

Weng

On 26/05/2021 06:21, Tianxiang Weng wrote:
> On Tuesday, May 25, 2021 at 12:32:55 PM UTC-7, Tianxiang Weng wrote:
...
>
> Hi Hans,
> After reading 6 pages of MIT ModelSim/Verilog Tutorial at file:///E:/Weng/00-Claim/00-Sorting/00-Simulation/ModelSim%20Files

Verilog?

/ModelSim_tutorial.pdf, I decided to abandon any attempt to use the
command-line method.
>
> The reason is very simple: if the Starter Edition ignores the -2008 parameter in using the icon method, it will ignore it in a command-line method. There is no good luck with it.

Not sure what you are doing but creating a Modelsim .do/.tcl file is
dead simple, here is the procedure for a simple design:

1) Create a work library (this is done automatically as well)
vlib work work

2) Optionally but recommended create a local modelsim.ini file
vmap work work

3) compile your design
vcom -quiet -2008 myfiles.vhd
vlog -quiet myver.sv

4) elaborate the design
vsim -quiet work.mytestbench

5) open waveform (or open previous saved one with do wave.do)
view wave

6) drag and drop your signals in the waveform window and save

7) run your simulation
run -all

To re-iterate all OEM versions support VHDL2008,

Regards,
Hans
www.ht-lab.com

>
> Thank you.
>
> Weng
>

On Tuesday, May 25, 2021 at 11:36:20 PM UTC-7, HT-Lab wrote:
> On 26/05/2021 06:21, Tianxiang Weng wrote:
> > On Tuesday, May 25, 2021 at 12:32:55 PM UTC-7, Tianxiang Weng wrote:
> ..
> >
> > Hi Hans,
> > After reading 6 pages of MIT ModelSim/Verilog Tutorial at file:///E:/Weng/00-Claim/00-Sorting/00-Simulation/ModelSim%20Files
> Verilog?
> /ModelSim_tutorial.pdf, I decided to abandon any attempt to use the
> command-line method.
> >
> > The reason is very simple: if the Starter Edition ignores the -2008 parameter in using the icon method, it will ignore it in a command-line method.. There is no good luck with it.
> Not sure what you are doing but creating a Modelsim .do/.tcl file is
> dead simple, here is the procedure for a simple design:
>
> 1) Create a work library (this is done automatically as well)
> vlib work work
>
> 2) Optionally but recommended create a local modelsim.ini file
> vmap work work
>
> 3) compile your design
> vcom -quiet -2008 myfiles.vhd
> vlog -quiet myver.sv
>
> 4) elaborate the design
> vsim -quiet work.mytestbench
>
> 5) open waveform (or open previous saved one with do wave.do)
> view wave
>
> 6) drag and drop your signals in the waveform window and save
>
> 7) run your simulation
> run -all
>
> To re-iterate all OEM versions support VHDL2008,
>
> Regards,
> Hans
> www.ht-lab.com
>
>
> >
> > Thank you.
> >
> > Weng
> >

Hi Hans,

Thank you very much, I appreciate your selfless efforts to help me.

I will try your method step by step and will report to you on this post for further advice after step 3.

I have a FIFO entity., 108 source code lines, to test if the Starter Edition allows using the VHDL-2008: eliminating a signal Full that drives the output port Full_O. My experience is the Starter Edition gives a hint that an output port cannot be read internally and the function can be implemented if it is compiled with the 2008 version set. Why I told you that the Starter Edition does not support the 2008 version, is because of the generated hint, i.t. after your step 3, I will immediately know if the Starter Edition supports the 2008 version.

Actually, I may need a few more months to finish my project. I am about halfway now to the finish line regarding the coding. With Starter Edition of ModelSim available now, I tried to compile my finished files to see if there are any types of errors and do simulation for the finished algorithm.

My original plan is when all my coding is finished, I will purchase Intel ModelSim for the first year of $1999, then start compiling and simulating with the VHDL-2008 version and finish it within 1 year.

If you are more interested in what I am doing now, we may communicate personally through my email: w t x w t x @ g m a I . c o m.

Weng

On Wednesday, May 26, 2021 at 4:35:32 AM UTC-7, Tianxiang Weng wrote:
> On Tuesday, May 25, 2021 at 11:36:20 PM UTC-7, HT-Lab wrote:
> > On 26/05/2021 06:21, Tianxiang Weng wrote:
> > > On Tuesday, May 25, 2021 at 12:32:55 PM UTC-7, Tianxiang Weng wrote:
> > ..
> > >
> > > Hi Hans,
> > > After reading 6 pages of MIT ModelSim/Verilog Tutorial at file:///E:/Weng/00-Claim/00-Sorting/00-Simulation/ModelSim%20Files
> > Verilog?
> > /ModelSim_tutorial.pdf, I decided to abandon any attempt to use the
> > command-line method.
> > >
> > > The reason is very simple: if the Starter Edition ignores the -2008 parameter in using the icon method, it will ignore it in a command-line method. There is no good luck with it.
> > Not sure what you are doing but creating a Modelsim .do/.tcl file is
> > dead simple, here is the procedure for a simple design:
> >
> > 1) Create a work library (this is done automatically as well)
> > vlib work work
> >
> > 2) Optionally but recommended create a local modelsim.ini file
> > vmap work work
> >
> > 3) compile your design
> > vcom -quiet -2008 myfiles.vhd
> > vlog -quiet myver.sv
> >
> > 4) elaborate the design
> > vsim -quiet work.mytestbench
> >
> > 5) open waveform (or open previous saved one with do wave.do)
> > view wave
> >
> > 6) drag and drop your signals in the waveform window and save
> >
> > 7) run your simulation
> > run -all
> >
> > To re-iterate all OEM versions support VHDL2008,
> >
> > Regards,
> > Hans
> > www.ht-lab.com
> >
> >
> > >
> > > Thank you.
> > >
> > > Weng
> > >
> Hi Hans,
>
> Thank you very much, I appreciate your selfless efforts to help me.
>
> I will try your method step by step and will report to you on this post for further advice after step 3.
>
> I have a FIFO entity., 108 source code lines, to test if the Starter Edition allows using the VHDL-2008: eliminating a signal Full that drives the output port Full_O. My experience is the Starter Edition gives a hint that an output port cannot be read internally and the function can be implemented if it is compiled with the 2008 version set. Why I told you that the Starter Edition does not support the 2008 version, is because of the generated hint, i.t. after your step 3, I will immediately know if the Starter Edition supports the 2008 version.
>
> Actually, I may need a few more months to finish my project. I am about halfway now to the finish line regarding the coding. With Starter Edition of ModelSim available now, I tried to compile my finished files to see if there are any types of errors and do simulation for the finished algorithm.
>
> My original plan is when all my coding is finished, I will purchase Intel ModelSim for the first year of $1999, then start compiling and simulating with the VHDL-2008 version and finish it within 1 year.
>
> If you are more interested in what I am doing now, we may communicate personally through my email: w t x w t x @ g m a I . c o m.
>
> Weng

Hans,
Here is the record of my compiling FIFO.vhd:

can't open "transcript": permission denied
# Reading pref.tcl
# Loading project FIFO
vcom -work work -2008 -explicit -stats=none FIFO.vhd
# Model Technology ModelSim - Intel FPGA Edition vcom 2021.1 Compiler 2021.02 Feb 3 2021
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity FIFO
# -- Compiling architecture A of FIFO
# ** Error: FIFO.vhd(87): Ambiguous type in infix expression; ieee.NUMERIC_STD.UNRESOLVED_UNSIGNED or ieee.NUMERIC_STD.UNRESOLVED_SIGNED.
# ** Note: FIFO.vhd(120): VHDL Compiler exiting
# C:/intelFPGA_pro/21.1/modelsim_ase/win32aloem/vcom failed.

The error is about a case statement:
case A & B is -- test this statement
....
end case;

In 2008, A & B can be two different signals; In 2002,
case C is -- C = A & B
....
end case;

In the Starter Edition, when ModelSim is being opened, one can only choose the "Jump Start" button to either create a project or open an existing project. No other choice to select.

I selected the "Create a project" button. After the input is finished I enter the following command line:
vcom -work work -2008 -explicit -stats=none FIFO.vhd

Is there anything I missed?

Weng

On 26/05/2021 17:41, Tianxiang Weng wrote:
...snip

Hi Weng,

>
> Hans,
> Here is the record of my compiling FIFO.vhd:
>
> can't open "transcript": permission denied

That is not good, do you have admin rights on your PC?

> # Reading pref.tcl
> # Loading project FIFO
> vcom -work work -2008 -explicit -stats=none FIFO.vhd
> # Model Technology ModelSim - Intel FPGA Edition vcom 2021.1 Compiler 2021.02 Feb 3 2021
> # -- Loading package STANDARD
> # -- Loading package TEXTIO
> # -- Loading package std_logic_1164
> # -- Loading package NUMERIC_STD
> # -- Compiling entity FIFO
> # -- Compiling architecture A of FIFO
> # ** Error: FIFO.vhd(87): Ambiguous type in infix expression; ieee.NUMERIC_STD.UNRESOLVED_UNSIGNED or ieee.NUMERIC_STD.UNRESOLVED_SIGNED.
> # ** Note: FIFO.vhd(120): VHDL Compiler exiting
> # C:/intelFPGA_pro/21.1/modelsim_ase/win32aloem/vcom failed.
>
> The error is about a case statement:
> case A & B is -- test this statement
> ...
> end case;
>
> In 2008, A & B can be two different signals; In 2002,
> case C is -- C = A & B
> ...
> end case;

Hard to tell what is going on, I would suggest you post your code on the
comp.lang.vhdl

> In the Starter Edition, when ModelSim is being opened, one can only choose the "Jump Start" button to either create a project or open an existing project. No other choice to select.

I suspect it find an mpf file (your previous project perhaps) and hence
defaults to using projects? Just delete/rename the mpf file and try
again. If that fails then you can try to rename or delete the Modelsim
registry entry:

HKEY_CURRENT_USER\Software\Model Technology Incorporated\ModelSim

When you rename/delete this entry Modelsim will recreate it when it
starts up and behaves as if it has just been installed.

>
> I selected the "Create a project" button. After the input is finished I enter the following command line:
> vcom -work work -2008 -explicit -stats=none FIFO.vhd
>
> Is there anything I missed?

Most likely but as I mentioned difficult to tell what is going on,

Good luck,
Hans.
www.ht-lab.com

>
> Weng
>

On Thursday, May 27, 2021 at 8:51:03 AM UTC-7, HT-Lab wrote:
> On 26/05/2021 17:41, Tianxiang Weng wrote:
> ..snip
>
> Hi Weng,
> >
> > Hans,
> > Here is the record of my compiling FIFO.vhd:
> >
> > can't open "transcript": permission denied
> That is not good, do you have admin rights on your PC?
> > # Reading pref.tcl
> > # Loading project FIFO
> > vcom -work work -2008 -explicit -stats=none FIFO.vhd
> > # Model Technology ModelSim - Intel FPGA Edition vcom 2021.1 Compiler 2021.02 Feb 3 2021
> > # -- Loading package STANDARD
> > # -- Loading package TEXTIO
> > # -- Loading package std_logic_1164
> > # -- Loading package NUMERIC_STD
> > # -- Compiling entity FIFO
> > # -- Compiling architecture A of FIFO
> > # ** Error: FIFO.vhd(87): Ambiguous type in infix expression; ieee.NUMERIC_STD.UNRESOLVED_UNSIGNED or ieee.NUMERIC_STD.UNRESOLVED_SIGNED.
> > # ** Note: FIFO.vhd(120): VHDL Compiler exiting
> > # C:/intelFPGA_pro/21.1/modelsim_ase/win32aloem/vcom failed.
> >
> > The error is about a case statement:
> > case A & B is -- test this statement
> > ...
> > end case;
> >
> > In 2008, A & B can be two different signals; In 2002,
> > case C is -- C = A & B
> > ...
> > end case;
> Hard to tell what is going on, I would suggest you post your code on the
> comp.lang.vhdl
> > In the Starter Edition, when ModelSim is being opened, one can only choose the "Jump Start" button to either create a project or open an existing project. No other choice to select.
> I suspect it find an mpf file (your previous project perhaps) and hence
> defaults to using projects? Just delete/rename the mpf file and try
> again. If that fails then you can try to rename or delete the Modelsim
> registry entry:
>
> HKEY_CURRENT_USER\Software\Model Technology Incorporated\ModelSim
>
> When you rename/delete this entry Modelsim will recreate it when it
> starts up and behaves as if it has just been installed.
> >
> > I selected the "Create a project" button. After the input is finished I enter the following command line:
> > vcom -work work -2008 -explicit -stats=none FIFO.vhd
> >
> > Is there anything I missed?
> Most likely but as I mentioned difficult to tell what is going on,
>
> Good luck,
> Hans.
> www.ht-lab.com
>
>
> >
> > Weng
> >

Hans,

I created a new directory, an empty one, then copied a modified FIFO.vhd into the directory; after that, I started ModelSim and created a new project and got the result.

No, I don't want to continue any other things to try it again.

Thank you.

Weng