On Tuesday, May 11, 2021 at 11:16:24 PM UTC+3, Ivan Godard wrote:
> On 5/11/2021 10:27 AM, Marcus wrote:
> > On 2021-05-10, MitchAlsup wrote:
> >> On Monday, May 10, 2021 at 3:53:45 PM UTC-5, robf...@gmail.com wrote:
> >>> ANY1 supports a 21 bit branch displacement for branching +/-1MB. It
> >>> may also store the return address in the target register allowing
> >>> conditional branch to subroutine.
> >> <
> >> How often do you find conditional branching to a subroutine to be
> >> effective ?
> >
> > I had conditional branch-and-link in my ISA at one point (probably
> > inspired by POWER or some such ISA), but then I realized that it
> > actually implied a conditional move to the link register, which
> > was something I wanted to avoid (plus the instructions ate up valuable
> > instruction encoding space) - so I removed those instructions.
> Doesn't have to require conditional move.
>
> In a belt machine, a call must update the belt in the same way whether
> taken or not, so Mill conditional calls drop null results if the call is
> untaken. Because of the availability of NaR as a metadata marker for
> invalid/missing data, the nulls are NaRs and so will poison any
> subsequent actual use of the value, but that's a QOI feature independent
> of the conditional call feature.
>
> In your case, you could have the link register unconditionally
> klobbered, either by the return address if taken, or a null if untaken.
> Or, if the return address can be meaningfully used whether taken or not,
> set the register unconditionally to what would be the return address if
> it had been taken. An untaken conditional call need not be totally free
> of side effects; it just must not enter the called address.

How is it different from any other premature use of destination register of avdanced load ?
To me it looks like a compiler bug rather than architecture bug.

On Saturday, May 15, 2021 at 11:11:36 PM UTC+3, Michael S wrote:
> On Tuesday, May 11, 2021 at 11:16:24 PM UTC+3, Ivan Godard wrote:
> > On 5/11/2021 10:27 AM, Marcus wrote:
> > > On 2021-05-10, MitchAlsup wrote:
> > >> On Monday, May 10, 2021 at 3:53:45 PM UTC-5, robf...@gmail.com wrote:
> > >>> ANY1 supports a 21 bit branch displacement for branching +/-1MB. It
> > >>> may also store the return address in the target register allowing
> > >>> conditional branch to subroutine.
> > >> <
> > >> How often do you find conditional branching to a subroutine to be
> > >> effective ?
> > >
> > > I had conditional branch-and-link in my ISA at one point (probably
> > > inspired by POWER or some such ISA), but then I realized that it
> > > actually implied a conditional move to the link register, which
> > > was something I wanted to avoid (plus the instructions ate up valuable
> > > instruction encoding space) - so I removed those instructions.
> > Doesn't have to require conditional move.
> >
> > In a belt machine, a call must update the belt in the same way whether
> > taken or not, so Mill conditional calls drop null results if the call is
> > untaken. Because of the availability of NaR as a metadata marker for
> > invalid/missing data, the nulls are NaRs and so will poison any
> > subsequent actual use of the value, but that's a QOI feature independent
> > of the conditional call feature.
> >
> > In your case, you could have the link register unconditionally
> > klobbered, either by the return address if taken, or a null if untaken.
> > Or, if the return address can be meaningfully used whether taken or not,
> > set the register unconditionally to what would be the return address if
> > it had been taken. An untaken conditional call need not be totally free
> > of side effects; it just must not enter the called address.
> How is it different from any other premature use of destination register of avdanced load ?
> To me it looks like a compiler bug rather than architecture bug.

A post went to wrong thread, sorry.
I am not sure if it was my own mistake or bug in google groups engine.