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devel / comp.arch / Re: PDP-11-like ISA

SubjectAuthor
* PDP-11-like ISAMitchAlsup
+* Re: PDP-11-like ISAJimBrakefield
|`- Re: PDP-11-like ISAMitchAlsup
+* Re: PDP-11-like ISAQuadibloc
|+* Re: PDP-11-like ISAQuadibloc
||`- Re: PDP-11-like ISAMitchAlsup
|+- Re: PDP-11-like ISAMitchAlsup
|+- Re: PDP-11-like ISAMitchAlsup
|`* Re: PDP-11-like ISAchris
| `* Re: PDP-11-like ISAQuadibloc
|  +* Re: PDP-11-like ISAMitchAlsup
|  |+* Re: PDP-11-like ISAIvan Godard
|  ||+* Re: PDP-11-like ISAMitchAlsup
|  |||`- Re: PDP-11-like ISAIvan Godard
|  ||`* Re: PDP-11-like ISATerje Mathisen
|  || `* Re: PDP-11-like ISAIvan Godard
|  ||  +* Re: PDP-11-like ISAMitchAlsup
|  ||  |+- Re: PDP-11-like ISATerje Mathisen
|  ||  |`* Re: PDP-11-like ISAEricP
|  ||  | +* Re: PDP-11-like ISAMitchAlsup
|  ||  | |`- Re: PDP-11-like ISAEricP
|  ||  | `- Re: PDP-11-like ISATerje Mathisen
|  ||  `* Re: PDP-11-like ISAStephen Fuld
|  ||   `* Re: PDP-11-like ISAIvan Godard
|  ||    `* Re: PDP-11-like ISAStephen Fuld
|  ||     +- Re: PDP-11-like ISAIvan Godard
|  ||     `- Re: PDP-11-like ISAIvan Godard
|  |`* Re: PDP-11-like ISAQuadibloc
|  | +* Re: PDP-11-like ISAQuadibloc
|  | |+* Re: PDP-11-like ISAIvan Godard
|  | ||`* Re: PDP-11-like ISAQuadibloc
|  | || `* Re: PDP-11-like ISAJames Harris
|  | ||  +* Condition codes (was: PDP-11-like ISA)Anton Ertl
|  | ||  |`* Re: Condition codes (was: PDP-11-like ISA)Quadibloc
|  | ||  | `- Re: Condition codes (was: PDP-11-like ISA)Anton Ertl
|  | ||  `* Re: PDP-11-like ISAMitchAlsup
|  | ||   `* Re: PDP-11-like ISAJames Harris
|  | ||    `- Re: PDP-11-like ISAMitchAlsup
|  | |`- Re: PDP-11-like ISAQuadibloc
|  | +* Re: PDP-11-like ISAMitchAlsup
|  | |`* Re: PDP-11-like ISAEricP
|  | | `- Re: PDP-11-like ISAMitchAlsup
|  | `- Condition codes (was: PDP-11-like ISA)Anton Ertl
|  `* Re: PDP-11-like ISAAnton Ertl
|   `* Re: PDP-11-like ISAQuadibloc
|    `* Re: PDP-11-like ISAAnton Ertl
|     +* Re: PDP-11-like ISAQuadibloc
|     |`- Re: PDP-11-like ISAQuadibloc
|     `* Re: PDP-11-like ISAMitchAlsup
|      `- Re: PDP-11-like ISAQuadibloc
`* Re: PDP-11-like ISAEricP
 +* Re: PDP-11-like ISAJimBrakefield
 |`* Re: PDP-11-like ISAMitchAlsup
 | `- Re: PDP-11-like ISAJimBrakefield
 +* Re: PDP-11-like ISAMitchAlsup
 |+* Re: PDP-11-like ISAQuadibloc
 ||+- Re: PDP-11-like ISAMitchAlsup
 ||`- Re: PDP-11-like ISAMitchAlsup
 |`* Re: PDP-11-like ISAEricP
 | +* Re: PDP-11-like ISAMitchAlsup
 | |`* Re: PDP-11-like ISAEricP
 | | `* Re: PDP-11-like ISAMitchAlsup
 | |  +- Re: PDP-11-like ISAJimBrakefield
 | |  +- Re: PDP-11-like ISAThomas Koenig
 | |  `* Re: PDP-11-like ISATerje Mathisen
 | |   +- Re: PDP-11-like ISAQuadibloc
 | |   +- Re: PDP-11-like ISAMitchAlsup
 | |   `* Re: PDP-11-like ISAStefan Monnier
 | |    `- Re: PDP-11-like ISATerje Mathisen
 | `* Re: PDP-11-like ISATerje Mathisen
 |  +* Re: PDP-11-like ISAEricP
 |  |`* Re: PDP-11-like ISATerje Mathisen
 |  | `* Re: PDP-11-like ISAMitchAlsup
 |  |  `* Re: PDP-11-like ISATerje Mathisen
 |  |   `* Re: PDP-11-like ISAEricP
 |  |    `* Re: PDP-11-like ISAMitchAlsup
 |  |     `- Re: PDP-11-like ISAEricP
 |  `* Re: PDP-11-like ISAMitchAlsup
 |   +* Re: PDP-11-like ISAMitchAlsup
 |   |`* Re: PDP-11-like ISAQuadibloc
 |   | `- Re: PDP-11-like ISAMitchAlsup
 |   `* Re: PDP-11-like ISATerje Mathisen
 |    `* Re: PDP-11-like ISAMitchAlsup
 |     +* Re: PDP-11-like ISAQuadibloc
 |     |`* Re: PDP-11-like ISAMitchAlsup
 |     | +* Re: PDP-11-like ISAJimBrakefield
 |     | |`- Re: PDP-11-like ISAMitchAlsup
 |     | `- Re: PDP-11-like ISATerje Mathisen
 |     `* Re: PDP-11-like ISAJames Harris
 |      `* Re: PDP-11-like ISAThomas Koenig
 |       +* Re: PDP-11-like ISAAnton Ertl
 |       |`- Re: PDP-11-like ISAThomas Koenig
 |       +* Re: PDP-11-like ISATerje Mathisen
 |       |`- Re: PDP-11-like ISAIvan Godard
 |       `- Re: PDP-11-like ISAEricP
 `* Re: PDP-11-like ISAQuadibloc
  +- Re: PDP-11-like ISAMitchAlsup
  `* Re: PDP-11-like ISAEricP
   +- Re: PDP-11-like ISABGB
   +* Re: PDP-11-like ISAMitchAlsup
   |`* Re: PDP-11-like ISATerje Mathisen
   `* Re: PDP-11-like ISAQuadibloc

Pages:12345
Re: PDP-11-like ISA

<sa8jqh$rlm$1@dont-email.me>

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https://www.novabbs.com/devel/article-flat.php?id=17772&group=comp.arch#17772

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From: iva...@millcomputing.com (Ivan Godard)
Newsgroups: comp.arch
Subject: Re: PDP-11-like ISA
Date: Mon, 14 Jun 2021 15:05:04 -0700
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 by: Ivan Godard - Mon, 14 Jun 2021 22:05 UTC

On 6/14/2021 2:25 PM, Stephen Fuld wrote:
> On 6/13/2021 11:45 PM, Ivan Godard wrote:
>> On 6/13/2021 6:29 PM, Stephen Fuld wrote:
>>> On 6/13/2021 1:33 PM, Ivan Godard wrote:
>>>> On 6/13/2021 1:03 PM, Terje Mathisen wrote:
>>
>>>> And that's the question. True, there could be bits for </=/> and you
>>>> do a compound for <= and >=, but that seems pointless to me; you
>>>> should have a negate flag (branch direction) in the instruction
>>>> instead of compounding. Otherwise, how often are compound checks of
>>>> real operands in real code? Yes, FP folding a NaN check is a
>>>> reasonable use - but how often is NaN checked for in real code
>>>> regardless of how you do it?
>>>>
>>>> So if compounds are ignorably rare then the bit vector is just an
>>>> encoding idea and should be measured on code density.
>>>
>>> One other point.  Mitch's scheme does all those checks with a single
>>> op code for the compare and one (or two if you include the
>>> predication) for for the conditional branch/predicate.  So depending
>>> upon how the alternative handles things, you might require fewer op
>>> codes.  How much that is worth is, of course, dependent on lots of
>>> other factors.
>>>
>>>
>>
>> Yes; it shifts entropy from opcode to bit selector. But it doesn't
>> reduce the total entropy.
>
> Of course, you are right, but if (unlike the Mill) you have fixed length
> instructions, especially with fixed length fields within them, you might
> have more, otherwise unused, bits available in other places.  e.g. in a
> 32 bit fixed instruction, for a conditional branch, typically one of
> the, otherwise unused, register specifier fields is available to hold
> those bits.
>
> As I said before, YMMV.

We're in violent agreement: it's an encoding device, of use where it's
useful.

BTW, Mill has fixed length instructions. But they are not necessarily
2^N sized, and you can have variable numbers of them bundled into 2^N
boundaries. As a result, instructions are entropy-optimal and
parse-optimal, and bundles are memory-access optimal.

Re: PDP-11-like ISA

<sa8jsv$s4a$1@dont-email.me>

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https://www.novabbs.com/devel/article-flat.php?id=17773&group=comp.arch#17773

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From: iva...@millcomputing.com (Ivan Godard)
Newsgroups: comp.arch
Subject: Re: PDP-11-like ISA
Date: Mon, 14 Jun 2021 15:06:22 -0700
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 by: Ivan Godard - Mon, 14 Jun 2021 22:06 UTC

On 6/14/2021 2:25 PM, Stephen Fuld wrote:
> On 6/13/2021 11:45 PM, Ivan Godard wrote:
>> On 6/13/2021 6:29 PM, Stephen Fuld wrote:
>>> On 6/13/2021 1:33 PM, Ivan Godard wrote:
>>>> On 6/13/2021 1:03 PM, Terje Mathisen wrote:
>>
>>>> And that's the question. True, there could be bits for </=/> and you
>>>> do a compound for <= and >=, but that seems pointless to me; you
>>>> should have a negate flag (branch direction) in the instruction
>>>> instead of compounding. Otherwise, how often are compound checks of
>>>> real operands in real code? Yes, FP folding a NaN check is a
>>>> reasonable use - but how often is NaN checked for in real code
>>>> regardless of how you do it?
>>>>
>>>> So if compounds are ignorably rare then the bit vector is just an
>>>> encoding idea and should be measured on code density.
>>>
>>> One other point.  Mitch's scheme does all those checks with a single
>>> op code for the compare and one (or two if you include the
>>> predication) for for the conditional branch/predicate.  So depending
>>> upon how the alternative handles things, you might require fewer op
>>> codes.  How much that is worth is, of course, dependent on lots of
>>> other factors.
>>>
>>>
>>
>> Yes; it shifts entropy from opcode to bit selector. But it doesn't
>> reduce the total entropy.
>
> Of course, you are right, but if (unlike the Mill) you have fixed length
> instructions, especially with fixed length fields within them, you might
> have more, otherwise unused, bits available in other places.  e.g. in a
> 32 bit fixed instruction, for a conditional branch, typically one of
> the, otherwise unused, register specifier fields is available to hold
> those bits.
>
> As I said before, YMMV.

We're in violent agreement: it's an encoding device, of use where it's
useful.

BTW, Mill has fixed length instructions. But they are not necessarily
2^N sized, and you can have variable numbers of them bundled into 2^N
boundaries. As a result, instructions are entropy-optimal and
parse-optimal, and bundles are memory-access optimal.

Re: PDP-11-like ISA

<safcr7$d1t$1@gioia.aioe.org>

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https://www.novabbs.com/devel/article-flat.php?id=17844&group=comp.arch#17844

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From: terje.ma...@tmsw.no (Terje Mathisen)
Newsgroups: comp.arch
Subject: Re: PDP-11-like ISA
Date: Thu, 17 Jun 2021 13:48:56 +0200
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 by: Terje Mathisen - Thu, 17 Jun 2021 11:48 UTC

EricP wrote:
> MitchAlsup wrote:
>> On Sunday, June 13, 2021 at 3:33:45 PM UTC-5, Ivan Godard wrote:
>>> On 6/13/2021 1:03 PM, Terje Mathisen wrote:
>>>> Ivan Godard wrote:
>>
>>>> I.e. any kind of compound check.
>>>> Terje
>> <
>>> And that's the question. True, there could be bits for </=/> and you
>>> do a compound for <= and >=, but that seems pointless to me; you
>>> should have a negate flag (branch direction) in the instruction
>>> instead of compounding. Otherwise, how often are compound checks of
>>> real operands in real code? Yes, FP folding a NaN check is a
>>> reasonable use - but how often is NaN checked for in real code
>>> regardless of how you do it?
>> <
>> Well Written FP codes do it all the time::
>> <
>> double ATAN2( double y, double x )
>> {   // IEEE 754-2019 quality ATAN2
>>     // deal with NANs
>>     if( ISNAN( x )             ) return x;
>>     if( ISNAN( y )             ) return y;
>>    // deal with infinities
>>    if( x == +∞  && |y|== +∞ ) return copysign(  π/4, y );
>>    if( x == +∞              ) return copysign(  0.0, y );
>>    if( x == -∞  && |y|== +∞ ) return copysign( 3π/4, y );
>>    if( x == -∞              ) return copysign(    π, y );
>>    if(             |y|== +∞ ) return copysign(  π/2, y );
>>     // deal with signed zeros
>>     if( x == 0.0  &&  y != 0.0 ) return copysign(  π/2, y );
>>     if( x >=+0.0  &&  y == 0.0 ) return copysign(  0.0, y );
>>     if( x <=-0.0  &&  y == 0.0 ) return copysign(    π, y );
>>     // calculate ATAN2 high performance style
>>    if( x  > 0.0             )
>>    {
>>         if( y < 0.0 && |y| < |x| ) return - π/2 - ATAN( x / y );
>>         if( y < 0.0 && |y| > |x| ) return       + ATAN( y / x );
>>         if( y > 0.0 && |y| < |x| ) return       + ATAN( y / x );
>>         if( y > 0.0 && |y| > |x| ) return + π/2 - ATAN( x / y );
>>    }
>>    if( x  < 0.0             )
>>    {         if( y < 0.0 && |y| > |x| ) return + π/2 + ATAN( x / y );
>>         if( y < 0.0 && |y| > |x| ) return + π   - ATAN( y / x );
>>         if( y > 0.0 && |y| < |x| ) return + π   - ATAN( y / x );
>>         if( y > 0.0 && |y| > |x| ) return +3π/2 + ATAN( x / y );
>>     }
>> <
>> Not so well written FP codes are (well) no so well written.
>> <
>> Also note: only 1 compare is required to perform all of the above checks
>> in My 66000 ISA.
>>> So if compounds are ignorably rare then the bit vector is just an
>>> encoding idea and should be measured on code density.
>
> How many bits is the cmp bit vector?
> I would imagine the above IF construct shows up in a lot of FP code.
> Can you use your cmp bit vector as an index to a switch instruction,
> or would it bloat too much?

For scalar code you want a single branch to separate out all the rare
cases, letting the straight line path be significantly faster.

For HW or SIMD you instead want all options to run at the same time, and
use the classification bits to select the proper result among the
alternatives.
>
> Or maybe a two switches, filter out all NAN's and INF's first,
> then deal with all the number variations.
>
Yeah, that's more like it.

Terje

--
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"

Re: PDP-11-like ISA

<safdeo$pt7$1@gioia.aioe.org>

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https://www.novabbs.com/devel/article-flat.php?id=17845&group=comp.arch#17845

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From: terje.ma...@tmsw.no (Terje Mathisen)
Newsgroups: comp.arch
Subject: Re: PDP-11-like ISA
Date: Thu, 17 Jun 2021 13:59:20 +0200
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 by: Terje Mathisen - Thu, 17 Jun 2021 11:59 UTC

Stefan Monnier wrote:
> Terje Mathisen [2021-06-14 07:55:39] wrote:
>> MitchAlsup wrote:
>>> On Saturday, June 12, 2021 at 2:23:09 PM UTC-5, EricP wrote:
>>>> That removes the IP from the register set and moves all the above mode
>>>> specifier bits into the opcode, where they can be optimally assigned.
>>> <
>>> I am currently playing with the notion where there is a small register file
>>> (8 entries) which is really fast, and a larger register file (64-256 entries)
>>> which is 1 cycle access, and then memory which is 3-4 cycles of access
>>> and supports sizes other than 64-bits. {The first 8 entries of the large
>>> file is the small 8 register file.}
>> So, this is a NURA (Non-Uniform Register Access) machine?
>> I am sure the compiler writes would love it. :-)
>> (Personally I would be perfectly happy, 8 effective registers are enough for
>> almost all the inner loop code I have ever written.)
>
> I believe you're familiar with a machine called "Mill" which has fast
> registers (called "belt positions") and slow registers (placed in
> a thingy called "scratchpad") ;-)

Hmmm... I might have stumbled over something called a Tiny Mill with
just 8 belt positions at some point in time. :-)

It is in fact quite narrow if you also want to use branchless
programming and pick() to join the multiple paths back together.

Terje

--
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"

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rocksolid light 0.9.7
clearnet tor