Le 15/06/2021 à 19:15, Stephen Fuld a écrit :
> On 6/15/2021 9:30 AM, Guillaume wrote:
>> Le 12/06/2021 à 22:28, Thomas Koenig a écrit :
>>> Advantages: There would be no need to write back the value
>>> to the physical register file, saving effort (and possibly
>>> making analysis easer).
>>
>> I don't really get it. In what kind of microarchitecture would a
>> register be written back if it had not been modified anyway?
>>
>>> Saving registers on function entry could be restricted on those
>>> which are actually valid, the same would hold for a context switch.
>>
>> Yeah, why not. Except...
>>
>> You need to figure out what a valid register means exactly. It's not
>> hard to figure that all registers would be flagged invalid upon
>> 'reset'. But once a given register has been written to, what exactly
>> would make it "invalid" again?
>
> How about you have started the execution of a load instruction, but the
> memory system hasn't yet returned the value?  You don't want to use the
> "old"/existing value, but the new value isn't available yet.

That's what is called a load-use hazard. There are tons of ways to deal
with this, usually left to various parts of the microarch depending on
its implementation. Usually left to the pipeline control unit for
pipelined processors.

Same for any operation that could span several cycles, by the way.

I don't think that's the kind of use cases the OP mentioned or had in
mind, but using a "valid" bit for handling those cases instead of other
means might yield some benefits, depending on what the microarch is.
Maybe especially for out-of-order execution. I'll have to give it some
thought.

On Tuesday, June 15, 2021 at 1:38:39 PM UTC-5, Guillaume wrote:
> Le 15/06/2021 à 18:39, MitchAlsup a écrit :
> > On Tuesday, June 15, 2021 at 11:30:38 AM UTC-5, Guillaume wrote:
> >> Le 12/06/2021 à 22:28, Thomas Koenig a écrit :
> >>> Advantages: There would be no need to write back the value
> >>> to the physical register file, saving effort (and possibly
> >>> making analysis easer).
> >> I don't really get it. In what kind of microarchitecture would a
> >> register be written back if it had not been modified anyway?
> > <
> > x86 where one has a shift and a shift count of 0. In this case the write back
> > is there to signal that the shift is complete and anyone dependent upon it
> > can now proceed.
> That's really an oddball here. How worth it can it be to go through such
> extents just to marginally improve I'm not even sure what in the end?
<
Back in the pre-486 days, microcode took a look at the shift count, and if
it were zero, just went on to the next instruction without modifying the
flags nor the result register.
<
This causes a "great disconnect" when building OoO machines because
until you see the shift count, you don't know which renamed register the
subsequent user of the destination instruction needs--nor do you know the
flag register values !!! or where they are supposed to come from !!!
<
When you get your chance--do not follow the x86 example.

Le 15/06/2021 à 20:45, MitchAlsup a écrit :
> On Tuesday, June 15, 2021 at 1:38:39 PM UTC-5, Guillaume wrote:
> Back in the pre-486 days, microcode took a look at the shift count, and if
> it were zero, just went on to the next instruction without modifying the
> flags nor the result register.
> <
> This causes a "great disconnect" when building OoO machines because
> until you see the shift count, you don't know which renamed register the
> subsequent user of the destination instruction needs--nor do you know the
> flag register values !!! or where they are supposed to come from !!!
> <
> When you get your chance--do not follow the x86 example.

Ah, thanks for the details. Always interesting to have those pieces of
history. And yes, you just confirmed this as an oddball, and even worse
than this.

MitchAlsup <MitchAlsup@aol.com> schrieb:
> On Tuesday, June 15, 2021 at 12:36:24 PM UTC-5, Thomas Koenig wrote:
>> MitchAlsup <Mitch...@aol.com> schrieb:
>> > On Tuesday, June 15, 2021 at 11:52:53 AM UTC-5, Thomas Koenig wrote:
>> >> Thomas Koenig <tko...@netcologne.de> schrieb:
>> >> > Thanks, but I am a technical writer
>> >> That should have read "I am not a technical writer".
>> ><
>> > Would it be rude of me to point out that that is bit more than a minor typo ?
>> No, please go ahead.
><
> At this point is no longer seem necessary.

If you'd said anything, I would in all probability have agreed.

Guillaume wrote:
> Le 15/06/2021 à 18:39, MitchAlsup a écrit :
>> On Tuesday, June 15, 2021 at 11:30:38 AM UTC-5, Guillaume wrote:
>>> Le 12/06/2021 à 22:28, Thomas Koenig a écrit :
>>>> Advantages: There would be no need to write back the value
>>>> to the physical register file, saving effort (and possibly
>>>> making analysis easer).
>>> I don't really get it. In what kind of microarchitecture would a
>>> register be written back if it had not been modified anyway?
>> <
>> x86 where one has a shift and a shift count of 0. In this case the
>> write back
>> is there to signal that the shift is complete and anyone dependent
>> upon it
>> can now proceed.
>
> That's really an oddball here. How worth it can it be to go through such
> extents just to marginally improve I'm not even sure what in the end?

It is a real issue that the flag bits are not guaranteed after an x86
shift when the count happened to be zero.

Terje

--
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"

Thomas Koenig <tkoenig@netcologne.de> writes:

> Thomas Koenig <tkoenig@netcologne.de> schrieb:
>
>> Thanks, but I am a technical writer
>
> That should have read "I am not a technical writer".

What you mean is you are not an editor. There is
every indication you qualify as a writer. ;)