On 7/14/2021 12:57 AM, Marcus wrote:
> On 2021-07-14 09:01, David Brown wrote:
>> On 14/07/2021 08:01, Marcus wrote:
>>> On 2021-07-13, Theo Markettos wrote:
>>>
>>> [snip]
>>>
>>>> The hardware is hugely worse in size and power efficiency than the
>>>> neural
>>>> network between our ears, but we pay that cost.
>>>>
>>>
>>> I personally think that the proper implementation of a power efficient
>>> neural network requires two things:
>>>
>>> 1) Memory (signals and weights) should be co-located with the ALU:s (or
>>>     distributed across the compute matrix, if you will).
>>>
>>> 2) Compute cells should only be active when activated by a signal.
>>>     Perhaps the design should not be clocked by a global clock at all?
>>>
>>
>> I agree on both accounts.  (I haven't looked much at neural networks
>> since university, but I assume the principles haven't changed.)
>>
>> A biological neuron encompasses its own memory (weights), its own
>> processing, its own IO, its own learning system.  To make really
>> powerful artificial neural networks, the component parts need that too.
>>   Then you can scale the whole thing by adding more of the same.
>
> Exactly. You'll not be bounded by memory bandwidth or similar - it's a
> truly distributed system that should scale very well.

The problem is the interconnect. In true, i.e. biological, neural nets,
a neuron receives input from thousands of other (apparently, but not
really, random) neurons. The "wires", AKA axons are each insulated (by
Glial cells) to prevent cross talk. You can't replicate this at scale
in a silicon chip without thousands of layers of interconnect.

--
- Stephen Fuld
(e-mail address disguised to prevent spam)

On Wednesday, July 14, 2021 at 6:41:31 PM UTC-5, Stephen Fuld wrote:
> On 7/14/2021 12:57 AM, Marcus wrote:
> > On 2021-07-14 09:01, David Brown wrote:
> >> On 14/07/2021 08:01, Marcus wrote:
> >>> On 2021-07-13, Theo Markettos wrote:
> >>>
> >>> [snip]
> >>>
> >>>> The hardware is hugely worse in size and power efficiency than the
> >>>> neural
> >>>> network between our ears, but we pay that cost.
> >>>>
> >>>
> >>> I personally think that the proper implementation of a power efficient
> >>> neural network requires two things:
> >>>
> >>> 1) Memory (signals and weights) should be co-located with the ALU:s (or
> >>> distributed across the compute matrix, if you will).
> >>>
> >>> 2) Compute cells should only be active when activated by a signal.
> >>> Perhaps the design should not be clocked by a global clock at all?
> >>>
> >>
> >> I agree on both accounts. (I haven't looked much at neural networks
> >> since university, but I assume the principles haven't changed.)
> >>
> >> A biological neuron encompasses its own memory (weights), its own
> >> processing, its own IO, its own learning system. To make really
> >> powerful artificial neural networks, the component parts need that too.
> >> Then you can scale the whole thing by adding more of the same.
> >
> > Exactly. You'll not be bounded by memory bandwidth or similar - it's a
> > truly distributed system that should scale very well.
> The problem is the interconnect. In true, i.e. biological, neural nets,
> a neuron receives input from thousands of other (apparently, but not
> really, random) neurons. The "wires", AKA axons are each insulated (by
> Glial cells) to prevent cross talk. You can't replicate this at scale
> in a silicon chip without thousands of layers of interconnect.
<
Lets make that thousands of layers of transistors ! You need to make both
the transistors and the interconnect 3D.
>
>
> --
> - Stephen Fuld
> (e-mail address disguised to prevent spam)

On Wednesday, July 14, 2021 at 5:56:47 PM UTC-6, MitchAlsup wrote:
> On Wednesday, July 14, 2021 at 6:41:31 PM UTC-5, Stephen Fuld wrote:

> > The problem is the interconnect. In true, i.e. biological, neural nets,
> > a neuron receives input from thousands of other (apparently, but not
> > really, random) neurons. The "wires", AKA axons are each insulated (by
> > Glial cells) to prevent cross talk. You can't replicate this at scale
> > in a silicon chip without thousands of layers of interconnect.

> Lets make that thousands of layers of transistors ! You need to make both
> the transistors and the interconnect 3D.

Ideally. But with current technology, thermal issues mitigate against that.

And with a hundred layers of interconnect, and enough transistors on the
substrate, one could make the same circuit as one could with a hundred layers
of transistors - the interconnect runs would just be ten times longer.

John Savard

On Wednesday, July 14, 2021 at 7:01:49 PM UTC-6, Quadibloc wrote:
> On Wednesday, July 14, 2021 at 5:56:47 PM UTC-6, MitchAlsup wrote:

> > Lets make that thousands of layers of transistors ! You need to make both
> > the transistors and the interconnect 3D.
> Ideally. But with current technology, thermal issues mitigate against that.

Of course, that might be changing soon:

https://www.extremetech.com/computing/324625-tsmc-mulls-on-chip-water-cooling-for-future-high-performance-silicon

John Savard

On Wednesday, July 14, 2021 at 8:11:33 PM UTC-5, Quadibloc wrote:
> On Wednesday, July 14, 2021 at 7:01:49 PM UTC-6, Quadibloc wrote:
> > On Wednesday, July 14, 2021 at 5:56:47 PM UTC-6, MitchAlsup wrote:
>
> > > Lets make that thousands of layers of transistors ! You need to make both
> > > the transistors and the interconnect 3D.
> > Ideally. But with current technology, thermal issues mitigate against that.
> Of course, that might be changing soon:
>
> https://www.extremetech.com/computing/324625-tsmc-mulls-on-chip-water-cooling-for-future-high-performance-silicon
<
This sounds a lot like what Stanford was trying to do (?experimenting?) on
in 1992-ish time frame. Stanford ultimately got 1000W/sq-cm ±
>
> John Savard

Quadibloc [2021-07-14 18:11:32] wrote:
> On Wednesday, July 14, 2021 at 7:01:49 PM UTC-6, Quadibloc wrote:
>> On Wednesday, July 14, 2021 at 5:56:47 PM UTC-6, MitchAlsup wrote:
>> > Lets make that thousands of layers of transistors ! You need to make both
>> > the transistors and the interconnect 3D.
>> Ideally. But with current technology, thermal issues mitigate against that.
> Of course, that might be changing soon:
> https://www.extremetech.com/computing/324625-tsmc-mulls-on-chip-water-cooling-for-future-high-performance-silicon

That seems irrelevant: the real problem is not how to move power away
from the chip, but how to reduce the power per unit of work so as to
last longer on the same battery, or so as to use a smaller battery and
make the device lighter.

I'm thinking here about mobile devices, but the same is true for
data centers. The only exceptions seem to be the desktops, where people
don't seem to care about the cost of the power consumption, so they're
willing to waste money, space, and decibels on heat removal.
But I hear that the market for desktops is shrinking pretty fast.

Stefan

On Wednesday, July 14, 2021 at 7:53:27 PM UTC-6, Stefan Monnier wrote:

> That seems irrelevant: the real problem is not how to move power away
> from the chip, but how to reduce the power per unit of work so as to
> last longer on the same battery, or so as to use a smaller battery and
> make the device lighter.

Irrelevant? The real problem is how to get the work *done*. If power consumption
can be reduced, great. But failing that, removing more heat is the second-best
way to allow more transistors to switch in a tiny space in a given time.

The goal is... to solve problems. To find answers.

John Savard

On Wednesday, July 14, 2021 at 8:39:07 PM UTC-6, Quadibloc wrote:
> On Wednesday, July 14, 2021 at 7:53:27 PM UTC-6, Stefan Monnier wrote:

> > That seems irrelevant: the real problem is not how to move power away
> > from the chip, but how to reduce the power per unit of work so as to
> > last longer on the same battery, or so as to use a smaller battery and
> > make the device lighter.

> Irrelevant? The real problem is how to get the work *done*. If power consumption
> can be reduced, great. But failing that, removing more heat is the second-best
> way to allow more transistors to switch in a tiny space in a given time.
>
> The goal is... to solve problems. To find answers.

And, *of course*, even after one has reduced the amount of power
a processor needs a hundredfold, one _still_ can benefit from some method
of removing heat faster that allows a hundred times as many processors to
be packed into a tiny space so that they can communicate quickly.

There is no end to the problems that need solving.

John Savard

On 7/14/2021 4:56 PM, MitchAlsup wrote:
> On Wednesday, July 14, 2021 at 6:41:31 PM UTC-5, Stephen Fuld wrote:
>> On 7/14/2021 12:57 AM, Marcus wrote:
>>> On 2021-07-14 09:01, David Brown wrote:
>>>> On 14/07/2021 08:01, Marcus wrote:
>>>>> On 2021-07-13, Theo Markettos wrote:
>>>>>
>>>>> [snip]
>>>>>
>>>>>> The hardware is hugely worse in size and power efficiency than the
>>>>>> neural
>>>>>> network between our ears, but we pay that cost.
>>>>>>
>>>>>
>>>>> I personally think that the proper implementation of a power efficient
>>>>> neural network requires two things:
>>>>>
>>>>> 1) Memory (signals and weights) should be co-located with the ALU:s (or
>>>>> distributed across the compute matrix, if you will).
>>>>>
>>>>> 2) Compute cells should only be active when activated by a signal.
>>>>> Perhaps the design should not be clocked by a global clock at all?
>>>>>
>>>>
>>>> I agree on both accounts. (I haven't looked much at neural networks
>>>> since university, but I assume the principles haven't changed.)
>>>>
>>>> A biological neuron encompasses its own memory (weights), its own
>>>> processing, its own IO, its own learning system. To make really
>>>> powerful artificial neural networks, the component parts need that too.
>>>> Then you can scale the whole thing by adding more of the same.
>>>
>>> Exactly. You'll not be bounded by memory bandwidth or similar - it's a
>>> truly distributed system that should scale very well.
>> The problem is the interconnect. In true, i.e. biological, neural nets,
>> a neuron receives input from thousands of other (apparently, but not
>> really, random) neurons. The "wires", AKA axons are each insulated (by
>> Glial cells) to prevent cross talk. You can't replicate this at scale
>> in a silicon chip without thousands of layers of interconnect.
> <
> Lets make that thousands of layers of transistors ! You need to make both
> the transistors and the interconnect 3D.

Perhaps. But other approaches are possible. IBM has done several,
including an analog chip that uses charge in a capacitor, sort of like a
real neuron uses,

https://research.ibm.com/publications/unassisted-true-analog-neural-network-training-chip

but the paper is behind a paywall,

and their True North chip

https://research.ibm.com/articles/brain-chip.shtml

--
- Stephen Fuld
(e-mail address disguised to prevent spam)

On 15/07/2021 01:41, Stephen Fuld wrote:
> On 7/14/2021 12:57 AM, Marcus wrote:
>> On 2021-07-14 09:01, David Brown wrote:
>>> On 14/07/2021 08:01, Marcus wrote:
>>>> On 2021-07-13, Theo Markettos wrote:
>>>>
>>>> [snip]
>>>>
>>>>> The hardware is hugely worse in size and power efficiency than the
>>>>> neural
>>>>> network between our ears, but we pay that cost.
>>>>>
>>>>
>>>> I personally think that the proper implementation of a power efficient
>>>> neural network requires two things:
>>>>
>>>> 1) Memory (signals and weights) should be co-located with the ALU:s (or
>>>>     distributed across the compute matrix, if you will).
>>>>
>>>> 2) Compute cells should only be active when activated by a signal.
>>>>     Perhaps the design should not be clocked by a global clock at all?
>>>>
>>>
>>> I agree on both accounts.  (I haven't looked much at neural networks
>>> since university, but I assume the principles haven't changed.)
>>>
>>> A biological neuron encompasses its own memory (weights), its own
>>> processing, its own IO, its own learning system.  To make really
>>> powerful artificial neural networks, the component parts need that too.
>>>   Then you can scale the whole thing by adding more of the same.
>>
>> Exactly. You'll not be bounded by memory bandwidth or similar - it's a
>> truly distributed system that should scale very well.
>
> The problem is the interconnect.  In true, i.e. biological, neural nets,
> a neuron receives input from thousands of other (apparently, but not
> really, random) neurons.  The "wires", AKA axons are each insulated (by
> Glial cells) to prevent cross talk.  You can't replicate this at scale
> in a silicon chip without thousands of layers of interconnect.
>
>

That is a problem if you are trying to fully replicate biological neural
systems. But that is not a practical aim - at least, not for a long
time yet. In particular, current neural networks are based on layers,
as a compromise between the capability of the networks and our
understanding of algorithms to teach and tune them. I think you can
come a /long/ way with layers that have a lot of interconnects within
the layer, but only connect to adjacent layers rather than having
connections throughout the system.

When you look at biological neural networks, the great majority of
connections are quite local. The number of long-distance connections
drops rapidly with the distance. After all, the scaling, spacing,
power-management and heat management challenges in biology are not much
different from those in silicon. The key difference is that details of
where these connections are made can change somewhat in a biological
system, while they are fixed in silicon.

So you could make your artificial neural networks with a small number of
fixed long-distance connections, rather than trying to support arbitrary
connections across the network.

MitchAlsup <MitchAlsup@aol.com> writes:
>On Tuesday, July 13, 2021 at 3:25:45 PM UTC-5, John Levine wrote:
>> The compiler did what it could to schedule memory references statically,
>> but once you could do that in hardware, dynamic hardware scheduling worked a lot better.
><
>Except for that power thing............

Including that power thing.

E.g., looking at

<https://images.anandtech.com/doci/14072/Exynos9820-Perf-Eff-Estimated.png>

we see that the OoO Cortex-A75 has better Perf/W than the in-order A55
as soon a you need more than 1.5 SPEC2006 Int+FP of performance, and
even if you need less, you fare hardly better.

Intel tried in-order for their low-power line (Atom) with Bonnell,
while AMD went for OoO with Bobcat. Bobcat is twice as fast per cycle
in my testing as Bonnell. Looking at dual-core chips with integrated
graphics, we see

core proc. chip CPU cl. TDP
Bobcat 40nm AMD C-70 1333MHz 9W
Bobcat 40nm AMD E2-2000 1750MHz 18W
Bonnell 45nm Atom D525 1833MHz 13W
Bonnell 32nm Atom D2700 2133MHz 10W

Taking the 2x IPC advantage of Bobcat into account, Bobcat in 40nm in
a 9W power bracket outperforms Bonnell in 32nm in a 10W power bracket.

Later Intel switched their low-power line to OoO with Silvermont, and
has stayed with OoO since.

Apple uses OoO for their energy-efficient cores (Icestorm in the A14).

The only ones who still seem to believe in in-order for
energy-efficient computing are ARM with their Cortex-A510.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

On Thursday, July 15, 2021 at 3:20:50 AM UTC-6, Anton Ertl wrote:

> Later Intel switched their low-power line to OoO with Silvermont, and
> has stayed with OoO since.

Couldn't that just be a consequence of process improvements?

A laptop has a certain power budget; it's bigger than that of a
smartphone.

So, at one point, OoO was only within the power budget of a desktop
computer. When it became possible to make an OoO processor with
a power budget suitable for laptops, of course this was faster than
perhaps having more cores that were in-order.

Today, we're at the point were processors in smartphones are
usually OoO. In-order is now used only for very small embedded
processors. This isn't because OoO doesn't need more transistors
and more power. It's because transistors got smaller and better,
so it was easier and easier to come up with the power that OoO
needed.

John Savard

MitchAlsup <MitchAlsup@aol.com> writes:
>This sounds a lot like what Stanford was trying to do (?experimenting?) on
>in 1992-ish time frame. Stanford ultimately got 1000W/sq-cm =C2=B1

<Heavy speculation>It seems to me that efforts like your AMD K9 and
Intel Tejas were designed with that cooling capacity in mind, and in
2005 it turned out to be not practically doable, and both projects
were canceled.</>

Currently, the power density of hot chips seems to be at maybe
200W/cm^2 (140W for a Ryzen 3800XT with 0.7cm^2 chiplet area), with
higher power density in various spots on the die.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

Anton Ertl <anton@mips.complang.tuwien.ac.at> schrieb:

> Currently, the power density of hot chips seems to be at maybe
> 200W/cm^2 (140W for a Ryzen 3800XT with 0.7cm^2 chiplet area), with
> higher power density in various spots on the die.

That's a high enery density, but it is within the range that
can be removed by pool boiling, certainly of water, possibly
by refrigerants (especially if you have some space between
the chips).

Mechanical stresses on the delicate chips could be another matter,
though.

On 7/15/2021 3:44 AM, Thomas Koenig wrote:
> Anton Ertl <anton@mips.complang.tuwien.ac.at> schrieb:
>
>> Currently, the power density of hot chips seems to be at maybe
>> 200W/cm^2 (140W for a Ryzen 3800XT with 0.7cm^2 chiplet area), with
>> higher power density in various spots on the die.
>
> That's a high enery density, but it is within the range that
> can be removed by pool boiling, certainly of water, possibly
> by refrigerants (especially if you have some space between
> the chips).
>
> Mechanical stresses on the delicate chips could be another matter,
> though.
>

Did you used to work on pressurized water reactors?

Ivan Godard <ivan@millcomputing.com> schrieb:
> On 7/15/2021 3:44 AM, Thomas Koenig wrote:
>> Anton Ertl <anton@mips.complang.tuwien.ac.at> schrieb:
>>
>>> Currently, the power density of hot chips seems to be at maybe
>>> 200W/cm^2 (140W for a Ryzen 3800XT with 0.7cm^2 chiplet area), with
>>> higher power density in various spots on the die.
>>
>> That's a high enery density, but it is within the range that
>> can be removed by pool boiling, certainly of water, possibly
>> by refrigerants (especially if you have some space between
>> the chips).
>>
>> Mechanical stresses on the delicate chips could be another matter,
>> though.
>>

> Did you used to work on pressurized water reactors?

No, but my diploma thesis was in the field of pool boiling,
and the subject of how much heat you can remove by boiling
(a.k.a. the critical heat flux) is a standard topic in studying
chemical engineering.

On 7/15/2021 4:04 AM, Thomas Koenig wrote:
> Ivan Godard <ivan@millcomputing.com> schrieb:
>> On 7/15/2021 3:44 AM, Thomas Koenig wrote:
>>> Anton Ertl <anton@mips.complang.tuwien.ac.at> schrieb:
>>>
>>>> Currently, the power density of hot chips seems to be at maybe
>>>> 200W/cm^2 (140W for a Ryzen 3800XT with 0.7cm^2 chiplet area), with
>>>> higher power density in various spots on the die.
>>>
>>> That's a high enery density, but it is within the range that
>>> can be removed by pool boiling, certainly of water, possibly
>>> by refrigerants (especially if you have some space between
>>> the chips).
>>>
>>> Mechanical stresses on the delicate chips could be another matter,
>>> though.
>>>
>
>> Did you used to work on pressurized water reactors?
>
> No, but my diploma thesis was in the field of pool boiling,
> and the subject of how much heat you can remove by boiling
> (a.k.a. the critical heat flux) is a standard topic in studying
> chemical engineering.
>

My second guess was superheaters in steam locomotives :-)

On Tue, 13 Jul 2021 14:58:48 -0700 (PDT), Quadibloc
<jsavard@ecn.ab.ca> wrote:

>On Tuesday, July 13, 2021 at 6:13:13 AM UTC-6, David Brown wrote:
>
>> What seems to be missing here (at least, /I/ have missed it) is a
>> discusion about what people actually want to do with computing power.
>> Is it fair to suggest that most tasks that people currently want to run
>> faster, are actually reasonably parallel? And that most tasks that
>> people want to run a /lot/ faster are /very/ parallel?
>
>Unfortunately, no, it isn't.
>
>Many of the tasks that people want to run faster are parallel, but some of
>them are not.
>
>Also, it's at least possible that *some* of the tasks people want to run
>faster... are perhaps more parallel than people realize, and some new
>programming paradigm might enable this parallelism to be brought to
>light. At least that's the hope that fuels attempts to design compilers
>that will bring out extra parallelism that's not obvious to human programmers.
>
>John Savard

The problem - at least with current hardware - is that programmers are
much better at identifying what CAN be done in parallel than what
SHOULD be done in parallel.

Starting scads of threads, many (or most) of which will end up blocked
due to lack of memory bandwidth to feed the processor(s), is not a
good idea.

I really like Mitch's VVM. I'm primarily a software guy, but from what
I've understood of it, VVM seems to address a number of the problems
that plague auto-vectorization. Waiting for actual hardware. 8-)

But vectorization is just one aspect of parallelism. There's quite a
lot of micro-thread parallelism inherent in many programs, but getting
compilers to extract it is not easy, and current hardware really is
not designed with micro-threads in mind. Watching the Mill and hoping
it succeeds.

YMMV,
George

On Thursday, July 15, 2021 at 8:32:15 AM UTC-6, George Neuner wrote:

> Starting scads of threads, many (or most) of which will end up blocked
> due to lack of memory bandwidth to feed the processor(s), is not a
> good idea.

That's true. But you can buy bandwidth, while latency tends to be a hard
limit. So that isn't a fatal obstacle to doing things faster, whereas not
knowing any way to do things in parallel would be.

John Savard

On 7/15/2021 1:02 AM, David Brown wrote:
> On 15/07/2021 01:41, Stephen Fuld wrote:
>> On 7/14/2021 12:57 AM, Marcus wrote:
>>> On 2021-07-14 09:01, David Brown wrote:
>>>> On 14/07/2021 08:01, Marcus wrote:
>>>>> On 2021-07-13, Theo Markettos wrote:
>>>>>
>>>>> [snip]
>>>>>
>>>>>> The hardware is hugely worse in size and power efficiency than the
>>>>>> neural
>>>>>> network between our ears, but we pay that cost.
>>>>>>
>>>>>
>>>>> I personally think that the proper implementation of a power efficient
>>>>> neural network requires two things:
>>>>>
>>>>> 1) Memory (signals and weights) should be co-located with the ALU:s (or
>>>>>     distributed across the compute matrix, if you will).
>>>>>
>>>>> 2) Compute cells should only be active when activated by a signal.
>>>>>     Perhaps the design should not be clocked by a global clock at all?
>>>>>
>>>>
>>>> I agree on both accounts.  (I haven't looked much at neural networks
>>>> since university, but I assume the principles haven't changed.)
>>>>
>>>> A biological neuron encompasses its own memory (weights), its own
>>>> processing, its own IO, its own learning system.  To make really
>>>> powerful artificial neural networks, the component parts need that too.
>>>>   Then you can scale the whole thing by adding more of the same.
>>>
>>> Exactly. You'll not be bounded by memory bandwidth or similar - it's a
>>> truly distributed system that should scale very well.
>>
>> The problem is the interconnect.  In true, i.e. biological, neural nets,
>> a neuron receives input from thousands of other (apparently, but not
>> really, random) neurons.  The "wires", AKA axons are each insulated (by
>> Glial cells) to prevent cross talk.  You can't replicate this at scale
>> in a silicon chip without thousands of layers of interconnect.
>>
>>
>
> That is a problem if you are trying to fully replicate biological neural
> systems. But that is not a practical aim - at least, not for a long
> time yet.

Certainly true for humans. Getting closer for flies! :-)

> In particular, current neural networks are based on layers,
> as a compromise between the capability of the networks and our
> understanding of algorithms to teach and tune them. I think you can
> come a /long/ way with layers that have a lot of interconnects within
> the layer, but only connect to adjacent layers rather than having
> connections throughout the system.

"long way" toward what goal? If you want to do engineering, that is, do
useful things, then I certainly agree. If you want to do science, that
is investigate more realistic models to better understand how brains
work, then not so much. (I don't mean to imply that science is useless
- far from it.)

> When you look at biological neural networks, the great majority of
> connections are quite local. The number of long-distance connections
> drops rapidly with the distance. After all, the scaling, spacing,
> power-management and heat management challenges in biology are not much
> different from those in silicon. The key difference is that details of
> where these connections are made can change somewhat in a biological
> system, while they are fixed in silicon.

Yes. Silicon systems emulate the changing connections by having lots of
"excess" connections, many of which have weights such that they are
essentially never used. By changing the weights, you emulate making new
and breaking connections. But this means you still have to have more
long distance connections than are "in use" at any particular time.

> So you could make your artificial neural networks with a small number of
> fixed long-distance connections, rather than trying to support arbitrary
> connections across the network.

Works within the limitations implied by the above.

--
- Stephen Fuld
(e-mail address disguised to prevent spam)

Ivan Godard <ivan@millcomputing.com> schrieb:
> On 7/15/2021 4:04 AM, Thomas Koenig wrote:
>> Ivan Godard <ivan@millcomputing.com> schrieb:
>>> On 7/15/2021 3:44 AM, Thomas Koenig wrote:
>>>> Anton Ertl <anton@mips.complang.tuwien.ac.at> schrieb:
>>>>
>>>>> Currently, the power density of hot chips seems to be at maybe
>>>>> 200W/cm^2 (140W for a Ryzen 3800XT with 0.7cm^2 chiplet area), with
>>>>> higher power density in various spots on the die.
>>>>
>>>> That's a high enery density, but it is within the range that
>>>> can be removed by pool boiling, certainly of water, possibly
>>>> by refrigerants (especially if you have some space between
>>>> the chips).
>>>>
>>>> Mechanical stresses on the delicate chips could be another matter,
>>>> though.
>>>>
>>
>>> Did you used to work on pressurized water reactors?
>>
>> No, but my diploma thesis was in the field of pool boiling,
>> and the subject of how much heat you can remove by boiling
>> (a.k.a. the critical heat flux) is a standard topic in studying
>> chemical engineering.
>>
>
> My second guess was superheaters in steam locomotives :-)

My name is not, and has never been, David Wardale :-) (who, AFAIK,
was the last person to do serious steam locomotive engineering).

#ifdef PEDANTIC

Superheaters do what the name says, they superheat steam.
When steam leaves a boiler, is in equilibrium with the liqid it
is in close contact with. A superheater is a heat exchanger which
increases the temperature further. This is a pure gas-phase heat
exchanger, with much lower heat transfer coefficients, but also
with a much lower heat load, so this is not a big problem.

So, you could in principle use a boiling liquid for cooling
compouter chips if you can solve the mechanical and other assorted
problems, but using a steam superheater would make little sense.

#endif

On Thursday, July 15, 2021 at 9:28:30 AM UTC-6, Thomas Koenig wrote:

> So, you could in principle use a boiling liquid for cooling
> compouter chips if you can solve the mechanical and other assorted
> problems, but using a steam superheater would make little sense.

Yes; even if one uses a working fluid with a sufficiently low boiling
point to be helpful, the point is that one is no longer benefiting from
the large latent heat of condensation. Just like the latent heat of
freezing makes ice so useful in cooling things (but sadly not computer
chips, as the solid phase is inconvenient to move around).

John Savard

On Thursday, July 15, 2021 at 9:28:30 AM UTC-6, Thomas Koenig wrote:

> So, you could in principle use a boiling liquid for cooling
> compouter chips if you can solve the mechanical and other assorted
> problems,

Isn't that what heat pipes use *already*?

John Savard

Quadibloc <jsavard@ecn.ab.ca> schrieb:
> On Thursday, July 15, 2021 at 9:28:30 AM UTC-6, Thomas Koenig wrote:
>
>> So, you could in principle use a boiling liquid for cooling
>> compouter chips if you can solve the mechanical and other assorted
>> problems,
>
> Isn't that what heat pipes use *already*?

Yep, but I was thinking of direct contact of the chips with the
boiling liquid (with a thin insulating laryer, presumably).

_Much_ more efficient. The nice thing is that your temperature
stays pretty much constant as long as there is enough liquid -
no hot edges.

Another nice property is that, if your chips run at 70°C (let's
say) and your vapor comes out the system at 60°C, the vapor is
easy and cheap to condense - even cooling water at 45°C can do it.

Water would be ideal because of its high enthalpy of vaporization
and because you can realize the highest heat fluxes with it.
It is also non-toxic.

However, it has some unpleasant properties for electronics, such
as being rather conductive with only trace amount of ions needed,
so that is probably out. You would also have to run it in a slight
vacuum to get below 100°C, which could be problematic.

So, another liquid would be called for, preferably something legal,
moral and non-fattening, with a boiling point of around 60°C, or
maybe a bit lower.

Hmm... a bit of a search turns up a Wikipedia aricle on
https://en.wikipedia.org/wiki/Novec_649/1230 which cites a source
that this has already been tried by Intel and SGI, so the
idea isn't new (and frankly, I would have been surprised if it was).

https://multimedia.3m.com/mws/media/569865O/3m-novec-engineered-fluid-649.pdf
tells me that the fluid they used has a rather low enthalpy of
vaporization, only 88 kJ/kg. That's not so great, water has
2100 kJ/kg and many other organic liquids have around 300.

Soo... maybe do a better insulation, put the chips on stacks and
build it all up like a plate heat exchanger.

(And no, I'm not 100% serious.)

On Thursday, July 15, 2021 at 12:57:10 PM UTC-5, Thomas Koenig wrote:
> Quadibloc <jsa...@ecn.ab.ca> schrieb:
> > On Thursday, July 15, 2021 at 9:28:30 AM UTC-6, Thomas Koenig wrote:
> >
> >> So, you could in principle use a boiling liquid for cooling
> >> compouter chips if you can solve the mechanical and other assorted
> >> problems,
> >
> > Isn't that what heat pipes use *already*?
> Yep, but I was thinking of direct contact of the chips with the
> boiling liquid (with a thin insulating laryer, presumably).
>
> _Much_ more efficient. The nice thing is that your temperature
> stays pretty much constant as long as there is enough liquid -
> no hot edges.
<
And a bit more dangerous. Boiling a liquid requires the liquid to
create bubbles (of the gas) and these bubbles invariably form at
the solid liquid interface. These microscopic bubbles can lift the
solid surface one atom at a time causing the surface to decompose
over time--limiting lifetime.
<
Non-boiling temperature transfer has much longer actual lifetimes.
>
> Another nice property is that, if your chips run at 70°C (let's
> say) and your vapor comes out the system at 60°C, the vapor is
> easy and cheap to condense - even cooling water at 45°C can do it.
>
> Water would be ideal because of its high enthalpy of vaporization
> and because you can realize the highest heat fluxes with it.
> It is also non-toxic.
>
> However, it has some unpleasant properties for electronics, such
> as being rather conductive with only trace amount of ions needed,
> so that is probably out. You would also have to run it in a slight
> vacuum to get below 100°C, which could be problematic.
>
> So, another liquid would be called for, preferably something legal,
> moral and non-fattening, with a boiling point of around 60°C, or
> maybe a bit lower.
>
> Hmm... a bit of a search turns up a Wikipedia aricle on
> https://en.wikipedia.org/wiki/Novec_649/1230 which cites a source
> that this has already been tried by Intel and SGI, so the
> idea isn't new (and frankly, I would have been surprised if it was).
>
> https://multimedia.3m.com/mws/media/569865O/3m-novec-engineered-fluid-649..pdf
> tells me that the fluid they used has a rather low enthalpy of
> vaporization, only 88 kJ/kg. That's not so great, water has
> 2100 kJ/kg and many other organic liquids have around 300.
>
> Soo... maybe do a better insulation, put the chips on stacks and
> build it all up like a plate heat exchanger.
>
> (And no, I'm not 100% serious.)