novaBBS - comp.arch - Re: Vector ISA Categorisation

Re: Vector ISA Categorisation

<f67a4cee-9189-45cd-9b6c-9cd11b513d1en@googlegroups.com>

https://www.novabbs.com/devel/article-flat.php?id=19634&group=comp.arch#19634

X-Received: by 2002:a05:620a:1999:: with SMTP id bm25mr16399285qkb.329.1628405696782;
Sat, 07 Aug 2021 23:54:56 -0700 (PDT)
X-Received: by 2002:a9d:365:: with SMTP id 92mr10263730otv.240.1628405696485;
Sat, 07 Aug 2021 23:54:56 -0700 (PDT)
Path: i2pn2.org!i2pn.org!paganini.bofh.team!usenet.pasdenom.info!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail
Newsgroups: comp.arch
Date: Sat, 7 Aug 2021 23:54:56 -0700 (PDT)
In-Reply-To: <6793e2d8-873d-4033-931b-e257af0b2a9fn@googlegroups.com>
Injection-Info: google-groups.googlegroups.com; posting-host=2001:56a:f39d:2c00:4827:33ef:c996:96a2;
posting-account=1nOeKQkAAABD2jxp4Pzmx9Hx5g9miO8y
NNTP-Posting-Host: 2001:56a:f39d:2c00:4827:33ef:c996:96a2
References: <sb6s70$dip$1@newsreader4.netcologne.de> <sb99gi$1r5$1@newsreader4.netcologne.de>
<sbh665$sht$1@dont-email.me> <sbubiu$unp$1@dont-email.me> <sbudg8$aje$1@dont-email.me>
<sc12qv$8ka$1@dont-email.me> <sc186o$gns$1@dont-email.me> <sc5cg5$a3p$1@dont-email.me>
<sc5fh8$p7q$1@dont-email.me> <sc8pjr$8ib$1@dont-email.me> <sc8uoc$2tc$1@dont-email.me>
<sc9iib$3ei$1@dont-email.me> <scac7e$ph4$1@dont-email.me> <63597d55-f5bd-42fc-bae3-38155d072128n@googlegroups.com>
<scan92$k7m$1@dont-email.me> <dc5c8894-e51d-46a8-b682-9784fb8ac205n@googlegroups.com>
<9020308c-08e6-4f4f-b29f-e4320c19b1c2n@googlegroups.com> <2336ffa3-df90-461a-a1cb-51147dfc504dn@googlegroups.com>
<9a596e40-0c21-4b4c-83b1-56c745dd199cn@googlegroups.com> <sceb52$b4t$1@dont-email.me>
<0e87d075-e620-4173-accc-e16e0adbba35n@googlegroups.com> <scgi37$u7v$1@dont-email.me>
<57a0784c-b114-460e-af96-9930e94441f3n@googlegroups.com> <schqua$k02$1@dont-email.me>
<999476a5-100e-49dc-9a06-4550a7c928f0n@googlegroups.com> <scjk6o$rme$1@dont-email.me>
<fbf6751b-6b88-4283-92ea-1fff4b7fe200n@googlegroups.com> <863e6886-f580-4cce-aaef-ddf8d6baa4dfn@googlegroups.com>
<5deba2bb-fa46-43e7-a8f2-01bc5cffb519n@googlegroups.com> <ca4a2e3b-0589-4b4a-8447-39128dab7af8n@googlegroups.com>
<7dc19ec1-a43d-4868-ad8b-7f03c320012fn@googlegroups.com> <f6590a76-2e16-486d-baf8-879ebdf36266n@googlegroups.com>
<9cb2db22-9778-4e1b-bcc4-71005c225c73n@googlegroups.com> <a688aab7-5ba9-4f22-8817-1060c3b29375n@googlegroups.com>
<0785c4c1-b891-4b0a-8fa9-d712ea178e1en@googlegroups.com> <8f0d50a6-897a-4924-84f9-f790395c90e9n@googlegroups.com>
<9260f971-4fd2-487c-ab00-249ca72f29a4n@googlegroups.com> <5a96aea9-fac3-4a98-939a-58bb54e493ddn@googlegroups.com>
<994b54f1-8600-40ca-a42e-f96946ccd86en@googlegroups.com> <f412574c-c964-44ca-aed6-a12ac40c8e83n@googlegroups.com>
<da6d3279-6156-4d68-8b8d-4296634a3d47n@googlegroups.com> <821cf9de-a741-4af7-8e2c-0989ab3a9c0cn@googlegroups.com>
<6793e2d8-873d-4033-931b-e257af0b2a9fn@googlegroups.com>
User-Agent: G2/1.0
MIME-Version: 1.0
Message-ID: <f67a4cee-9189-45cd-9b6c-9cd11b513d1en@googlegroups.com>
Subject: Re: Vector ISA Categorisation
From: jsav...@ecn.ab.ca (Quadibloc)
Injection-Date: Sun, 08 Aug 2021 06:54:56 +0000
Content-Type: text/plain; charset="UTF-8"

by: Quadibloc - Sun, 8 Aug 2021 06:54 UTC

On Saturday, August 7, 2021 at 8:10:00 AM UTC-6, Quadibloc wrote:
> On Saturday, August 7, 2021 at 4:17:11 AM UTC-6, luke.l...@gmail.com wrote:
>
> > what i really like about what you came up with (the original version)
> > is that the number of bits used for signalling sizes is a completely
> > parallel one... but it's also about the same number of bits used *for*
> > signalling as in RISC-V.
> Thank you. Of course, though, I'm only able to do this because a
> signalling bit intrudes on every 16-bit instruction slot.
>
> That is possible because in this restricted 16-bit instruction format,
> I am not using displacements longer than 15 bits.
>
> When I use full 16-bit displacements, and I also have immediates
> that might be 16, 32, or 64 bits, with no possibility of a signalling
> bit intruding on that space, normally I would have no option of using
> a completely parallel scheme - at least, not one of this general kind.
>
> In some previous incarnations of Concertina II, I switched to 18-bit
> instruction slots so I could combine 16-bit displacements with parallel
> encoding. (Immediates, though, were handled through block headers.)
>
> So this is why the other instruction formats use block headers to
> attain O(1) decoding instead.

The page has now been updated at

http://www.quadibloc.com/arch/cp0101.htm

to reflect the new encoding scheme.

John Savard

Re: Vector ISA Categorisation

<e99ff33a-a323-436c-8334-0c3b354eda04n@googlegroups.com>

copy mid

https://www.novabbs.com/devel/article-flat.php?id=19682&group=comp.arch#19682

copy link Newsgroups: comp.arch

X-Received: by 2002:a05:6214:c6f:: with SMTP id t15mr21719511qvj.52.1628482040179;
Sun, 08 Aug 2021 21:07:20 -0700 (PDT)
X-Received: by 2002:aca:686:: with SMTP id 128mr15041152oig.119.1628482039930;
Sun, 08 Aug 2021 21:07:19 -0700 (PDT)
Path: i2pn2.org!i2pn.org!weretis.net!feeder8.news.weretis.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail
Newsgroups: comp.arch
Date: Sun, 8 Aug 2021 21:07:19 -0700 (PDT)
In-Reply-To: <f67a4cee-9189-45cd-9b6c-9cd11b513d1en@googlegroups.com>
Injection-Info: google-groups.googlegroups.com; posting-host=2001:56a:f39d:2c00:8d94:f663:223a:c43d;
posting-account=1nOeKQkAAABD2jxp4Pzmx9Hx5g9miO8y
NNTP-Posting-Host: 2001:56a:f39d:2c00:8d94:f663:223a:c43d
References: <sb6s70$dip$1@newsreader4.netcologne.de> <sb99gi$1r5$1@newsreader4.netcologne.de>
<sbh665$sht$1@dont-email.me> <sbubiu$unp$1@dont-email.me> <sbudg8$aje$1@dont-email.me>
<sc12qv$8ka$1@dont-email.me> <sc186o$gns$1@dont-email.me> <sc5cg5$a3p$1@dont-email.me>
<sc5fh8$p7q$1@dont-email.me> <sc8pjr$8ib$1@dont-email.me> <sc8uoc$2tc$1@dont-email.me>
<sc9iib$3ei$1@dont-email.me> <scac7e$ph4$1@dont-email.me> <63597d55-f5bd-42fc-bae3-38155d072128n@googlegroups.com>
<scan92$k7m$1@dont-email.me> <dc5c8894-e51d-46a8-b682-9784fb8ac205n@googlegroups.com>
<9020308c-08e6-4f4f-b29f-e4320c19b1c2n@googlegroups.com> <2336ffa3-df90-461a-a1cb-51147dfc504dn@googlegroups.com>
<9a596e40-0c21-4b4c-83b1-56c745dd199cn@googlegroups.com> <sceb52$b4t$1@dont-email.me>
<0e87d075-e620-4173-accc-e16e0adbba35n@googlegroups.com> <scgi37$u7v$1@dont-email.me>
<57a0784c-b114-460e-af96-9930e94441f3n@googlegroups.com> <schqua$k02$1@dont-email.me>
<999476a5-100e-49dc-9a06-4550a7c928f0n@googlegroups.com> <scjk6o$rme$1@dont-email.me>
<fbf6751b-6b88-4283-92ea-1fff4b7fe200n@googlegroups.com> <863e6886-f580-4cce-aaef-ddf8d6baa4dfn@googlegroups.com>
<5deba2bb-fa46-43e7-a8f2-01bc5cffb519n@googlegroups.com> <ca4a2e3b-0589-4b4a-8447-39128dab7af8n@googlegroups.com>
<7dc19ec1-a43d-4868-ad8b-7f03c320012fn@googlegroups.com> <f6590a76-2e16-486d-baf8-879ebdf36266n@googlegroups.com>
<9cb2db22-9778-4e1b-bcc4-71005c225c73n@googlegroups.com> <a688aab7-5ba9-4f22-8817-1060c3b29375n@googlegroups.com>
<0785c4c1-b891-4b0a-8fa9-d712ea178e1en@googlegroups.com> <8f0d50a6-897a-4924-84f9-f790395c90e9n@googlegroups.com>
<9260f971-4fd2-487c-ab00-249ca72f29a4n@googlegroups.com> <5a96aea9-fac3-4a98-939a-58bb54e493ddn@googlegroups.com>
<994b54f1-8600-40ca-a42e-f96946ccd86en@googlegroups.com> <f412574c-c964-44ca-aed6-a12ac40c8e83n@googlegroups.com>
<da6d3279-6156-4d68-8b8d-4296634a3d47n@googlegroups.com> <821cf9de-a741-4af7-8e2c-0989ab3a9c0cn@googlegroups.com>
<6793e2d8-873d-4033-931b-e257af0b2a9fn@googlegroups.com> <f67a4cee-9189-45cd-9b6c-9cd11b513d1en@googlegroups.com>
User-Agent: G2/1.0
MIME-Version: 1.0
Message-ID: <e99ff33a-a323-436c-8334-0c3b354eda04n@googlegroups.com>
Subject: Re: Vector ISA Categorisation
From: jsav...@ecn.ab.ca (Quadibloc)
Injection-Date: Mon, 09 Aug 2021 04:07:20 +0000
Content-Type: text/plain; charset="UTF-8"

by: Quadibloc - Mon, 9 Aug 2021 04:07 UTC

On Sunday, August 8, 2021 at 12:54:57 AM UTC-6, Quadibloc wrote:

> The page has now been updated at
>
> http://www.quadibloc.com/arch/cp0101.htm
>
> to reflect the new encoding scheme.

Corrections have been made, to remove addressing modes
not applicable when indexing is not available.

As well, another class of 32-bit memory reference instructions,
the multiple-register load and store instructions, was added,
as sufficient opcode space was available.

Also, a description of the variouis addressing modes for memory-reference
instructions was added to the previous page:

http://www.quadibloc.com/arch/cp01.htm

from a previous iteration of the Concertina II instruction set; it got lost along
the way since now only the extended version of the instruction set has all five
modes in a single instruction format.

John Savard

Subject	Author
Split register files	Thomas Koenig
Re: Split register files	Ivan Godard
Re: Split register files	Thomas Koenig
Re: Split register files	Brett
Re: Split register files	Thomas Koenig
Re: Split register files	Brett
Re: Split register files	Brett
Re: Split register files	Ivan Godard
Re: Split register files	Brett
Re: Split register files	Ivan Godard
Re: Split register files	Stefan Monnier
Re: Split register files	Ivan Godard
Re: Split register files	Stephen Fuld
Re: Split register files	Stefan Monnier
Rescue vs scratchpad (was: Split register files)	Stefan Monnier
Re: Rescue vs scratchpad (was: Split register files)	Ivan Godard
Re: Split register files	Brett
Re: Split register files	Ivan Godard
Re: Split register files	Brett
Re: Split register files	Ivan Godard
Re: Mill conAsm vs genAsm (was: Split register files)	Marcus
Re: Mill conAsm vs genAsm (was: Split register files)	Ivan Godard
Re: Mill conAsm vs genAsm (was: Split register files)	Quadibloc
Re: Mill conAsm vs genAsm (was: Split register files)	Ivan Godard
Re: Mill conAsm vs genAsm (was: Split register files)	MitchAlsup
Re: Mill conAsm vs genAsm (was: Split register files)	Quadibloc
Re: Mill conAsm vs genAsm (was: Split register files)	MitchAlsup
Re: Mill conAsm vs genAsm (was: Split register files)	Quadibloc
Re: Mill conAsm vs genAsm (was: Split register files)	Marcus
Re: Mill conAsm vs genAsm (was: Split register files)	Quadibloc
Re: Mill conAsm vs genAsm (was: Split register files)	Marcus
Vector ISA Categorisation	luke.l...@gmail.com
Re: Vector ISA Categorisation	Stephen Fuld
Re: Vector ISA Categorisation	luke.l...@gmail.com
Re: Vector ISA Categorisation	Stefan Monnier
Re: Vector ISA Categorisation	Stephen Fuld
Re: Vector ISA Categorisation	Marcus
Re: Vector ISA Categorisation	luke.l...@gmail.com
Re: Vector ISA Categorisation	mbitsnbites
Re: Vector ISA Categorisation	luke.l...@gmail.com
Re: Vector ISA Categorisation	Marcus
Re: Vector ISA Categorisation	MitchAlsup
Re: Vector ISA Categorisation	Quadibloc
Re: Vector ISA Categorisation	Quadibloc
Re: Vector ISA Categorisation	MitchAlsup
Re: Vector ISA Categorisation	MitchAlsup
Re: Vector ISA Categorisation	Quadibloc
Re: Vector ISA Categorisation	Ivan Godard
Re: Vector ISA Categorisation	Quadibloc
Re: Vector ISA Categorisation	MitchAlsup
Re: Vector ISA Categorisation	Quadibloc
Re: Vector ISA Categorisation	Quadibloc
Re: Vector ISA Categorisation	MitchAlsup
Re: Vector ISA Categorisation	Quadibloc
Re: Vector ISA Categorisation	MitchAlsup
Re: Vector ISA Categorisation	Quadibloc
Re: Vector ISA Categorisation	Quadibloc
Re: Vector ISA Categorisation	Quadibloc
Re: Vector ISA Categorisation	luke.l...@gmail.com
Re: Vector ISA Categorisation	Quadibloc
Re: Vector ISA Categorisation	Quadibloc
Re: Vector ISA Categorisation	Quadibloc
Re: Vector ISA Categorisation	luke.l...@gmail.com
Re: Vector ISA Categorisation	Quadibloc
Re: Vector ISA Categorisation	Marcus
Re: Vector ISA Categorisation	Quadibloc
Re: Vector ISA Categorisation	Quadibloc
Re: Vector ISA Categorisation	luke.l...@gmail.com
Re: Vector ISA Categorisation	Quadibloc
Re: Vector ISA Categorisation	Quadibloc
Re: Vector ISA Categorisation	Quadibloc
Re: Vector ISA Categorisation	MitchAlsup
Re: Vector ISA Categorisation	luke.l...@gmail.com
Re: Vector ISA Categorisation	MitchAlsup
Re: Vector ISA Categorisation	luke.l...@gmail.com
Re: Vector ISA Categorisation	Thomas Koenig
Re: Vector ISA Categorisation	luke.l...@gmail.com
Re: Vector ISA Categorisation	Ivan Godard
Re: Vector ISA Categorisation	Thomas Koenig
Re: Vector ISA Categorisation	MitchAlsup
Re: Vector ISA Categorisation	EricP
Re: Vector ISA Categorisation	Stefan Monnier
Re: Vector ISA Categorisation	MitchAlsup
Re: Vector ISA Categorisation	MitchAlsup
Re: Vector ISA Categorisation	EricP
Re: Vector ISA Categorisation	MitchAlsup
Re: Vector ISA Categorisation	Quadibloc
Re: Vector ISA Categorisation	Thomas Koenig
Re: Vector ISA Categorisation	MitchAlsup
Re: Vector ISA Categorisation	Thomas Koenig
Re: Vector ISA Categorisation	MitchAlsup
Re: Vector ISA Categorisation	luke.l...@gmail.com
Re: Vector ISA Categorisation	luke.l...@gmail.com
Re: Vector ISA Categorisation	MitchAlsup
Re: Vector ISA Categorisation	luke.l...@gmail.com
Re: Vector ISA Categorisation	MitchAlsup
Re: Vector ISA Categorisation	MitchAlsup
Re: Vector ISA Categorisation	Terje Mathisen
Re: Vector ISA Categorisation	MitchAlsup
Re: Vector ISA Categorisation	MitchAlsup
Re: Vector ISA Categorisation	luke.l...@gmail.com
Re: Vector ISA Categorisation	MitchAlsup
Re: Mill conAsm vs genAsm (was: Split register files)	Quadibloc
Re: Mill conAsm vs genAsm (was: Split register files)	luke.l...@gmail.com
Re: Mill conAsm vs genAsm (was: Split register files)	Paul A. Clayton
Re: Mill conAsm vs genAsm	Stefan Monnier
Re: Split register files	Stefan Monnier
Re: Split register files	Thomas Koenig
Re: Split register files	John Dallman
Re: Split register files	Anton Ertl
Re: Split register files	Stefan Monnier
Re: Split register files	MitchAlsup

Real Users know your home telephone number.

devel / comp.arch / Re: Vector ISA Categorisation