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devel / comp.arch.fpga / Re: Is there any software I can use to transform state machines in VHDL into drawings?

SubjectAuthor
* Is there any software I can use to transform state machines in VHDLTianxiang Weng
+* Re: Is there any software I can use to transform state machines inkkoorndyk
|`* Re: Is there any software I can use to transform state machines inTianxiang Weng
| `* Re: Is there any software I can use to transform state machines inThomas Koenig
|  `* Re: Is there any software I can use to transform state machines inTianxiang Weng
|   `- Re: Is there any software I can use to transform state machines in VHDL into draTheo
+- Re: Is there any software I can use to transform state machines inGuy Eschemann
`- Re: Is there any software I can use to transform state machines inSvenn Are Bjerkem

1
Is there any software I can use to transform state machines in VHDL into drawings?

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Subject: Is there any software I can use to transform state machines in VHDL
into drawings?
From: wtx...@gmail.com (Tianxiang Weng)
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 by: Tianxiang Weng - Wed, 8 Sep 2021 20:24 UTC

Hi,
I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings.

Is there any software I can use to transform state machines in VHDL into drawings?

Thank you.

Weng

Re: Is there any software I can use to transform state machines in VHDL into drawings?

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Subject: Re: Is there any software I can use to transform state machines in
VHDL into drawings?
From: kris.koo...@gmail.com (kkoorndyk)
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 by: kkoorndyk - Thu, 9 Sep 2021 15:01 UTC

On Wednesday, September 8, 2021 at 4:24:49 PM UTC-4, Tianxiang Weng wrote:
> Hi,
> I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings.
>
> Is there any software I can use to transform state machines in VHDL into drawings?
>
> Thank you.
>
> Weng

Questasim has a FSM debugger option that generates a graphical view of your state machine, but it's not always a great view for documentation purposes.

Re: Is there any software I can use to transform state machines in VHDL into drawings?

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Subject: Re: Is there any software I can use to transform state machines in
VHDL into drawings?
From: wtx...@gmail.com (Tianxiang Weng)
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 by: Tianxiang Weng - Thu, 9 Sep 2021 20:44 UTC

On Thursday, September 9, 2021 at 8:01:46 AM UTC-7, kkoorndyk wrote:
> On Wednesday, September 8, 2021 at 4:24:49 PM UTC-4, Tianxiang Weng wrote:
> > Hi,
> > I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings.
> >
> > Is there any software I can use to transform state machines in VHDL into drawings?
> >
> > Thank you.
> >
> > Weng
> Questasim has a FSM debugger option that generates a graphical view of your state machine, but it's not always a great view for documentation purposes.

What I have been developing is a set of new hardware circuits that have been never used. I want to apply for patents with full state machines design disclosed. For correctness, the state machines block diagrams should be consistent with the source code in VHDL. So I am seeking such tools. Now I have to draw block diagrams manually, it may introduce inconsistence.

Weng

Re: Is there any software I can use to transform state machines in VHDL into drawings?

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From: tkoe...@netcologne.de (Thomas Koenig)
Newsgroups: comp.arch.fpga
Subject: Re: Is there any software I can use to transform state machines in
VHDL into drawings?
Date: Fri, 10 Sep 2021 10:24:01 -0000 (UTC)
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 by: Thomas Koenig - Fri, 10 Sep 2021 10:24 UTC

Tianxiang Weng <wtxwtx@gmail.com> schrieb:
> On Thursday, September 9, 2021 at 8:01:46 AM UTC-7, kkoorndyk wrote:
>> On Wednesday, September 8, 2021 at 4:24:49 PM UTC-4, Tianxiang Weng wrote:
>> > Hi,
>> > I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings.
>> >
>> > Is there any software I can use to transform state machines in VHDL into drawings?
>> >
>> > Thank you.
>> >
>> > Weng
>> Questasim has a FSM debugger option that generates a graphical view of your state machine, but it's not always a great view for documentation purposes.
>
> What I have been developing is a set of new hardware circuits that have been never used. I want to apply for patents with full state machines design disclosed. For correctness, the state machines block diagrams should be consistent with the source code in VHDL. So I am seeking such tools. Now I have to draw block diagrams manually, it may introduce inconsistence.

You could use https://github.com/hneemann/Digital to draw your state
machines, then export to VHDL.

Re: Is there any software I can use to transform state machines in VHDL into drawings?

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Subject: Re: Is there any software I can use to transform state machines in
VHDL into drawings?
From: wtx...@gmail.com (Tianxiang Weng)
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 by: Tianxiang Weng - Fri, 10 Sep 2021 19:35 UTC

On Friday, September 10, 2021 at 3:24:05 AM UTC-7, Thomas Koenig wrote:
> Tianxiang Weng <wtx...@gmail.com> schrieb:
> > On Thursday, September 9, 2021 at 8:01:46 AM UTC-7, kkoorndyk wrote:
> >> On Wednesday, September 8, 2021 at 4:24:49 PM UTC-4, Tianxiang Weng wrote:
> >> > Hi,
> >> > I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings.
> >> >
> >> > Is there any software I can use to transform state machines in VHDL into drawings?
> >> >
> >> > Thank you.
> >> >
> >> > Weng
> >> Questasim has a FSM debugger option that generates a graphical view of your state machine, but it's not always a great view for documentation purposes.
> >
> > What I have been developing is a set of new hardware circuits that have been never used. I want to apply for patents with full state machines design disclosed. For correctness, the state machines block diagrams should be consistent with the source code in VHDL. So I am seeking such tools. Now I have to draw block diagrams manually, it may introduce inconsistency.
> You could use https://github.com/hneemann/Digital to draw your state
> machines, then export to VHDL.

Thomas Koenig,
I reviewed the website https://github.com/hneemann/Digital; it is a wonderful product, but I prefer my coding practice: using VHDL and drawing mutually to complete a complex state machine. I use Intel Visio to draw state machine block diagrams.

When reviewing a state machine design, it is easier to use state machine block diagrams.

Thank you.

Weng

Re: Is there any software I can use to transform state machines in VHDL into drawings?

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From: theom+n...@chiark.greenend.org.uk (Theo)
Newsgroups: comp.arch.fpga
Subject: Re: Is there any software I can use to transform state machines in VHDL into drawings?
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 by: Theo - Sat, 18 Sep 2021 20:56 UTC

Tianxiang Weng <wtxwtx@gmail.com> wrote:
> When reviewing a state machine design, it is easier to use state machine
> block diagrams.

A codebase I look after puts $display statements in the code that print
Graphviz code for each state in the state machine. The testbench exercises
the code to pass through all the states. When run, you pipe the output into
a .dot file and feed that into Graphviz, which will generate a PNG, SVG,
PDF of the state transition diagram.

It's a hack, but it works well enough.

Theo

Re: Is there any software I can use to transform state machines in VHDL into drawings?

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Subject: Re: Is there any software I can use to transform state machines in
VHDL into drawings?
From: guy.esch...@gmail.com (Guy Eschemann)
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 by: Guy Eschemann - Tue, 5 Oct 2021 11:26 UTC

I believe the Sigasi editor has something like that: https://insights.sigasi.com/manual/views/#state-machine-view

Cheers,
Guy.

On Wednesday, September 8, 2021 at 10:24:49 PM UTC+2, Tianxiang Weng wrote:
> Hi,
> I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings.
>
> Is there any software I can use to transform state machines in VHDL into drawings?
>
> Thank you.
>
> Weng

Re: Is there any software I can use to transform state machines in VHDL into drawings?

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Subject: Re: Is there any software I can use to transform state machines in
VHDL into drawings?
From: svenn.bj...@gmail.com (Svenn Are Bjerkem)
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 by: Svenn Are Bjerkem - Fri, 5 Nov 2021 22:53 UTC

TerosHDL plugin in VSCode has some rudimentary state-machine detection

1
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