Rocksolid Light

Welcome to novaBBS (click a section below)

mail  files  register  newsreader  groups  login

Message-ID:  

All laws are simulations of reality. -- John C. Lilly


devel / comp.arch / On diodes (answer to a poster at RWT.com)

SubjectAuthor
* On diodes (answer to a poster at RWT.com)Vasco Costa
+* Re: On diodes (answer to a poster at RWT.com)Quadibloc
|+* Re: On diodes (answer to a poster at RWT.com)Vasco Costa
||+* Re: On diodes (answer to a poster at RWT.com)Anton Ertl
|||`* Re: On diodes (answer to a poster at RWT.com)Quadibloc
||| +* Re: On diodes (answer to a poster at RWT.com)Anton Ertl
||| |`* Re: On diodes (answer to a poster at RWT.com)David Brown
||| | +* Re: On diodes (answer to a poster at RWT.com)MitchAlsup
||| | |`- Re: On diodes (answer to a poster at RWT.com)Thomas Koenig
||| | +* Re: On diodes (answer to a poster at RWT.com)Quadibloc
||| | |+- Re: On diodes (answer to a poster at RWT.com)David Brown
||| | |`* Re: On diodes (answer to a poster at RWT.com)antispam
||| | | +- Re: On diodes (answer to a poster at RWT.com)Thomas Koenig
||| | | `- Re: On diodes (answer to a poster at RWT.com)EricP
||| | `- Re: On diodes (answer to a poster at RWT.com)Anton Ertl
||| `* Re: On diodes (answer to a poster at RWT.com)MitchAlsup
|||  `- Re: On diodes (answer to a poster at RWT.com)Michael S
||`* Re: On diodes (answer to a poster at RWT.com)Quadibloc
|| `* Re: On diodes (answer to a poster at RWT.com)Theo Markettos
||  `* Re: On diodes (answer to a poster at RWT.com)Quadibloc
||   `* Re: On diodes (answer to a poster at RWT.com)Thomas Koenig
||    +* Re: On diodes (answer to a poster at RWT.com)Niklas Holsti
||    |+* Re: On diodes (answer to a poster at RWT.com)Theo Markettos
||    ||`- Re: On diodes (answer to a poster at RWT.com)Anton Ertl
||    |`* Re: On diodes (answer to a poster at RWT.com)Anton Ertl
||    | +- Re: On diodes (answer to a poster at RWT.com)MitchAlsup
||    | +* Re: On diodes (answer to a poster at RWT.com)Thomas Koenig
||    | |+* Re: On diodes (answer to a poster at RWT.com)Anton Ertl
||    | ||`* Re: On diodes (answer to a poster at RWT.com)Theo Markettos
||    | || `* Re: On diodes (answer to a poster at RWT.com)MitchAlsup
||    | ||  `* Re: On diodes (answer to a poster at RWT.com)Theo Markettos
||    | ||   `* Re: On diodes (answer to a poster at RWT.com)Anton Ertl
||    | ||    `- Re: On diodes (answer to a poster at RWT.com)EricP
||    | |`- Re: On diodes (answer to a poster at RWT.com)MitchAlsup
||    | `* Re: On diodes (answer to a poster at RWT.com)Niklas Holsti
||    |  `- Re: On diodes (answer to a poster at RWT.com)Thomas Koenig
||    `* Re: On diodes (answer to a poster at RWT.com)MitchAlsup
||     `* Re: On diodes (answer to a poster at RWT.com)Thomas Koenig
||      +* Re: On diodes (answer to a poster at RWT.com)Anton Ertl
||      |+- Re: On diodes (answer to a poster at RWT.com)MitchAlsup
||      |+- Re: On diodes (answer to a poster at RWT.com)Thomas Koenig
||      |`- Re: On diodes (answer to a poster at RWT.com)Anton Ertl
||      `* Re: On diodes (answer to a poster at RWT.com)MitchAlsup
||       `- Re: On diodes (answer to a poster at RWT.com)Thomas Koenig
|`- Re: On diodes (answer to a poster at RWT.com)MitchAlsup
+- Re: On diodes (answer to a poster at RWT.com)Joe Pfeiffer
`- Re: On diodes (answer to a poster at RWT.com)Paul A. Clayton

Pages:12
On diodes (answer to a poster at RWT.com)

<1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com>

 copy mid

https://www.novabbs.com/devel/article-flat.php?id=20112&group=comp.arch#20112

 copy link   Newsgroups: comp.arch
X-Received: by 2002:ad4:4533:: with SMTP id l19mr24774967qvu.55.1629884716686;
Wed, 25 Aug 2021 02:45:16 -0700 (PDT)
X-Received: by 2002:a05:6808:f90:: with SMTP id o16mr1312399oiw.37.1629884716486;
Wed, 25 Aug 2021 02:45:16 -0700 (PDT)
Path: i2pn2.org!i2pn.org!paganini.bofh.team!usenet.pasdenom.info!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail
Newsgroups: comp.arch
Date: Wed, 25 Aug 2021 02:45:16 -0700 (PDT)
Injection-Info: google-groups.googlegroups.com; posting-host=144.64.185.162; posting-account=68D3awoAAABKe1mUbulBNmV4G3MrhsQ_
NNTP-Posting-Host: 144.64.185.162
User-Agent: G2/1.0
MIME-Version: 1.0
Message-ID: <1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com>
Subject: On diodes (answer to a poster at RWT.com)
From: vasco.co...@gmail.com (Vasco Costa)
Injection-Date: Wed, 25 Aug 2021 09:45:16 +0000
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
 by: Vasco Costa - Wed, 25 Aug 2021 09:45 UTC

In answer to a user's mention of "diode logic" the proof is in the pudding.

This one knows someone else who used to work on TVs who had the hots for diodes yet transistors won. This is thanks to a massive support for transistors which goes all the way to the regular transistor gate. Unless you replace the entire edifice, like, work with Synopsys to completely generate something with that logic from a higher level language AND make it competitive with transistors it won't win. Plus it needs to be manufacturable. We have had all sorts of things which supposedly would win over transistor logic including superconductors and other exotic stuff. Even Gallium Arsenide and Nitride are having issues competing with bulk silicon in many older applications. Plus today we have dopants and strained silicon. If these diodes can be made with existing semi machine tools and materials effectively then you may have a chance. But if you insist on a product which, like, needs to be baked for 10x the time of a regular transistor, well, then just plain forget it for anything but niche applications. We have enough of an issue producing enough silicon.

I miss anonymous posting in the main RWT.com threads. *sniff*

Re: On diodes (answer to a poster at RWT.com)

<8837d585-222c-46fd-b23a-d775a93efcd4n@googlegroups.com>

 copy mid

https://www.novabbs.com/devel/article-flat.php?id=20115&group=comp.arch#20115

 copy link   Newsgroups: comp.arch
X-Received: by 2002:a05:620a:68c:: with SMTP id f12mr1882325qkh.363.1629903010308;
Wed, 25 Aug 2021 07:50:10 -0700 (PDT)
X-Received: by 2002:a4a:2c49:: with SMTP id o70mr34151085ooo.71.1629903010072;
Wed, 25 Aug 2021 07:50:10 -0700 (PDT)
Path: i2pn2.org!i2pn.org!news.niel.me!usenet.pasdenom.info!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail
Newsgroups: comp.arch
Date: Wed, 25 Aug 2021 07:50:09 -0700 (PDT)
In-Reply-To: <1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com>
Injection-Info: google-groups.googlegroups.com; posting-host=2001:56a:f39d:2c00:daf:819:7298:6b34;
posting-account=1nOeKQkAAABD2jxp4Pzmx9Hx5g9miO8y
NNTP-Posting-Host: 2001:56a:f39d:2c00:daf:819:7298:6b34
References: <1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com>
User-Agent: G2/1.0
MIME-Version: 1.0
Message-ID: <8837d585-222c-46fd-b23a-d775a93efcd4n@googlegroups.com>
Subject: Re: On diodes (answer to a poster at RWT.com)
From: jsav...@ecn.ab.ca (Quadibloc)
Injection-Date: Wed, 25 Aug 2021 14:50:10 +0000
Content-Type: text/plain; charset="UTF-8"
 by: Quadibloc - Wed, 25 Aug 2021 14:50 UTC

A diode is a PN junction, and so diodes can be put on any silicon chip
made by any standard bipolar process.
The issue that would prevent diode logic from being an alternative to
CMOS is not, therefore, one of the process being incompatible with
modern-day silicon foundries.
Instead, the problem is that a "1" level would now involve the continuous
flow of current, rather than just being a higher voltage, with no current
flow except when logic levels change. So the same heat issues that led
to CMOS replacing NMOS and PMOS prevent diode logic from being used.
No doubt there are other issues involved, since bipolar meant TTL, and
TTL replaced DTL for good reasons back in the day.

But back before there _were_ transistors, using diodes for logic as much
as possible, with only the occasional vacuum tube when a signal had to
be amplified or inverted, was indeed a very good idea.
Today, though, diodes aren't smaller than transistors by a large enough
margin.

John Savard

Re: On diodes (answer to a poster at RWT.com)

<5d28ceec-ec25-4e89-ab31-0b95d5723d31n@googlegroups.com>

 copy mid

https://www.novabbs.com/devel/article-flat.php?id=20116&group=comp.arch#20116

 copy link   Newsgroups: comp.arch
X-Received: by 2002:a37:b686:: with SMTP id g128mr31666456qkf.68.1629903477065;
Wed, 25 Aug 2021 07:57:57 -0700 (PDT)
X-Received: by 2002:a9d:1b5:: with SMTP id e50mr38257623ote.76.1629903476874;
Wed, 25 Aug 2021 07:57:56 -0700 (PDT)
Path: i2pn2.org!i2pn.org!paganini.bofh.team!usenet.pasdenom.info!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail
Newsgroups: comp.arch
Date: Wed, 25 Aug 2021 07:57:56 -0700 (PDT)
In-Reply-To: <8837d585-222c-46fd-b23a-d775a93efcd4n@googlegroups.com>
Injection-Info: google-groups.googlegroups.com; posting-host=144.64.185.162; posting-account=68D3awoAAABKe1mUbulBNmV4G3MrhsQ_
NNTP-Posting-Host: 144.64.185.162
References: <1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com> <8837d585-222c-46fd-b23a-d775a93efcd4n@googlegroups.com>
User-Agent: G2/1.0
MIME-Version: 1.0
Message-ID: <5d28ceec-ec25-4e89-ab31-0b95d5723d31n@googlegroups.com>
Subject: Re: On diodes (answer to a poster at RWT.com)
From: vasco.co...@gmail.com (Vasco Costa)
Injection-Date: Wed, 25 Aug 2021 14:57:57 +0000
Content-Type: text/plain; charset="UTF-8"
 by: Vasco Costa - Wed, 25 Aug 2021 14:57 UTC

On Wednesday, August 25, 2021 at 3:50:11 PM UTC+1, Quadibloc wrote:
> A diode is a PN junction, and so diodes can be put on any silicon chip
> made by any standard bipolar process.
> The issue that would prevent diode logic from being an alternative to
> CMOS is not, therefore, one of the process being incompatible with
> modern-day silicon foundries.
> Instead, the problem is that a "1" level would now involve the continuous
> flow of current, rather than just being a higher voltage, with no current
> flow except when logic levels change. So the same heat issues that led
> to CMOS replacing NMOS and PMOS prevent diode logic from being used.
> No doubt there are other issues involved, since bipolar meant TTL, and
> TTL replaced DTL for good reasons back in the day.
>
> But back before there _were_ transistors, using diodes for logic as much
> as possible, with only the occasional vacuum tube when a signal had to
> be amplified or inverted, was indeed a very good idea.
> Today, though, diodes aren't smaller than transistors by a large enough
> margin.

This is an interesting argument given the person at RWT.com claims diodes use less power draw.
What you are discussing basically states they can't store a high level without power draw.
In other words it can't act like the standard flip-flop in terms of power draw and is in fact worse.

If today's levels of idle power leakage continue to increase perhaps diodes might make sense again?

Are processors still designed on top of NAND and NOR gates or what? How much low level transistor analog design is still being done? Questions, questions.

Re: On diodes (answer to a poster at RWT.com)

<2021Aug25.173027@mips.complang.tuwien.ac.at>

 copy mid

https://www.novabbs.com/devel/article-flat.php?id=20117&group=comp.arch#20117

 copy link   Newsgroups: comp.arch
Path: i2pn2.org!i2pn.org!eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail
From: ant...@mips.complang.tuwien.ac.at (Anton Ertl)
Newsgroups: comp.arch
Subject: Re: On diodes (answer to a poster at RWT.com)
Date: Wed, 25 Aug 2021 15:30:27 GMT
Organization: Institut fuer Computersprachen, Technische Universitaet Wien
Lines: 14
Message-ID: <2021Aug25.173027@mips.complang.tuwien.ac.at>
References: <1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com> <8837d585-222c-46fd-b23a-d775a93efcd4n@googlegroups.com> <5d28ceec-ec25-4e89-ab31-0b95d5723d31n@googlegroups.com>
Injection-Info: reader02.eternal-september.org; posting-host="698bda361438bbb368b34d24c14a45d6";
logging-data="4977"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX181gMgswytDrZEG4XVDwG7K"
Cancel-Lock: sha1:UtUZAux3+/5PcXt3FEqyRlqwQK8=
X-newsreader: xrn 10.00-beta-3
 by: Anton Ertl - Wed, 25 Aug 2021 15:30 UTC

Vasco Costa <vasco.costa@gmail.com> writes:
>If today's levels of idle power leakage continue to increase perhaps diodes might make sense again?

Leakage power has been discussed as big future problem 20 years ago
(e.g., I wrote "in the future leakage will play a role as important as
switching power" in <2002May19.121444@a0.complang.tuwien.ac.at>), but
such predictions turned out not to be true. The circuit design people
found ways to avoid this problem. In particular, they seem to be very
aggressive on power gating. I guess there are other tricks.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

Re: On diodes (answer to a poster at RWT.com)

<1736b6a4-a8f3-4be2-b288-f25f215b72den@googlegroups.com>

 copy mid

https://www.novabbs.com/devel/article-flat.php?id=20118&group=comp.arch#20118

 copy link   Newsgroups: comp.arch
X-Received: by 2002:a37:bf47:: with SMTP id p68mr26889634qkf.202.1629907876016;
Wed, 25 Aug 2021 09:11:16 -0700 (PDT)
X-Received: by 2002:a05:6830:3482:: with SMTP id c2mr16015852otu.16.1629907875789;
Wed, 25 Aug 2021 09:11:15 -0700 (PDT)
Path: i2pn2.org!i2pn.org!paganini.bofh.team!usenet.pasdenom.info!usenet-fr.net!fdn.fr!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail
Newsgroups: comp.arch
Date: Wed, 25 Aug 2021 09:11:15 -0700 (PDT)
In-Reply-To: <5d28ceec-ec25-4e89-ab31-0b95d5723d31n@googlegroups.com>
Injection-Info: google-groups.googlegroups.com; posting-host=2001:56a:f39d:2c00:60aa:1a19:afc9:92b;
posting-account=1nOeKQkAAABD2jxp4Pzmx9Hx5g9miO8y
NNTP-Posting-Host: 2001:56a:f39d:2c00:60aa:1a19:afc9:92b
References: <1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com>
<8837d585-222c-46fd-b23a-d775a93efcd4n@googlegroups.com> <5d28ceec-ec25-4e89-ab31-0b95d5723d31n@googlegroups.com>
User-Agent: G2/1.0
MIME-Version: 1.0
Message-ID: <1736b6a4-a8f3-4be2-b288-f25f215b72den@googlegroups.com>
Subject: Re: On diodes (answer to a poster at RWT.com)
From: jsav...@ecn.ab.ca (Quadibloc)
Injection-Date: Wed, 25 Aug 2021 16:11:16 +0000
Content-Type: text/plain; charset="UTF-8"
 by: Quadibloc - Wed, 25 Aug 2021 16:11 UTC

On Wednesday, August 25, 2021 at 8:57:58 AM UTC-6, vasco...@gmail.com wrote:

> Are processors still designed on top of NAND and NOR gates or what?

Yes. Very much so. NAND and NOR gates are what you build from transistors in
CMOS.

Idle power leakage is a big issue limiting the performance of integrated
circuits. It's the main reason why as we have gone to even smaller processes,
the raw speed of microprocessors has stopped increasing. Switching from
transistors to diodes won't do a thing about it, since the leakage is from wires,
not from active components.

This is why there is much research on "low-k dielectrics". There is also research
on "high-k dielectrics" to make transistors work better, so we need insulators at
both ends of that scale.

It's certainly true that unlike a transistor, a diode doesn't need power to be'
supplied to it to run. But it's what the diode does in the context of a digital
circuit that matters.

John Savard

Re: On diodes (answer to a poster at RWT.com)

<81bca21d-8976-490b-acb9-78558d1bad3cn@googlegroups.com>

 copy mid

https://www.novabbs.com/devel/article-flat.php?id=20119&group=comp.arch#20119

 copy link   Newsgroups: comp.arch
X-Received: by 2002:a37:ab15:: with SMTP id u21mr32069409qke.439.1629908009421;
Wed, 25 Aug 2021 09:13:29 -0700 (PDT)
X-Received: by 2002:a4a:434d:: with SMTP id l13mr35253160ooj.83.1629908009168;
Wed, 25 Aug 2021 09:13:29 -0700 (PDT)
Path: i2pn2.org!i2pn.org!paganini.bofh.team!usenet.pasdenom.info!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail
Newsgroups: comp.arch
Date: Wed, 25 Aug 2021 09:13:28 -0700 (PDT)
In-Reply-To: <2021Aug25.173027@mips.complang.tuwien.ac.at>
Injection-Info: google-groups.googlegroups.com; posting-host=2001:56a:f39d:2c00:60aa:1a19:afc9:92b;
posting-account=1nOeKQkAAABD2jxp4Pzmx9Hx5g9miO8y
NNTP-Posting-Host: 2001:56a:f39d:2c00:60aa:1a19:afc9:92b
References: <1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com>
<8837d585-222c-46fd-b23a-d775a93efcd4n@googlegroups.com> <5d28ceec-ec25-4e89-ab31-0b95d5723d31n@googlegroups.com>
<2021Aug25.173027@mips.complang.tuwien.ac.at>
User-Agent: G2/1.0
MIME-Version: 1.0
Message-ID: <81bca21d-8976-490b-acb9-78558d1bad3cn@googlegroups.com>
Subject: Re: On diodes (answer to a poster at RWT.com)
From: jsav...@ecn.ab.ca (Quadibloc)
Injection-Date: Wed, 25 Aug 2021 16:13:29 +0000
Content-Type: text/plain; charset="UTF-8"
 by: Quadibloc - Wed, 25 Aug 2021 16:13 UTC

On Wednesday, August 25, 2021 at 9:37:31 AM UTC-6, Anton Ertl wrote:

> Leakage power has been discussed as big future problem 20 years ago
> (e.g., I wrote "in the future leakage will play a role as important as
> switching power" in <2002May1...@a0.complang.tuwien.ac.at>), but
> such predictions turned out not to be true.

And here I thought - thanks to Mitch Alsup, even - that leakage _is_ indeed
a problem. Not big enough to stop people from making microprocessors at
smaller sizes, no, but it's the main reason why they're still running at speeds
like 3.33 GHz instead of 10 GHz by now.

John Savard

Re: On diodes (answer to a poster at RWT.com)

<2021Aug25.184509@mips.complang.tuwien.ac.at>

 copy mid

https://www.novabbs.com/devel/article-flat.php?id=20120&group=comp.arch#20120

 copy link   Newsgroups: comp.arch
Path: i2pn2.org!i2pn.org!eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail
From: ant...@mips.complang.tuwien.ac.at (Anton Ertl)
Newsgroups: comp.arch
Subject: Re: On diodes (answer to a poster at RWT.com)
Date: Wed, 25 Aug 2021 16:45:09 GMT
Organization: Institut fuer Computersprachen, Technische Universitaet Wien
Lines: 37
Message-ID: <2021Aug25.184509@mips.complang.tuwien.ac.at>
References: <1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com> <8837d585-222c-46fd-b23a-d775a93efcd4n@googlegroups.com> <5d28ceec-ec25-4e89-ab31-0b95d5723d31n@googlegroups.com> <2021Aug25.173027@mips.complang.tuwien.ac.at> <81bca21d-8976-490b-acb9-78558d1bad3cn@googlegroups.com>
Injection-Info: reader02.eternal-september.org; posting-host="698bda361438bbb368b34d24c14a45d6";
logging-data="22560"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+WkczzEnoJcs10LBHMNGsv"
Cancel-Lock: sha1:N+/0nC4RNrNBlCUMByj6/aP2778=
X-newsreader: xrn 10.00-beta-3
 by: Anton Ertl - Wed, 25 Aug 2021 16:45 UTC

Quadibloc <jsavard@ecn.ab.ca> writes:
>And here I thought - thanks to Mitch Alsup, even - that leakage _is_ indeed
>a problem.

It is, but they seem to be able to keep it in check. E.g., a 2.8GHz
Prescott (90nm, 125M transistors) consumes 100W (according to
<https://en.wikipedia.org/wiki/Pentium_4>), and also a substantial
amount while idle. I have a Skylake (Core i5-6600K from 2016) here
that consumes 2W when all cores are idle, 20W when one core is loaded,
50W when all four cores are loaded (maybe some more with AVX). The
idle power consumption tells you how well Intel managed to deal with
leakage in 2016. The loaded power consumption shows that they also
managed to get that down (and if you look at reviews of recent Intel
CPUs, they use this to increase the clock speed through aggressive
frequency and voltage scaling.

>Not big enough to stop people from making microprocessors at
>smaller sizes, no, but it's the main reason why they're still running at speeds
>like 3.33 GHz instead of 10 GHz by now.

Why would clock-independent leakage power have that effect?

My understanding is that the way to higher clocks would have been to
have pipelines with many stages, each with a low number of gate delays
(e.g., 8 instead of 16 or more for current designs). E.g., make a
Pentium 4 with 54 pipeline stages rather than the 20 of
Willamette/Northwood or the 31 of Prescott/Cedar Mill. The Tejas and
Mitch Alsup's K9 went in that direction, but both were cancelled in
2005. Such designs would have increased transistors and thus leakage
power (somwhat linearly with the number of stages), but switching
power even more (both with the number of stages and with the clock
rate).

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

Re: On diodes (answer to a poster at RWT.com)

<c3e39fbb-6a68-4c28-b065-89ddbb1dc81cn@googlegroups.com>

 copy mid

https://www.novabbs.com/devel/article-flat.php?id=20121&group=comp.arch#20121

 copy link   Newsgroups: comp.arch
X-Received: by 2002:ad4:562a:: with SMTP id cb10mr2605743qvb.23.1629912505590;
Wed, 25 Aug 2021 10:28:25 -0700 (PDT)
X-Received: by 2002:a9d:6a4b:: with SMTP id h11mr39466312otn.5.1629912505353;
Wed, 25 Aug 2021 10:28:25 -0700 (PDT)
Path: i2pn2.org!i2pn.org!weretis.net!feeder8.news.weretis.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail
Newsgroups: comp.arch
Date: Wed, 25 Aug 2021 10:28:25 -0700 (PDT)
In-Reply-To: <81bca21d-8976-490b-acb9-78558d1bad3cn@googlegroups.com>
Injection-Info: google-groups.googlegroups.com; posting-host=104.59.204.55; posting-account=H_G_JQkAAADS6onOMb-dqvUozKse7mcM
NNTP-Posting-Host: 104.59.204.55
References: <1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com>
<8837d585-222c-46fd-b23a-d775a93efcd4n@googlegroups.com> <5d28ceec-ec25-4e89-ab31-0b95d5723d31n@googlegroups.com>
<2021Aug25.173027@mips.complang.tuwien.ac.at> <81bca21d-8976-490b-acb9-78558d1bad3cn@googlegroups.com>
User-Agent: G2/1.0
MIME-Version: 1.0
Message-ID: <c3e39fbb-6a68-4c28-b065-89ddbb1dc81cn@googlegroups.com>
Subject: Re: On diodes (answer to a poster at RWT.com)
From: MitchAl...@aol.com (MitchAlsup)
Injection-Date: Wed, 25 Aug 2021 17:28:25 +0000
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
 by: MitchAlsup - Wed, 25 Aug 2021 17:28 UTC

On Wednesday, August 25, 2021 at 11:13:30 AM UTC-5, Quadibloc wrote:
> On Wednesday, August 25, 2021 at 9:37:31 AM UTC-6, Anton Ertl wrote:
>
> > Leakage power has been discussed as big future problem 20 years ago
> > (e.g., I wrote "in the future leakage will play a role as important as
> > switching power" in <2002May1...@a0.complang.tuwien.ac.at>), but
> > such predictions turned out not to be true.
<
> And here I thought - thanks to Mitch Alsup, even - that leakage _is_ indeed
> a problem. Not big enough to stop people from making microprocessors at
> smaller sizes, no, but it's the main reason why they're still running at speeds
> like 3.33 GHz instead of 10 GHz by now.
<
Back in the Opteron days,
a) the clock was close to 50% of the power of the die
b) leakage was another 15%
c) so only 35% of the power was going to performing work.
<
d) heavy power gating and clever clock strategies save ½ of clock power
e) careful power management (like turning off FPU when integer code is running)
.....saves ½ of leakage and 10% on performing work
<
But the reason CPUs at stuck at 5 GHz is wires. As you shrink the process
transistors get faster (higher transconductance) but wires get slower from
a number of causes--3D capacitance stays relatively the same, but the wires
get more resistive from smaller cross section. At fast edge rates, skin effect
makes the wires even more resistive as current does not flow through the good
section of the wire, but only the skin which is made of barrier metals not the
copper core.
>
> John Savard

Re: On diodes (answer to a poster at RWT.com)

<1b8s0pxuwj.fsf@pfeifferfamily.net>

 copy mid

https://www.novabbs.com/devel/article-flat.php?id=20122&group=comp.arch#20122

 copy link   Newsgroups: comp.arch
Path: i2pn2.org!i2pn.org!aioe.org!eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail
From: pfeif...@cs.nmsu.edu (Joe Pfeiffer)
Newsgroups: comp.arch
Subject: Re: On diodes (answer to a poster at RWT.com)
Date: Wed, 25 Aug 2021 12:05:00 -0600
Organization: A noiseless patient Spider
Lines: 6
Message-ID: <1b8s0pxuwj.fsf@pfeifferfamily.net>
References: <1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com>
Mime-Version: 1.0
Content-Type: text/plain
Injection-Info: reader02.eternal-september.org; posting-host="b6d59e1b7cdd0e0cf0c4a8aa38317170";
logging-data="7852"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/vOF8lgzZpxFMpWMRIK7eH/oaO3CCUD3A="
User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/27.1 (gnu/linux)
Cancel-Lock: sha1:mYm0WMw0gcUaqHjZugEW7KQNqo0=
sha1:C+0kSLg6TWnEBavfLorYF/D9G4c=
 by: Joe Pfeiffer - Wed, 25 Aug 2021 18:05 UTC

Vasco Costa <vasco.costa@gmail.com> writes:

> In answer to a user's mention of "diode logic" the proof is in the pudding.

Is this a followup to a particular post in this newsgroup? Could you
either point to that post or wherever it did come from?

Re: On diodes (answer to a poster at RWT.com)

<5a68576c-6768-454b-90b8-4910870bd1e6n@googlegroups.com>

 copy mid

https://www.novabbs.com/devel/article-flat.php?id=20123&group=comp.arch#20123

 copy link   Newsgroups: comp.arch
X-Received: by 2002:a05:6214:20eb:: with SMTP id 11mr536980qvk.52.1629923297085;
Wed, 25 Aug 2021 13:28:17 -0700 (PDT)
X-Received: by 2002:a9d:5603:: with SMTP id e3mr259137oti.178.1629923296844;
Wed, 25 Aug 2021 13:28:16 -0700 (PDT)
Path: i2pn2.org!rocksolid2!news.neodome.net!news.ortolo.eu!fdn.fr!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail
Newsgroups: comp.arch
Date: Wed, 25 Aug 2021 13:28:16 -0700 (PDT)
In-Reply-To: <8837d585-222c-46fd-b23a-d775a93efcd4n@googlegroups.com>
Injection-Info: google-groups.googlegroups.com; posting-host=104.59.204.55; posting-account=H_G_JQkAAADS6onOMb-dqvUozKse7mcM
NNTP-Posting-Host: 104.59.204.55
References: <1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com> <8837d585-222c-46fd-b23a-d775a93efcd4n@googlegroups.com>
User-Agent: G2/1.0
MIME-Version: 1.0
Message-ID: <5a68576c-6768-454b-90b8-4910870bd1e6n@googlegroups.com>
Subject: Re: On diodes (answer to a poster at RWT.com)
From: MitchAl...@aol.com (MitchAlsup)
Injection-Date: Wed, 25 Aug 2021 20:28:17 +0000
Content-Type: text/plain; charset="UTF-8"
 by: MitchAlsup - Wed, 25 Aug 2021 20:28 UTC

On Wednesday, August 25, 2021 at 9:50:11 AM UTC-5, Quadibloc wrote:
> A diode is a PN junction, and so diodes can be put on any silicon chip
> made by any standard bipolar process.
<
agreed
<
> The issue that would prevent diode logic from being an alternative to
> CMOS is not, therefore, one of the process being incompatible with
> modern-day silicon foundries.
<
You are aware that back in the days we used wells to constrain transistors
that the sources and drains were (W E R E) diodes into the wells ??? Or
how do you think the wells were kept at proper voltages ?
<
> Instead, the problem is that a "1" level would now involve the continuous
> flow of current, rather than just being a higher voltage, with no current
> flow except when logic levels change. So the same heat issues that led
> to CMOS replacing NMOS and PMOS prevent diode logic from being used.
> No doubt there are other issues involved, since bipolar meant TTL, and
> TTL replaced DTL for good reasons back in the day.
<
The real problem with diodes is that you need resistors. CMOS processes
are great at making transistors wires, tolerably good at making capacitors,
not very good at making inductors, and horrible at making resistors.
<
Diode logic needs resistors, and often 3 power supplies.
<
And you still need the transistors to supply gain from stage to stage.
<
Yet you can make gates directly from transistors without needing the
resistors and voltage levels diodes need to make logic. Diodes lost
because the overall economics favored transistors.
>
> But back before there _were_ transistors, using diodes for logic as much
> as possible, with only the occasional vacuum tube when a signal had to
> be amplified or inverted, was indeed a very good idea.
> Today, though, diodes aren't smaller than transistors by a large enough
> margin.
>
> John Savard

Re: On diodes (answer to a poster at RWT.com)

<sg7fs7$474$1@dont-email.me>

 copy mid

https://www.novabbs.com/devel/article-flat.php?id=20131&group=comp.arch#20131

 copy link   Newsgroups: comp.arch
Path: i2pn2.org!i2pn.org!eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail
From: david.br...@hesbynett.no (David Brown)
Newsgroups: comp.arch
Subject: Re: On diodes (answer to a poster at RWT.com)
Date: Thu, 26 Aug 2021 09:29:10 +0200
Organization: A noiseless patient Spider
Lines: 63
Message-ID: <sg7fs7$474$1@dont-email.me>
References: <1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com>
<8837d585-222c-46fd-b23a-d775a93efcd4n@googlegroups.com>
<5d28ceec-ec25-4e89-ab31-0b95d5723d31n@googlegroups.com>
<2021Aug25.173027@mips.complang.tuwien.ac.at>
<81bca21d-8976-490b-acb9-78558d1bad3cn@googlegroups.com>
<2021Aug25.184509@mips.complang.tuwien.ac.at>
Mime-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Transfer-Encoding: 7bit
Injection-Date: Thu, 26 Aug 2021 07:29:11 -0000 (UTC)
Injection-Info: reader02.eternal-september.org; posting-host="88c9bacb65ea2036705abae614c98530";
logging-data="4324"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/Kl+29I/K5JzF+BTk3bd/ZiAiMTGTr5vM="
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101
Thunderbird/78.11.0
Cancel-Lock: sha1:pA42XYsuCZB9uW9U8XP77UngAd0=
In-Reply-To: <2021Aug25.184509@mips.complang.tuwien.ac.at>
Content-Language: en-GB
 by: David Brown - Thu, 26 Aug 2021 07:29 UTC

On 25/08/2021 18:45, Anton Ertl wrote:
> Quadibloc <jsavard@ecn.ab.ca> writes:
>> And here I thought - thanks to Mitch Alsup, even - that leakage _is_ indeed
>> a problem.
>
> It is, but they seem to be able to keep it in check. E.g., a 2.8GHz
> Prescott (90nm, 125M transistors) consumes 100W (according to
> <https://en.wikipedia.org/wiki/Pentium_4>), and also a substantial
> amount while idle. I have a Skylake (Core i5-6600K from 2016) here
> that consumes 2W when all cores are idle, 20W when one core is loaded,
> 50W when all four cores are loaded (maybe some more with AVX). The
> idle power consumption tells you how well Intel managed to deal with
> leakage in 2016. The loaded power consumption shows that they also
> managed to get that down (and if you look at reviews of recent Intel
> CPUs, they use this to increase the clock speed through aggressive
> frequency and voltage scaling.
>
>> Not big enough to stop people from making microprocessors at
>> smaller sizes, no, but it's the main reason why they're still running at speeds
>> like 3.33 GHz instead of 10 GHz by now.
>
> Why would clock-independent leakage power have that effect?

My understanding (and I don't know anything like as much about this
stuff as many of the others here) is that increasing the speed of
transistors requires either reducing the gate capacitance, or increasing
the gate current. Increasing the gate current means increasing the
dynamic power needed, while reducing the gate capacitance gives you more
leakage.

I don't know the figures for the balances between dynamic power, leakage
currents and switching speeds, but there will be a point where
increasing switching speeds without impractically high switching
currents would lead to unworkably high leakage current. Dynamic power
gating helps a lot, but you can't switch off /everything/ even when idle.

>
> My understanding is that the way to higher clocks would have been to
> have pipelines with many stages, each with a low number of gate delays
> (e.g., 8 instead of 16 or more for current designs). E.g., make a
> Pentium 4 with 54 pipeline stages rather than the 20 of
> Willamette/Northwood or the 31 of Prescott/Cedar Mill. The Tejas and
> Mitch Alsup's K9 went in that direction, but both were cancelled in
> 2005. Such designs would have increased transistors and thus leakage
> power (somwhat linearly with the number of stages), but switching
> power even more (both with the number of stages and with the clock
> rate).
>

Longer pipelines can give you higher clocks for the same transistor
switching speed. But there are diminishing returns. As pipelines get
longer, you need more complicated logic to keep track - more
out-of-order execution, more super-scaler, more speculative execution,
or your performance goes down, especially on mispredicted branches. And
all of that costs more leaking transistors that are powered all the
time, thus your total idle current is a problem again. The Pentium 4
showed what you get when you use long pipelines to target bragging
rights of higher clocks speeds rather than actual real-world
performance. Intel saw it was a dead end, and dropped it when they went
back to the Pentium Pro architecture as the starting point for the
following generation ("core", IIRC).

Re: On diodes (answer to a poster at RWT.com)

<331b6e35-d98b-475d-ac23-659c0bdd25e2n@googlegroups.com>

 copy mid

https://www.novabbs.com/devel/article-flat.php?id=20132&group=comp.arch#20132

 copy link   Newsgroups: comp.arch
X-Received: by 2002:ac8:7d07:: with SMTP id g7mr2161231qtb.238.1629966311825;
Thu, 26 Aug 2021 01:25:11 -0700 (PDT)
X-Received: by 2002:a54:470c:: with SMTP id k12mr1575972oik.78.1629966311594;
Thu, 26 Aug 2021 01:25:11 -0700 (PDT)
Path: i2pn2.org!i2pn.org!weretis.net!feeder6.news.weretis.net!news.snarked.org!border2.nntp.dca1.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail
Newsgroups: comp.arch
Date: Thu, 26 Aug 2021 01:25:11 -0700 (PDT)
In-Reply-To: <c3e39fbb-6a68-4c28-b065-89ddbb1dc81cn@googlegroups.com>
Injection-Info: google-groups.googlegroups.com; posting-host=199.203.251.52; posting-account=ow8VOgoAAAAfiGNvoH__Y4ADRwQF1hZW
NNTP-Posting-Host: 199.203.251.52
References: <1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com>
<8837d585-222c-46fd-b23a-d775a93efcd4n@googlegroups.com> <5d28ceec-ec25-4e89-ab31-0b95d5723d31n@googlegroups.com>
<2021Aug25.173027@mips.complang.tuwien.ac.at> <81bca21d-8976-490b-acb9-78558d1bad3cn@googlegroups.com>
<c3e39fbb-6a68-4c28-b065-89ddbb1dc81cn@googlegroups.com>
User-Agent: G2/1.0
MIME-Version: 1.0
Message-ID: <331b6e35-d98b-475d-ac23-659c0bdd25e2n@googlegroups.com>
Subject: Re: On diodes (answer to a poster at RWT.com)
From: already5...@yahoo.com (Michael S)
Injection-Date: Thu, 26 Aug 2021 08:25:11 +0000
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
Lines: 56
 by: Michael S - Thu, 26 Aug 2021 08:25 UTC

On Wednesday, August 25, 2021 at 8:28:26 PM UTC+3, MitchAlsup wrote:
> On Wednesday, August 25, 2021 at 11:13:30 AM UTC-5, Quadibloc wrote:
> > On Wednesday, August 25, 2021 at 9:37:31 AM UTC-6, Anton Ertl wrote:
> >
> > > Leakage power has been discussed as big future problem 20 years ago
> > > (e.g., I wrote "in the future leakage will play a role as important as
> > > switching power" in <2002May1...@a0.complang.tuwien.ac.at>), but
> > > such predictions turned out not to be true.
> <
> > And here I thought - thanks to Mitch Alsup, even - that leakage _is_ indeed
> > a problem. Not big enough to stop people from making microprocessors at
> > smaller sizes, no, but it's the main reason why they're still running at speeds
> > like 3.33 GHz instead of 10 GHz by now.
> <
> Back in the Opteron days,
> a) the clock was close to 50% of the power of the die
> b) leakage was another 15%
> c) so only 35% of the power was going to performing work.
> <
> d) heavy power gating and clever clock strategies save ½ of clock power
> e) careful power management (like turning off FPU when integer code is running)
> ....saves ½ of leakage and 10% on performing work
> <
> But the reason CPUs at stuck at 5 GHz is wires.

Power density plays no role?

> As you shrink the process
> transistors get faster (higher transconductance) but wires get slower from
> a number of causes--3D capacitance stays relatively the same, but the wires
> get more resistive from smaller cross section. At fast edge rates, skin effect
> makes the wires even more resistive as current does not flow through the good
> section of the wire, but only the skin which is made of barrier metals not the
> copper core.

Also, absolute dimensions of finer layers of wires are approaching mean free path of electrons in copper.
Which means that bulk conductivity no longer applies even for DC.
It was speculated as one of the reasons for Intel's switch to Cobalt on two metal inner layers of their 10nm process.
I don't know if it was the main reason or fear of electromigration was more significant.

> >
> > John Savard

Re: On diodes (answer to a poster at RWT.com)

<Peh*baEsy@news.chiark.greenend.org.uk>

 copy mid

https://www.novabbs.com/devel/article-flat.php?id=20133&group=comp.arch#20133

 copy link   Newsgroups: comp.arch
Path: i2pn2.org!i2pn.org!paganini.bofh.team!newsfeed.xs3.de!nntp-feed.chiark.greenend.org.uk!ewrotcd!.POSTED!not-for-mail
From: theom+n...@chiark.greenend.org.uk (Theo Markettos)
Newsgroups: comp.arch
Subject: Re: On diodes (answer to a poster at RWT.com)
Date: 26 Aug 2021 12:50:29 +0100 (BST)
Organization: University of Cambridge, England
Lines: 38
Message-ID: <Peh*baEsy@news.chiark.greenend.org.uk>
References: <1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com> <8837d585-222c-46fd-b23a-d775a93efcd4n@googlegroups.com> <5d28ceec-ec25-4e89-ab31-0b95d5723d31n@googlegroups.com> <1736b6a4-a8f3-4be2-b288-f25f215b72den@googlegroups.com>
NNTP-Posting-Host: chiark.greenend.org.uk
X-Trace: chiark.greenend.org.uk 1629978631 27099 212.13.197.229 (26 Aug 2021 11:50:31 GMT)
X-Complaints-To: abuse@chiark.greenend.org.uk
NNTP-Posting-Date: Thu, 26 Aug 2021 11:50:31 +0000 (UTC)
User-Agent: tin/1.8.3-20070201 ("Scotasay") (UNIX) (Linux/3.16.0-11-amd64 (x86_64))
Originator: theom@chiark.greenend.org.uk ([212.13.197.229])
 by: Theo Markettos - Thu, 26 Aug 2021 11:50 UTC

Quadibloc <jsavard@ecn.ab.ca> wrote:
> On Wednesday, August 25, 2021 at 8:57:58 AM UTC-6, vasco...@gmail.com wrote:
>
> > Are processors still designed on top of NAND and NOR gates or what?
>
> Yes. Very much so. NAND and NOR gates are what you build from transistors in
> CMOS.

Yes and no. You /can/ build NAND and NOR gates from transistors, and they
do get used a lot, but for the last few decades the building blocks have
been 'standard cells'. You can have NAND and NOR standard cells, but often
the ones used are more complex functions like adders and SRAM cells, which
are optimised at a transistor level rather than being constructed out of
NAND and NOR gates. It's up to your synthesis tool to pick the standard
cells to implement whatever you asked it for, and generally it will try to
pick the more complex cells if they can provide a power/performance/area
improvement.

The people who design the standard cells are the ones who are still doing
transistor level design, but they do it in full awareness of the fabrication
process they're targeting.
> Idle power leakage is a big issue limiting the performance of integrated
> circuits. It's the main reason why as we have gone to even smaller processes,
> the raw speed of microprocessors has stopped increasing. Switching from
> transistors to diodes won't do a thing about it, since the leakage is from wires,
> not from active components.

There's the issue of leakage, but that's different from steady state idle
currents. If you switched to diodes you would have enormous idle currents
through all the pullup resistors, on top of what leaks through the
substrate. CMOS eliminates the pullup resistors and so massively reduces
the idle power - in essence because the resistance is so much more (but
non-infinite) than the pullup resistor.

Diodes might have been a competitor for NMOS, but not CMOS.

Theo

Re: On diodes (answer to a poster at RWT.com)

<2ed38fcd-d738-4a2d-a307-54faa8292199n@googlegroups.com>

 copy mid

https://www.novabbs.com/devel/article-flat.php?id=20135&group=comp.arch#20135

 copy link   Newsgroups: comp.arch
X-Received: by 2002:a0c:cb8f:: with SMTP id p15mr5323340qvk.2.1630002668493;
Thu, 26 Aug 2021 11:31:08 -0700 (PDT)
X-Received: by 2002:a9d:1469:: with SMTP id h96mr4331111oth.82.1630002668211;
Thu, 26 Aug 2021 11:31:08 -0700 (PDT)
Path: i2pn2.org!i2pn.org!aioe.org!news.uzoreto.com!newsfeed.xs4all.nl!newsfeed8.news.xs4all.nl!news-out.netnews.com!news.alt.net!fdc3.netnews.com!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail
Newsgroups: comp.arch
Date: Thu, 26 Aug 2021 11:31:08 -0700 (PDT)
In-Reply-To: <sg7fs7$474$1@dont-email.me>
Injection-Info: google-groups.googlegroups.com; posting-host=104.59.204.55; posting-account=H_G_JQkAAADS6onOMb-dqvUozKse7mcM
NNTP-Posting-Host: 104.59.204.55
References: <1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com>
<8837d585-222c-46fd-b23a-d775a93efcd4n@googlegroups.com> <5d28ceec-ec25-4e89-ab31-0b95d5723d31n@googlegroups.com>
<2021Aug25.173027@mips.complang.tuwien.ac.at> <81bca21d-8976-490b-acb9-78558d1bad3cn@googlegroups.com>
<2021Aug25.184509@mips.complang.tuwien.ac.at> <sg7fs7$474$1@dont-email.me>
User-Agent: G2/1.0
MIME-Version: 1.0
Message-ID: <2ed38fcd-d738-4a2d-a307-54faa8292199n@googlegroups.com>
Subject: Re: On diodes (answer to a poster at RWT.com)
From: MitchAl...@aol.com (MitchAlsup)
Injection-Date: Thu, 26 Aug 2021 18:31:08 +0000
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
X-Received-Bytes: 6575
 by: MitchAlsup - Thu, 26 Aug 2021 18:31 UTC

On Thursday, August 26, 2021 at 2:29:13 AM UTC-5, David Brown wrote:
> On 25/08/2021 18:45, Anton Ertl wrote:
> > Quadibloc <jsa...@ecn.ab.ca> writes:
> >> And here I thought - thanks to Mitch Alsup, even - that leakage _is_ indeed
> >> a problem.
> >
> > It is, but they seem to be able to keep it in check. E.g., a 2.8GHz
> > Prescott (90nm, 125M transistors) consumes 100W (according to
> > <https://en.wikipedia.org/wiki/Pentium_4>), and also a substantial
> > amount while idle. I have a Skylake (Core i5-6600K from 2016) here
> > that consumes 2W when all cores are idle, 20W when one core is loaded,
> > 50W when all four cores are loaded (maybe some more with AVX). The
> > idle power consumption tells you how well Intel managed to deal with
> > leakage in 2016. The loaded power consumption shows that they also
> > managed to get that down (and if you look at reviews of recent Intel
> > CPUs, they use this to increase the clock speed through aggressive
> > frequency and voltage scaling.
> >
> >> Not big enough to stop people from making microprocessors at
> >> smaller sizes, no, but it's the main reason why they're still running at speeds
> >> like 3.33 GHz instead of 10 GHz by now.
> >
> > Why would clock-independent leakage power have that effect?
> My understanding (and I don't know anything like as much about this
> stuff as many of the others here) is that increasing the speed of
> transistors requires either reducing the gate capacitance, or increasing
> the gate current. Increasing the gate current means increasing the
> dynamic power needed, while reducing the gate capacitance gives you more
> leakage.
<
Back at 14nm FinFET, there was only a dozen atoms of oxide between gate
and channel. This is where all the work on high K dielectrics come in.
High K dielectric enabled keeping 12 atoms between channel and gate
but make the electric field over the channel stronger. Stronger field,
greater transconductance.
<
They ran out of room to make the oxide thinner.
<
Conversely, over in the metal stack, they look for low K dielectrics to
reduce the wire to wire capacitance.
>
> I don't know the figures for the balances between dynamic power, leakage
> currents and switching speeds, but there will be a point where
> increasing switching speeds without impractically high switching
> currents would lead to unworkably high leakage current. Dynamic power
> gating helps a lot, but you can't switch off /everything/ even when idle.
<
As voltage rises across a FET source to drain, there is a point at which
the channel cannot be turned completely off, just below this point
leakage is femtoAmps, above this point there is a sharp rise in leakage.
<
One can make a transistor have greater transconductance by lowering the
gate voltage at which the transistor turns on (Vtn). Simultaneoulsy this
enables leakage at lower source-drain voltages. So you can choose::
fast and hot, or slow and cool. and not a whole lot in between.
> >
> > My understanding is that the way to higher clocks would have been to
> > have pipelines with many stages, each with a low number of gate delays
> > (e.g., 8 instead of 16 or more for current designs). E.g., make a
> > Pentium 4 with 54 pipeline stages rather than the 20 of
> > Willamette/Northwood or the 31 of Prescott/Cedar Mill. The Tejas and
> > Mitch Alsup's K9 went in that direction, but both were cancelled in
> > 2005. Such designs would have increased transistors and thus leakage
> > power (somwhat linearly with the number of stages), but switching
> > power even more (both with the number of stages and with the clock
> > rate).
> >
> Longer pipelines can give you higher clocks for the same transistor
> switching speed. But there are diminishing returns. As pipelines get
> longer, you need more complicated logic to keep track - more
> out-of-order execution, more super-scaler, more speculative execution,
> or your performance goes down, especially on mispredicted branches. And
> all of that costs more leaking transistors that are powered all the
> time, thus your total idle current is a problem again. The Pentium 4
> showed what you get when you use long pipelines to target bragging
> rights of higher clocks speeds rather than actual real-world
> performance. Intel saw it was a dead end, and dropped it when they went
> back to the Pentium Pro architecture as the starting point for the
> following generation ("core", IIRC).
<
Mitch's second law: If you have a k stage pipeline running at frequency f
and double the number of stages, you will end up with k×2.5 actual stages.
<
If you started with a 16-gates per cycle (and 5-gates for clock jitter skew)
you new pipeline will run at::
<
(16+5)/(8+5) = 1.6×f
<
2.5× the effort, 1.6× the benefit.
<
This assumes the branch predictor makes 1/2.5 as many branch mispredictions..

Re: On diodes (answer to a poster at RWT.com)

<a70175e1-88a5-40e6-9261-ac6d76328c18n@googlegroups.com>

 copy mid

https://www.novabbs.com/devel/article-flat.php?id=20138&group=comp.arch#20138

 copy link   Newsgroups: comp.arch
X-Received: by 2002:a05:622a:10c:: with SMTP id u12mr5019143qtw.303.1630007763940;
Thu, 26 Aug 2021 12:56:03 -0700 (PDT)
X-Received: by 2002:a9d:694c:: with SMTP id p12mr4624190oto.182.1630007763621;
Thu, 26 Aug 2021 12:56:03 -0700 (PDT)
Path: i2pn2.org!i2pn.org!paganini.bofh.team!usenet.pasdenom.info!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail
Newsgroups: comp.arch
Date: Thu, 26 Aug 2021 12:56:03 -0700 (PDT)
In-Reply-To: <sg7fs7$474$1@dont-email.me>
Injection-Info: google-groups.googlegroups.com; posting-host=2001:56a:f39d:2c00:718b:60d4:7b41:87bb;
posting-account=1nOeKQkAAABD2jxp4Pzmx9Hx5g9miO8y
NNTP-Posting-Host: 2001:56a:f39d:2c00:718b:60d4:7b41:87bb
References: <1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com>
<8837d585-222c-46fd-b23a-d775a93efcd4n@googlegroups.com> <5d28ceec-ec25-4e89-ab31-0b95d5723d31n@googlegroups.com>
<2021Aug25.173027@mips.complang.tuwien.ac.at> <81bca21d-8976-490b-acb9-78558d1bad3cn@googlegroups.com>
<2021Aug25.184509@mips.complang.tuwien.ac.at> <sg7fs7$474$1@dont-email.me>
User-Agent: G2/1.0
MIME-Version: 1.0
Message-ID: <a70175e1-88a5-40e6-9261-ac6d76328c18n@googlegroups.com>
Subject: Re: On diodes (answer to a poster at RWT.com)
From: jsav...@ecn.ab.ca (Quadibloc)
Injection-Date: Thu, 26 Aug 2021 19:56:03 +0000
Content-Type: text/plain; charset="UTF-8"
 by: Quadibloc - Thu, 26 Aug 2021 19:56 UTC

On Thursday, August 26, 2021 at 1:29:13 AM UTC-6, David Brown wrote:
> The Pentium 4
> showed what you get when you use long pipelines to target bragging
> rights of higher clocks speeds rather than actual real-world
> performance.

That's what I _thought_ Intel was up to at the time.

However, since then I learned better. The higher clock speeds did
actually reflect higher performance... in terms of _throughput_,
the same way that having more cores means more performance.

While a chip with twice the cores and the same clock speed can't
perform a single thread any faster, it can perform twice the threads.
A chip with a higher clock speed but more clocks per instructions is
also able to perform additional threads... during the in-between
clocks.

And, unlike a multi-core chip, sometimes the additional parallel workload
can belong to the same thread, thanks to out-of-order execution.

John Savard

Re: On diodes (answer to a poster at RWT.com)

<34c1108d-e1b6-4b69-8f0c-24fa8809a396n@googlegroups.com>

 copy mid

https://www.novabbs.com/devel/article-flat.php?id=20139&group=comp.arch#20139

 copy link   Newsgroups: comp.arch
X-Received: by 2002:ad4:58ea:: with SMTP id di10mr6115911qvb.60.1630007938166;
Thu, 26 Aug 2021 12:58:58 -0700 (PDT)
X-Received: by 2002:a9d:d35:: with SMTP id 50mr4658304oti.22.1630007937900;
Thu, 26 Aug 2021 12:58:57 -0700 (PDT)
Path: i2pn2.org!i2pn.org!news.niel.me!usenet.pasdenom.info!usenet-fr.net!proxad.net!feeder1-2.proxad.net!209.85.160.216.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail
Newsgroups: comp.arch
Date: Thu, 26 Aug 2021 12:58:57 -0700 (PDT)
In-Reply-To: <Peh*baEsy@news.chiark.greenend.org.uk>
Injection-Info: google-groups.googlegroups.com; posting-host=2001:56a:f39d:2c00:718b:60d4:7b41:87bb;
posting-account=1nOeKQkAAABD2jxp4Pzmx9Hx5g9miO8y
NNTP-Posting-Host: 2001:56a:f39d:2c00:718b:60d4:7b41:87bb
References: <1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com>
<8837d585-222c-46fd-b23a-d775a93efcd4n@googlegroups.com> <5d28ceec-ec25-4e89-ab31-0b95d5723d31n@googlegroups.com>
<1736b6a4-a8f3-4be2-b288-f25f215b72den@googlegroups.com> <Peh*baEsy@news.chiark.greenend.org.uk>
User-Agent: G2/1.0
MIME-Version: 1.0
Message-ID: <34c1108d-e1b6-4b69-8f0c-24fa8809a396n@googlegroups.com>
Subject: Re: On diodes (answer to a poster at RWT.com)
From: jsav...@ecn.ab.ca (Quadibloc)
Injection-Date: Thu, 26 Aug 2021 19:58:58 +0000
Content-Type: text/plain; charset="UTF-8"
 by: Quadibloc - Thu, 26 Aug 2021 19:58 UTC

On Thursday, August 26, 2021 at 5:50:35 AM UTC-6, Theo Markettos wrote:
> Quadibloc <jsa...@ecn.ab.ca> wrote:
> > On Wednesday, August 25, 2021 at 8:57:58 AM UTC-6, vasco...@gmail.com wrote:

> > > Are processors still designed on top of NAND and NOR gates or what?

> > Yes. Very much so. NAND and NOR gates are what you build from transistors in
> > CMOS.

> Yes and no. You /can/ build NAND and NOR gates from transistors, and they
> do get used a lot, but for the last few decades the building blocks have
> been 'standard cells'.

True, _except_ for highly-optimized designs like the microprocessors from
AMD and Intel. But since standard cells are themselves built from NAND
and NOR gates, I thought that to be an irrelevant technicality.

John Savard

Re: On diodes (answer to a poster at RWT.com)

<sga1uu$hbi$2@newsreader4.netcologne.de>

 copy mid

https://www.novabbs.com/devel/article-flat.php?id=20140&group=comp.arch#20140

 copy link   Newsgroups: comp.arch
Path: i2pn2.org!i2pn.org!weretis.net!feeder8.news.weretis.net!newsreader4.netcologne.de!news.netcologne.de!.POSTED.2001-4dd7-22d2-0-7285-c2ff-fe6c-992d.ipv6dyn.netcologne.de!not-for-mail
From: tkoe...@netcologne.de (Thomas Koenig)
Newsgroups: comp.arch
Subject: Re: On diodes (answer to a poster at RWT.com)
Date: Fri, 27 Aug 2021 06:50:06 -0000 (UTC)
Organization: news.netcologne.de
Distribution: world
Message-ID: <sga1uu$hbi$2@newsreader4.netcologne.de>
References: <1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com>
<8837d585-222c-46fd-b23a-d775a93efcd4n@googlegroups.com>
<5d28ceec-ec25-4e89-ab31-0b95d5723d31n@googlegroups.com>
<1736b6a4-a8f3-4be2-b288-f25f215b72den@googlegroups.com>
<Peh*baEsy@news.chiark.greenend.org.uk>
<34c1108d-e1b6-4b69-8f0c-24fa8809a396n@googlegroups.com>
Injection-Date: Fri, 27 Aug 2021 06:50:06 -0000 (UTC)
Injection-Info: newsreader4.netcologne.de; posting-host="2001-4dd7-22d2-0-7285-c2ff-fe6c-992d.ipv6dyn.netcologne.de:2001:4dd7:22d2:0:7285:c2ff:fe6c:992d";
logging-data="17778"; mail-complaints-to="abuse@netcologne.de"
User-Agent: slrn/1.0.3 (Linux)
 by: Thomas Koenig - Fri, 27 Aug 2021 06:50 UTC

Quadibloc <jsavard@ecn.ab.ca> schrieb:
> On Thursday, August 26, 2021 at 5:50:35 AM UTC-6, Theo Markettos wrote:
>> Quadibloc <jsa...@ecn.ab.ca> wrote:
>> > On Wednesday, August 25, 2021 at 8:57:58 AM UTC-6, vasco...@gmail.com wrote:
>
>> > > Are processors still designed on top of NAND and NOR gates or what?
>
>> > Yes. Very much so. NAND and NOR gates are what you build from transistors in
>> > CMOS.
>
>> Yes and no. You /can/ build NAND and NOR gates from transistors, and they
>> do get used a lot, but for the last few decades the building blocks have
>> been 'standard cells'.
>
> True, _except_ for highly-optimized designs like the microprocessors from
> AMD and Intel. But since standard cells are themselves built from NAND
> and NOR gates,

Certainly not, we are out of the age of the Apollo guidance computer.

If you look at, for example,
https://sus.ziti.uni-heidelberg.de/Lehre/WS1617_DST/DST_Fischer_06_Einfache_Bloecke_FF.pptx.pdf
on slide 22 (in German) you will find a 24-transistor inverting full adder
made up of 24 transistors. Page 18 will show you the implementation
based on AOI logic.

If you implemented the AOI logic with NAND and NOR gates, you would use
many more transistors.

>I thought that to be an irrelevant technicality.

Not really.

Re: On diodes (answer to a poster at RWT.com)

<sga1v8$8o1$1@dont-email.me>

 copy mid

https://www.novabbs.com/devel/article-flat.php?id=20141&group=comp.arch#20141

 copy link   Newsgroups: comp.arch
Path: i2pn2.org!i2pn.org!eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail
From: david.br...@hesbynett.no (David Brown)
Newsgroups: comp.arch
Subject: Re: On diodes (answer to a poster at RWT.com)
Date: Fri, 27 Aug 2021 08:50:16 +0200
Organization: A noiseless patient Spider
Lines: 43
Message-ID: <sga1v8$8o1$1@dont-email.me>
References: <1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com>
<8837d585-222c-46fd-b23a-d775a93efcd4n@googlegroups.com>
<5d28ceec-ec25-4e89-ab31-0b95d5723d31n@googlegroups.com>
<2021Aug25.173027@mips.complang.tuwien.ac.at>
<81bca21d-8976-490b-acb9-78558d1bad3cn@googlegroups.com>
<2021Aug25.184509@mips.complang.tuwien.ac.at> <sg7fs7$474$1@dont-email.me>
<a70175e1-88a5-40e6-9261-ac6d76328c18n@googlegroups.com>
Mime-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Transfer-Encoding: 7bit
Injection-Date: Fri, 27 Aug 2021 06:50:16 -0000 (UTC)
Injection-Info: reader02.eternal-september.org; posting-host="fed6096691498295289ba6a5bd23a888";
logging-data="8961"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1/s3fA2C5a+7tk+AN8HT9KrKBvoZ16OHKw="
User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101
Thunderbird/78.11.0
Cancel-Lock: sha1:17G3ETN1nj4bDvEto8RG1wzlJpA=
In-Reply-To: <a70175e1-88a5-40e6-9261-ac6d76328c18n@googlegroups.com>
Content-Language: en-GB
 by: David Brown - Fri, 27 Aug 2021 06:50 UTC

On 26/08/2021 21:56, Quadibloc wrote:
> On Thursday, August 26, 2021 at 1:29:13 AM UTC-6, David Brown wrote:
>> The Pentium 4
>> showed what you get when you use long pipelines to target bragging
>> rights of higher clocks speeds rather than actual real-world
>> performance.
>
> That's what I _thought_ Intel was up to at the time.
>
> However, since then I learned better. The higher clock speeds did
> actually reflect higher performance... in terms of _throughput_,
> the same way that having more cores means more performance.
>

Certainly there can be a trade-off between greater throughput, and lower
latency (or, if you prefer, lower costs for branches and changes of
flow). There are some applications for which throughput rules, but
those are more common for server applications and big systems, than
desktops and user interaction.

> While a chip with twice the cores and the same clock speed can't
> perform a single thread any faster, it can perform twice the threads.
> A chip with a higher clock speed but more clocks per instructions is
> also able to perform additional threads... during the in-between
> clocks.
>

I suppose that is possible in theory, but it was not possible on
practice on the P4. It works well on bigger designs with more serious
SMT, such as Power and SPARC SMT cores which are designed to keep
instructions flowing through the core despite interruptions in the flow
of any one thread. But those are designed for applications where you
have dozens or hundreds of threads running all the time - not desktops
where much of the time you have no more than a few percent processor
usage on average, and you rarely have many threads active with useful
work but you want top speed from those few threads.

> And, unlike a multi-core chip, sometimes the additional parallel workload
> can belong to the same thread, thanks to out-of-order execution.
>
> John Savard
>

Re: On diodes (answer to a poster at RWT.com)

<sga64c$ji2$1@newsreader4.netcologne.de>

 copy mid

https://www.novabbs.com/devel/article-flat.php?id=20142&group=comp.arch#20142

 copy link   Newsgroups: comp.arch
Path: i2pn2.org!i2pn.org!paganini.bofh.team!news.dns-netz.com!news.freedyn.net!newsreader4.netcologne.de!news.netcologne.de!.POSTED.2001-4dd7-22d2-0-7285-c2ff-fe6c-992d.ipv6dyn.netcologne.de!not-for-mail
From: tkoe...@netcologne.de (Thomas Koenig)
Newsgroups: comp.arch
Subject: Re: On diodes (answer to a poster at RWT.com)
Date: Fri, 27 Aug 2021 08:01:16 -0000 (UTC)
Organization: news.netcologne.de
Distribution: world
Message-ID: <sga64c$ji2$1@newsreader4.netcologne.de>
References: <1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com>
<8837d585-222c-46fd-b23a-d775a93efcd4n@googlegroups.com>
<5d28ceec-ec25-4e89-ab31-0b95d5723d31n@googlegroups.com>
<2021Aug25.173027@mips.complang.tuwien.ac.at>
<81bca21d-8976-490b-acb9-78558d1bad3cn@googlegroups.com>
<2021Aug25.184509@mips.complang.tuwien.ac.at> <sg7fs7$474$1@dont-email.me>
<2ed38fcd-d738-4a2d-a307-54faa8292199n@googlegroups.com>
Injection-Date: Fri, 27 Aug 2021 08:01:16 -0000 (UTC)
Injection-Info: newsreader4.netcologne.de; posting-host="2001-4dd7-22d2-0-7285-c2ff-fe6c-992d.ipv6dyn.netcologne.de:2001:4dd7:22d2:0:7285:c2ff:fe6c:992d";
logging-data="20034"; mail-complaints-to="abuse@netcologne.de"
User-Agent: slrn/1.0.3 (Linux)
 by: Thomas Koenig - Fri, 27 Aug 2021 08:01 UTC

MitchAlsup <MitchAlsup@aol.com> schrieb:
><
> Back at 14nm FinFET, there was only a dozen atoms of oxide between gate
> and channel. This is where all the work on high K dielectrics come in.
> High K dielectric enabled keeping 12 atoms between channel and gate
> but make the electric field over the channel stronger. Stronger field,
> greater transconductance.
><
> They ran out of room to make the oxide thinner.

In other words: Atoms don't scale.

Re: On diodes (answer to a poster at RWT.com)

<iorn4oFsj98U1@mid.individual.net>

 copy mid

https://www.novabbs.com/devel/article-flat.php?id=20144&group=comp.arch#20144

 copy link   Newsgroups: comp.arch
Path: i2pn2.org!i2pn.org!news.swapon.de!fu-berlin.de!uni-berlin.de!individual.net!not-for-mail
From: niklas.h...@tidorum.invalid (Niklas Holsti)
Newsgroups: comp.arch
Subject: Re: On diodes (answer to a poster at RWT.com)
Date: Fri, 27 Aug 2021 11:47:19 +0300
Organization: Tidorum Ltd
Lines: 43
Message-ID: <iorn4oFsj98U1@mid.individual.net>
References: <1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com>
<8837d585-222c-46fd-b23a-d775a93efcd4n@googlegroups.com>
<5d28ceec-ec25-4e89-ab31-0b95d5723d31n@googlegroups.com>
<1736b6a4-a8f3-4be2-b288-f25f215b72den@googlegroups.com>
<Peh*baEsy@news.chiark.greenend.org.uk>
<34c1108d-e1b6-4b69-8f0c-24fa8809a396n@googlegroups.com>
<sga1uu$hbi$2@newsreader4.netcologne.de>
Mime-Version: 1.0
Content-Type: text/plain; charset=utf-8; format=flowed
Content-Transfer-Encoding: 7bit
X-Trace: individual.net j+JUmy+ptf67vkU1gx9smAFa8RWoYc8WcnrcaAXPSSiMP2udxb
Cancel-Lock: sha1:1U8jhFSz5f2Y7mMsqaDBjWkvWh4=
User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.14; rv:78.0)
Gecko/20100101 Thunderbird/78.13.0
In-Reply-To: <sga1uu$hbi$2@newsreader4.netcologne.de>
Content-Language: en-US
 by: Niklas Holsti - Fri, 27 Aug 2021 08:47 UTC

On 2021-08-27 9:50, Thomas Koenig wrote:
> Quadibloc <jsavard@ecn.ab.ca> schrieb:
>> On Thursday, August 26, 2021 at 5:50:35 AM UTC-6, Theo Markettos wrote:
>>> Quadibloc <jsa...@ecn.ab.ca> wrote:
>>>> On Wednesday, August 25, 2021 at 8:57:58 AM UTC-6, vasco...@gmail.com wrote:
>>
>>>>> Are processors still designed on top of NAND and NOR gates or what?
>>
>>>> Yes. Very much so. NAND and NOR gates are what you build from transistors in
>>>> CMOS.
>>
>>> Yes and no. You /can/ build NAND and NOR gates from transistors, and they
>>> do get used a lot, but for the last few decades the building blocks have
>>> been 'standard cells'.
>>
>> True, _except_ for highly-optimized designs like the microprocessors from
>> AMD and Intel. But since standard cells are themselves built from NAND
>> and NOR gates,
>
> Certainly not, we are out of the age of the Apollo guidance computer.
>
> If you look at, for example,
> https://sus.ziti.uni-heidelberg.de/Lehre/WS1617_DST/DST_Fischer_06_Einfache_Bloecke_FF.pptx.pdf
> on slide 22 (in German) you will find a 24-transistor inverting full adder
> made up of 24 transistors. Page 18 will show you the implementation
> based on AOI logic.
>
> If you implemented the AOI logic with NAND and NOR gates, you would use
> many more transistors.

Hm. Slide 18, showing the AOI logic, also says "10+2" transistors for
the carry, and "14+2" transistors for the sum. That would be a total of
28 transistors, not so many more than 24. But perhaps I misunderstand
slide 18, and its transistor counts do not reflect an implementation
built from gates?

On the other hand, the Wikipedia descriptions of gates show that a
typical (N)AND or (N)OR gate can be built from 2-3 transistors, except
in CMOS where more are required (but the referenced slides make a point
of "no CMOS!"). With that number of transistors per gate, the transistor
counts on slide 18 seem right for the implementation built from gates,
with not many more transistors than for the optimized circuit on slide 22.

Re: On diodes (answer to a poster at RWT.com)

<2021Aug27.094329@mips.complang.tuwien.ac.at>

 copy mid

https://www.novabbs.com/devel/article-flat.php?id=20145&group=comp.arch#20145

 copy link   Newsgroups: comp.arch
Path: i2pn2.org!i2pn.org!eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail
From: ant...@mips.complang.tuwien.ac.at (Anton Ertl)
Newsgroups: comp.arch
Subject: Re: On diodes (answer to a poster at RWT.com)
Date: Fri, 27 Aug 2021 07:43:29 GMT
Organization: Institut fuer Computersprachen, Technische Universitaet Wien
Lines: 135
Message-ID: <2021Aug27.094329@mips.complang.tuwien.ac.at>
References: <1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com> <8837d585-222c-46fd-b23a-d775a93efcd4n@googlegroups.com> <5d28ceec-ec25-4e89-ab31-0b95d5723d31n@googlegroups.com> <2021Aug25.173027@mips.complang.tuwien.ac.at> <81bca21d-8976-490b-acb9-78558d1bad3cn@googlegroups.com> <2021Aug25.184509@mips.complang.tuwien.ac.at> <sg7fs7$474$1@dont-email.me>
Injection-Info: reader02.eternal-september.org; posting-host="c7186496f997e847cab40f2f27332733";
logging-data="13765"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+QusJ3QTukgaBy4FauZ5Oi"
Cancel-Lock: sha1:X4OxWYRr4QOwO6vD7wFw1LBr9iM=
X-newsreader: xrn 10.00-beta-3
 by: Anton Ertl - Fri, 27 Aug 2021 07:43 UTC

David Brown <david.brown@hesbynett.no> writes:
>On 25/08/2021 18:45, Anton Ertl wrote:
>> Quadibloc <jsavard@ecn.ab.ca> writes:
>>> And here I thought - thanks to Mitch Alsup, even - that leakage _is_ indeed
>>> a problem.
>>
>> It is, but they seem to be able to keep it in check. E.g., a 2.8GHz
>> Prescott (90nm, 125M transistors) consumes 100W (according to
>> <https://en.wikipedia.org/wiki/Pentium_4>), and also a substantial
>> amount while idle. I have a Skylake (Core i5-6600K from 2016) here
>> that consumes 2W when all cores are idle, 20W when one core is loaded,
>> 50W when all four cores are loaded (maybe some more with AVX). The
>> idle power consumption tells you how well Intel managed to deal with
>> leakage in 2016. The loaded power consumption shows that they also
>> managed to get that down (and if you look at reviews of recent Intel
>> CPUs, they use this to increase the clock speed through aggressive
>> frequency and voltage scaling.
>>
>>> Not big enough to stop people from making microprocessors at
>>> smaller sizes, no, but it's the main reason why they're still running at speeds
>>> like 3.33 GHz instead of 10 GHz by now.
>>
>> Why would clock-independent leakage power have that effect?
>
>My understanding (and I don't know anything like as much about this
>stuff as many of the others here) is that increasing the speed of
>transistors requires either reducing the gate capacitance, or increasing
>the gate current. Increasing the gate current means increasing the
>dynamic power needed, while reducing the gate capacitance gives you more
>leakage.

Actually in the Willamette (180nm) they used domino logic (a dynamic
technique) to get fast-switching circuits (they had 4GHz on their
16-bit ALU core (with 2 staggered 16-bit ALUs) on the fastest
Willamette). In smaller processes transistor speed became less
important (wire speed and power consumption became more
important) and circuit designers went back to static CMOS (or that's
what I heard).

In any case, they used the fastest transistors possible in the process
of the time in the critical paths of processors like Willamette, so
increasing gate current was not possible (and reducing gate
capacitance was not possible, either). And they knew what to expect
in the next process generations, and that was that wire time
would become dominant and would slow process-based clock increases.
Yet Intel planned for 7GHz for Tejas and 10GHz by 2011, and they
planned to do it with even deeper pipelining.

They must also have known the power (and power density) consequences,
so my speculation is that they bet on a promising cooling technology,
and when those promises evaporated, they cancelled Tejas (and AMD
cancelled K9).

>I don't know the figures for the balances between dynamic power, leakage
>currents and switching speeds, but there will be a point where
>increasing switching speeds without impractically high switching
>currents would lead to unworkably high leakage current. Dynamic power
>gating helps a lot, but you can't switch off /everything/ even when idle.

Actually current high-performance CPUs switch off almost everything
when idle, as evidenced by the very low power consumption when idle.
The issue is more that you cannot switch off everything when loaded,
so if leakage becomes dominant, you will see a lot of it when the CPU
is not idle.

What we can see from actual processors is that Skylake takes a few
hundred cycles to power up the upper 128 bits of the SIMD FUs. Intel
CPUs also differentiate between light and heavy SIMD instructions for
the purposes of determining the AVX offset (which lowers the clock to
reduce power consumption), and looking at
<https://lemire.me/blog/2018/08/25/avx-512-throttling-heavy-instructions-are-maybe-not-so-dangerous/>,
you need a pretty high rate of heavy instructions on recent Intel CPUs
to notice a clock lowering. From that I infer that either they have
another, very fast, power-gating mechanism that allows power-gating
per instruction, or switching power is still dominant under load. And
if it is the fast power-gating mechanism, are the practical
consequences any different from the case where switching speed is
dominant?

>> My understanding is that the way to higher clocks would have been to
>> have pipelines with many stages, each with a low number of gate delays
>> (e.g., 8 instead of 16 or more for current designs). E.g., make a
>> Pentium 4 with 54 pipeline stages rather than the 20 of
>> Willamette/Northwood or the 31 of Prescott/Cedar Mill. The Tejas and
>> Mitch Alsup's K9 went in that direction, but both were cancelled in
>> 2005. Such designs would have increased transistors and thus leakage
>> power (somwhat linearly with the number of stages), but switching
>> power even more (both with the number of stages and with the clock
>> rate).
>>
>
>Longer pipelines can give you higher clocks for the same transistor
>switching speed. But there are diminishing returns. As pipelines get
>longer, you need more complicated logic to keep track - more
>out-of-order execution, more super-scaler, more speculative execution,
>or your performance goes down, especially on mispredicted branches.

Yes, and Sprange and Carmean [sprangle&carmean02] from Intel have
written a nice paper on these tradeoffs, and found that, for the
Pentium 4 microarchitecture, 52 pipeline stages is optimal (or would
have been optimal if power had not become an issue). That was with
the Pentium 4 branch predictor. With current branch predictors, I
guess that the would-be optimum would be even higher.

@InProceedings{sprangle&carmean02,
author = {Eric Sprangle and Doug Carmean},
title = {Increasing Processor Performance by Implementing
Deeper Pipelines},
crossref = {isca02},
pages = {25--34},
url = {http://www.cs.cmu.edu/afs/cs/academic/class/15740-f03/public/doc/discussions/uniprocessors/technology/deep-pipelines-isca02.pdf},
annote = {This paper starts with the Williamette (Pentium~4)
pipeline and discusses and evaluates changes to the
pipeline length. In particular, it gives numbers on
how lengthening various latencies would affect IPC;
on a per-cycle basis the ALU latency is most
important, then L1 cache, then L2 cache, then branch
misprediction; however, the total effect of
lengthening the pipeline to double the clock rate
gives the reverse order (because branch
misprediction gains more cycles than the other
latencies). The paper reports 52 pipeline stages
with 1.96 times the original clock rate as optimal
for the Pentium~4 microarchitecture, resulting in a
reduction of 1.45 of core time and an overall
speedup of about 1.29 (including waiting for
memory). Various other topics are discussed, such as
nonlinear effects when introducing bypasses, and
varying cache sizes. Recommended reading.}
}

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

Re: On diodes (answer to a poster at RWT.com)

<Reh*ftJsy@news.chiark.greenend.org.uk>

 copy mid

https://www.novabbs.com/devel/article-flat.php?id=20147&group=comp.arch#20147

 copy link   Newsgroups: comp.arch
Path: i2pn2.org!i2pn.org!paganini.bofh.team!newsfeed.xs3.de!nntp-feed.chiark.greenend.org.uk!ewrotcd!.POSTED!not-for-mail
From: theom+n...@chiark.greenend.org.uk (Theo Markettos)
Newsgroups: comp.arch
Subject: Re: On diodes (answer to a poster at RWT.com)
Date: 27 Aug 2021 12:57:11 +0100 (BST)
Organization: University of Cambridge, England
Lines: 23
Message-ID: <Reh*ftJsy@news.chiark.greenend.org.uk>
References: <1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com> <8837d585-222c-46fd-b23a-d775a93efcd4n@googlegroups.com> <5d28ceec-ec25-4e89-ab31-0b95d5723d31n@googlegroups.com> <1736b6a4-a8f3-4be2-b288-f25f215b72den@googlegroups.com> <Peh*baEsy@news.chiark.greenend.org.uk> <34c1108d-e1b6-4b69-8f0c-24fa8809a396n@googlegroups.com> <sga1uu$hbi$2@newsreader4.netcologne.de> <iorn4oFsj98U1@mid.individual.net>
NNTP-Posting-Host: chiark.greenend.org.uk
X-Trace: chiark.greenend.org.uk 1630065433 17604 212.13.197.229 (27 Aug 2021 11:57:13 GMT)
X-Complaints-To: abuse@chiark.greenend.org.uk
NNTP-Posting-Date: Fri, 27 Aug 2021 11:57:13 +0000 (UTC)
User-Agent: tin/1.8.3-20070201 ("Scotasay") (UNIX) (Linux/3.16.0-11-amd64 (x86_64))
Originator: theom@chiark.greenend.org.uk ([212.13.197.229])
 by: Theo Markettos - Fri, 27 Aug 2021 11:57 UTC

Niklas Holsti <niklas.holsti@tidorum.invalid> wrote:
> On 2021-08-27 9:50, Thomas Koenig wrote:
> > If you look at, for example,
> > https://sus.ziti.uni-heidelberg.de/Lehre/WS1617_DST/DST_Fischer_06_Einfache_Bloecke_FF.pptx.pdf
> > on slide 22 (in German) you will find a 24-transistor inverting full adder
> > made up of 24 transistors. Page 18 will show you the implementation
> > based on AOI logic.
>
> On the other hand, the Wikipedia descriptions of gates show that a
> typical (N)AND or (N)OR gate can be built from 2-3 transistors, except
> in CMOS where more are required (but the referenced slides make a point
> of "no CMOS!"). With that number of transistors per gate, the transistor
> counts on slide 18 seem right for the implementation built from gates,
> with not many more transistors than for the optimized circuit on slide 22.

Can anyone explain what the slides mean by 'kein CMOS' and
'NICHT-CMOS-Gatter'? The diagrams look like CMOS to me - there's no
pullup/down resistors, nor is there precharge logic.

Are they trying to say that designing with NMOS and PMOS transistors is 'not
CMOS' because they aren't using them in N/P pairs?

Theo

Re: On diodes (answer to a poster at RWT.com)

<2021Aug27.154454@mips.complang.tuwien.ac.at>

 copy mid

https://www.novabbs.com/devel/article-flat.php?id=20148&group=comp.arch#20148

 copy link   Newsgroups: comp.arch
Path: i2pn2.org!i2pn.org!eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail
From: ant...@mips.complang.tuwien.ac.at (Anton Ertl)
Newsgroups: comp.arch
Subject: Re: On diodes (answer to a poster at RWT.com)
Date: Fri, 27 Aug 2021 13:44:54 GMT
Organization: Institut fuer Computersprachen, Technische Universitaet Wien
Lines: 31
Message-ID: <2021Aug27.154454@mips.complang.tuwien.ac.at>
References: <1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com> <8837d585-222c-46fd-b23a-d775a93efcd4n@googlegroups.com> <5d28ceec-ec25-4e89-ab31-0b95d5723d31n@googlegroups.com> <1736b6a4-a8f3-4be2-b288-f25f215b72den@googlegroups.com> <Peh*baEsy@news.chiark.greenend.org.uk> <34c1108d-e1b6-4b69-8f0c-24fa8809a396n@googlegroups.com> <sga1uu$hbi$2@newsreader4.netcologne.de> <iorn4oFsj98U1@mid.individual.net> <Reh*ftJsy@news.chiark.greenend.org.uk>
Injection-Info: reader02.eternal-september.org; posting-host="c7186496f997e847cab40f2f27332733";
logging-data="8082"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX1+fWFa9dOUEGIQw8Tou2nrw"
Cancel-Lock: sha1:kF2fMPKDf83dVKxiDnStCrzyIek=
X-newsreader: xrn 10.00-beta-3
 by: Anton Ertl - Fri, 27 Aug 2021 13:44 UTC

Theo Markettos <theom+news@chiark.greenend.org.uk> writes:
>Niklas Holsti <niklas.holsti@tidorum.invalid> wrote:
>> On 2021-08-27 9:50, Thomas Koenig wrote:
>> > If you look at, for example,
>> > https://sus.ziti.uni-heidelberg.de/Lehre/WS1617_DST/DST_Fischer_06_Einfache_Bloecke_FF.pptx.pdf
>> > on slide 22 (in German) you will find a 24-transistor inverting full adder
>> > made up of 24 transistors. Page 18 will show you the implementation
>> > based on AOI logic.
>>
>> On the other hand, the Wikipedia descriptions of gates show that a
>> typical (N)AND or (N)OR gate can be built from 2-3 transistors, except
>> in CMOS where more are required (but the referenced slides make a point
>> of "no CMOS!"). With that number of transistors per gate, the transistor
>> counts on slide 18 seem right for the implementation built from gates,
>> with not many more transistors than for the optimized circuit on slide 22.
>
>Can anyone explain what the slides mean by 'kein CMOS' and
>'NICHT-CMOS-Gatter'? The diagrams look like CMOS to me - there's no
>pullup/down resistors, nor is there precharge logic.
>
>Are they trying to say that designing with NMOS and PMOS transistors is 'not
>CMOS' because they aren't using them in N/P pairs?

My guess is: In ordinary CMOS, you have a pair of transistors in
series on one side (P or N) and in parallel on the complementary side,
and the non-CMOS circuits don't satisfy that.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

Re: On diodes (answer to a poster at RWT.com)

<2021Aug27.155339@mips.complang.tuwien.ac.at>

 copy mid

https://www.novabbs.com/devel/article-flat.php?id=20149&group=comp.arch#20149

 copy link   Newsgroups: comp.arch
Path: i2pn2.org!i2pn.org!eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail
From: ant...@mips.complang.tuwien.ac.at (Anton Ertl)
Newsgroups: comp.arch
Subject: Re: On diodes (answer to a poster at RWT.com)
Date: Fri, 27 Aug 2021 13:53:39 GMT
Organization: Institut fuer Computersprachen, Technische Universitaet Wien
Lines: 49
Message-ID: <2021Aug27.155339@mips.complang.tuwien.ac.at>
References: <1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com> <8837d585-222c-46fd-b23a-d775a93efcd4n@googlegroups.com> <5d28ceec-ec25-4e89-ab31-0b95d5723d31n@googlegroups.com> <1736b6a4-a8f3-4be2-b288-f25f215b72den@googlegroups.com> <Peh*baEsy@news.chiark.greenend.org.uk> <34c1108d-e1b6-4b69-8f0c-24fa8809a396n@googlegroups.com> <sga1uu$hbi$2@newsreader4.netcologne.de> <iorn4oFsj98U1@mid.individual.net>
Injection-Info: reader02.eternal-september.org; posting-host="c7186496f997e847cab40f2f27332733";
logging-data="24504"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX18qejgOie/Jeh1qcJUAB3Ss"
Cancel-Lock: sha1:E6Hh6S1eQrgW83bnDhYfAQWD3Vk=
X-newsreader: xrn 10.00-beta-3
 by: Anton Ertl - Fri, 27 Aug 2021 13:53 UTC

Niklas Holsti <niklas.holsti@tidorum.invalid> writes:
>On 2021-08-27 9:50, Thomas Koenig wrote:
>> If you look at, for example,
>> https://sus.ziti.uni-heidelberg.de/Lehre/WS1617_DST/DST_Fischer_06_Einfache_Bloecke_FF.pptx.pdf
>> on slide 22 (in German) you will find a 24-transistor inverting full adder
>> made up of 24 transistors. Page 18 will show you the implementation
>> based on AOI logic.
>>
>> If you implemented the AOI logic with NAND and NOR gates, you would use
>> many more transistors.
>
>
>Hm. Slide 18, showing the AOI logic, also says "10+2" transistors for
>the carry, and "14+2" transistors for the sum. That would be a total of
>28 transistors, not so many more than 24. But perhaps I misunderstand
>slide 18, and its transistor counts do not reflect an implementation
>built from gates?

It says "gemischtes Gatter" (mixed gate) on slide 18, whatever that
means. If I count 4 transistors for every 2-input gate, 2 for every
1-input gate, and 6 for every 3-input gate, the result is 18
transistors for the C_out part and 22 for the S part, totalling 40.
Or 36 if you accept inverted results, like the optimized circuit does.
And that's actually optimisitic, because most of the gates are AND and
OR-gates, so if you do it naively, you have to insert 6 inverters,
bringing the total to 52 transistors (48 with inverted results).

So the difference between naive and optimized is a factor of 2 at the
transistor level for this example. If you go to a lower level
(e.g. slide 9) there is additional optimiztion opportunity.

>On the other hand, the Wikipedia descriptions of gates show that a
>typical (N)AND or (N)OR gate can be built from 2-3 transistors, except
>in CMOS where more are required (but the referenced slides make a point
>of "no CMOS!").

But if you look at slide 21, you see that the corresponding CMOS
circuit also only has 10 transistors. The reason for the
transformation to the non-CMOS 10-transistor circuit is to avoid
having 3 PMOS transistors in series (stack height=3). Not sure why
that is a problem for the C_out-computing circuit, but not for the
S-computing part of the circuit shown on slide 22. It's not the
propagation delay from C_in to C_out, because the 3 stacked PMOS
transistors in the C_out circuit only have A and B as inputs.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

Re: On diodes (answer to a poster at RWT.com)

<633a381a-d2d3-4604-b448-2b87f4bb0c08n@googlegroups.com>

 copy mid

https://www.novabbs.com/devel/article-flat.php?id=20150&group=comp.arch#20150

 copy link   Newsgroups: comp.arch
X-Received: by 2002:a05:620a:1aa6:: with SMTP id bl38mr9816103qkb.36.1630078829754;
Fri, 27 Aug 2021 08:40:29 -0700 (PDT)
X-Received: by 2002:aca:5f09:: with SMTP id t9mr6967319oib.157.1630078829448;
Fri, 27 Aug 2021 08:40:29 -0700 (PDT)
Path: i2pn2.org!i2pn.org!aioe.org!feeder1.feed.usenet.farm!feed.usenet.farm!news-out.netnews.com!news.alt.net!fdc3.netnews.com!peer01.ams1!peer.ams1.xlned.com!news.xlned.com!peer02.iad!feed-me.highwinds-media.com!news.highwinds-media.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail
Newsgroups: comp.arch
Date: Fri, 27 Aug 2021 08:40:29 -0700 (PDT)
In-Reply-To: <sga1uu$hbi$2@newsreader4.netcologne.de>
Injection-Info: google-groups.googlegroups.com; posting-host=104.59.204.55; posting-account=H_G_JQkAAADS6onOMb-dqvUozKse7mcM
NNTP-Posting-Host: 104.59.204.55
References: <1f6c5073-311a-43aa-96bc-f310a1a48830n@googlegroups.com>
<8837d585-222c-46fd-b23a-d775a93efcd4n@googlegroups.com> <5d28ceec-ec25-4e89-ab31-0b95d5723d31n@googlegroups.com>
<1736b6a4-a8f3-4be2-b288-f25f215b72den@googlegroups.com> <Peh*baEsy@news.chiark.greenend.org.uk>
<34c1108d-e1b6-4b69-8f0c-24fa8809a396n@googlegroups.com> <sga1uu$hbi$2@newsreader4.netcologne.de>
User-Agent: G2/1.0
MIME-Version: 1.0
Message-ID: <633a381a-d2d3-4604-b448-2b87f4bb0c08n@googlegroups.com>
Subject: Re: On diodes (answer to a poster at RWT.com)
From: MitchAl...@aol.com (MitchAlsup)
Injection-Date: Fri, 27 Aug 2021 15:40:29 +0000
Content-Type: text/plain; charset="UTF-8"
X-Received-Bytes: 3042
 by: MitchAlsup - Fri, 27 Aug 2021 15:40 UTC

On Friday, August 27, 2021 at 1:50:09 AM UTC-5, Thomas Koenig wrote:
> Quadibloc <jsa...@ecn.ab.ca> schrieb:
> > On Thursday, August 26, 2021 at 5:50:35 AM UTC-6, Theo Markettos wrote:
> >> Quadibloc <jsa...@ecn.ab.ca> wrote:
> >> > On Wednesday, August 25, 2021 at 8:57:58 AM UTC-6, vasco...@gmail.com wrote:
> >
> >> > > Are processors still designed on top of NAND and NOR gates or what?
> >
> >> > Yes. Very much so. NAND and NOR gates are what you build from transistors in
> >> > CMOS.
> >
> >> Yes and no. You /can/ build NAND and NOR gates from transistors, and they
> >> do get used a lot, but for the last few decades the building blocks have
> >> been 'standard cells'.
> >
> > True, _except_ for highly-optimized designs like the microprocessors from
> > AMD and Intel. But since standard cells are themselves built from NAND
> > and NOR gates,
> Certainly not, we are out of the age of the Apollo guidance computer.
>
> If you look at, for example,
> https://sus.ziti.uni-heidelberg.de/Lehre/WS1617_DST/DST_Fischer_06_Einfache_Bloecke_FF.pptx.pdf
> on slide 22 (in German) you will find a 24-transistor inverting full adder
> made up of 24 transistors. Page 18 will show you the implementation
> based on AOI logic.
<
What you find on page 22 is a (3-2)-compressor (A.K.A. Full adder) with 2 gates of delay.
<
But I do like the professors down in the transistors way of showing circuitry.
>
> If you implemented the AOI logic with NAND and NOR gates, you would use
> many more transistors.
> >I thought that to be an irrelevant technicality.
> Not really.

Pages:12
server_pubkey.txt

rocksolid light 0.9.7
clearnet tor