On Friday, August 27, 2021 at 9:21:08 AM UTC-5, Anton Ertl wrote:
> Niklas Holsti <niklas...@tidorum.invalid> writes:
> >On 2021-08-27 9:50, Thomas Koenig wrote:
> >> If you look at, for example,
> >> https://sus.ziti.uni-heidelberg.de/Lehre/WS1617_DST/DST_Fischer_06_Einfache_Bloecke_FF.pptx.pdf
> >> on slide 22 (in German) you will find a 24-transistor inverting full adder
> >> made up of 24 transistors. Page 18 will show you the implementation
> >> based on AOI logic.
> >>
> >> If you implemented the AOI logic with NAND and NOR gates, you would use
> >> many more transistors.
> >
> >
> >Hm. Slide 18, showing the AOI logic, also says "10+2" transistors for
> >the carry, and "14+2" transistors for the sum. That would be a total of
> >28 transistors, not so many more than 24. But perhaps I misunderstand
> >slide 18, and its transistor counts do not reflect an implementation
> >built from gates?
> It says "gemischtes Gatter" (mixed gate) on slide 18, whatever that
> means. If I count 4 transistors for every 2-input gate, 2 for every
> 1-input gate, and 6 for every 3-input gate, the result is 18
> transistors for the C_out part and 22 for the S part, totalling 40.
> Or 36 if you accept inverted results, like the optimized circuit does.
> And that's actually optimisitic, because most of the gates are AND and
> OR-gates, so if you do it naively, you have to insert 6 inverters,
> bringing the total to 52 transistors (48 with inverted results).
>
> So the difference between naive and optimized is a factor of 2 at the
> transistor level for this example. If you go to a lower level
> (e.g. slide 9) there is additional optimiztion opportunity.
> >On the other hand, the Wikipedia descriptions of gates show that a
> >typical (N)AND or (N)OR gate can be built from 2-3 transistors, except
> >in CMOS where more are required (but the referenced slides make a point
> >of "no CMOS!").
<
> But if you look at slide 21, you see that the corresponding CMOS
> circuit also only has 10 transistors. The reason for the
> transformation to the non-CMOS 10-transistor circuit is to avoid
> having 3 PMOS transistors in series (stack height=3). Not sure why
> that is a problem for the C_out-computing circuit, but not for the
> S-computing part of the circuit shown on slide 22. It's not the
> propagation delay from C_in to C_out, because the 3 stacked PMOS
> transistors in the C_out circuit only have A and B as inputs.
<
Back in the days we were allowed to use T-Gates, we, by and large,
allowed 3-P-channels to be between Vdd and signal out and 4-N-
channels. This has to do with the body effect of P versus N, and
the higher threshold voltage of P versus N. FinFETs have essentially
gotten rid of the body effect and P-channels are much more like
N-channels in those technologies.
<
> - anton
> --
> 'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
> Mitch Alsup, <c17fcd89-f024-40e7...@googlegroups.com>

Anton Ertl <anton@mips.complang.tuwien.ac.at> schrieb:

> It says "gemischtes Gatter" (mixed gate) on slide 18, whatever that
> means.

I think it means the or-and-or-invert logic that is shown.

[...]

> But if you look at slide 21, you see that the corresponding CMOS
> circuit also only has 10 transistors. The reason for the
> transformation to the non-CMOS 10-transistor circuit is to avoid
> having 3 PMOS transistors in series (stack height=3). Not sure why
> that is a problem for the C_out-computing circuit, but not for the
> S-computing part of the circuit shown on slide 22. It's not the
> propagation delay from C_in to C_out, because the 3 stacked PMOS
> transistors in the C_out circuit only have A and B as inputs.

It's three P transistors in series for the inverted C_out signal
as oppposed to two in the optimized version. Carry delay is
critical for any sort of adder.

I'm not quite sure I understand why it is labeled "Not CMOS",
though. Granted, the circuits do not follow the usual rule of
"parallel on one side, serial on the other", but is that
actually required for calling a circuit to be called CMOS,
or isn't it possible to deviate from that as long as the
signal logic is the same for both polarities?

Thomas Koenig <tkoenig@netcologne.de> writes:
>Anton Ertl <anton@mips.complang.tuwien.ac.at> schrieb:
>
>> It says "gemischtes Gatter" (mixed gate) on slide 18, whatever that
>> means.
>
>I think it means the or-and-or-invert logic that is shown.

My guess is that it means one (mixed) gate for the whole
C_out-generating part rather than 4 or 5 pure gates. Note also the
occurence on slide 21.

>> But if you look at slide 21, you see that the corresponding CMOS
>> circuit also only has 10 transistors. The reason for the
>> transformation to the non-CMOS 10-transistor circuit is to avoid
>> having 3 PMOS transistors in series (stack height=3). Not sure why
>> that is a problem for the C_out-computing circuit, but not for the
>> S-computing part of the circuit shown on slide 22. It's not the
>> propagation delay from C_in to C_out, because the 3 stacked PMOS
>> transistors in the C_out circuit only have A and B as inputs.
>
>It's three P transistors in series for the inverted C_out signal
>as oppposed to two in the optimized version. Carry delay is
>critical for any sort of adder.

From carry-in to carry-out, yes. For the A and B inputs, less so.
It's interesting that in the S part the series of three PMOS
transistors also includes C_in. However, !S also depends on !C_out,
so when C_in comes in later than A and B, the path including C_out may
be slower than the third PMOS transistor in series.

>I'm not quite sure I understand why it is labeled "Not CMOS",
>though. Granted, the circuits do not follow the usual rule of
>"parallel on one side, serial on the other", but is that
>actually required for calling a circuit to be called CMOS,

<https://en.wikipedia.org/wiki/CMOS#Duality> suggests this.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

On Friday, August 27, 2021 at 11:45:22 AM UTC-5, Thomas Koenig wrote:
> Anton Ertl <an...@mips.complang.tuwien.ac.at> schrieb:
> > It says "gemischtes Gatter" (mixed gate) on slide 18, whatever that
> > means.
> I think it means the or-and-or-invert logic that is shown.
>
> [...]
> > But if you look at slide 21, you see that the corresponding CMOS
> > circuit also only has 10 transistors. The reason for the
> > transformation to the non-CMOS 10-transistor circuit is to avoid
> > having 3 PMOS transistors in series (stack height=3). Not sure why
> > that is a problem for the C_out-computing circuit, but not for the
> > S-computing part of the circuit shown on slide 22. It's not the
> > propagation delay from C_in to C_out, because the 3 stacked PMOS
> > transistors in the C_out circuit only have A and B as inputs.
> It's three P transistors in series for the inverted C_out signal
> as oppposed to two in the optimized version. Carry delay is
> critical for any sort of adder.
>
> I'm not quite sure I understand why it is labeled "Not CMOS",
> though. Granted, the circuits do not follow the usual rule of
> "parallel on one side, serial on the other", but is that
> actually required for calling a circuit to be called CMOS,
<
No, The serial on one side parallel on the other is the only
means where there is no constant crowbar current in the
gate {I.e., a direct path from Vdd to Gnd in non-transient
input condition.}
<
> or isn't it possible to deviate from that as long as the
> signal logic is the same for both polarities?

Anton Ertl <anton@mips.complang.tuwien.ac.at> wrote:
> Thomas Koenig <tkoenig@netcologne.de> writes:
>
> >I'm not quite sure I understand why it is labeled "Not CMOS",
> >though. Granted, the circuits do not follow the usual rule of
> >"parallel on one side, serial on the other", but is that
> >actually required for calling a circuit to be called CMOS,
>
> <https://en.wikipedia.org/wiki/CMOS#Duality> suggests this.

Is that actually a necessity in real life?

For example, suppose I had a circuit where if A, B or C were high then the
output should be low. I can wire those up with three parallel NMOS
transistors between the output and Vss.

But then suppose that I know that if D goes low then the output should be
high. Furthermore I know that D never goes low when A, B or C are high. I
could use D to drive a PMOS between the output and Vdd.

That's an output signal that is always driven, assuming the implicit input
conditions are met. It is not fully specified, in the sense of being valid
for all inputs, but it could be as part of a wider system as generated by a
synthesis tool. And it saves transistors over fully matching the pairs.

In older CMOS technologies it might actually be about balanced in size,
given the ~3x higher mobility of NMOS over PMOS.

It seems like the duality is a concept which is useful in terms of thinking
about CMOS circuits (ie there's no implicit pullup/pulldown, signals must
always be driven, so every signal is wired to both a PMOS and an NMOS
transistor). But when there are corners to be cut, it seems like a pretty
obvious one to go for.

Theo

On Friday, August 27, 2021 at 5:51:14 PM UTC-5, Theo Markettos wrote:
> Anton Ertl <an...@mips.complang.tuwien.ac.at> wrote:
> > Thomas Koenig <tko...@netcologne.de> writes:
> >
> > >I'm not quite sure I understand why it is labeled "Not CMOS",
> > >though. Granted, the circuits do not follow the usual rule of
> > >"parallel on one side, serial on the other", but is that
> > >actually required for calling a circuit to be called CMOS,
> >
> > <https://en.wikipedia.org/wiki/CMOS#Duality> suggests this.
> Is that actually a necessity in real life?
>
> For example, suppose I had a circuit where if A, B or C were high then the
> output should be low. I can wire those up with three parallel NMOS
> transistors between the output and Vss.
>
> But then suppose that I know that if D goes low then the output should be
> high. Furthermore I know that D never goes low when A, B or C are high. I
> could use D to drive a PMOS between the output and Vdd.
>
> That's an output signal that is always driven, assuming the implicit input
> conditions are met. It is not fully specified, in the sense of being valid
> for all inputs, but it could be as part of a wider system as generated by a
> synthesis tool. And it saves transistors over fully matching the pairs.
>
> In older CMOS technologies it might actually be about balanced in size,
> given the ~3x higher mobility of NMOS over PMOS.
>
> It seems like the duality is a concept which is useful in terms of thinking
> about CMOS circuits (ie there's no implicit pullup/pulldown, signals must
> always be driven, so every signal is wired to both a PMOS and an NMOS
> transistor). But when there are corners to be cut, it seems like a pretty
> obvious one to go for.
<
This "duality" of which you speak is simply using deMorgan's laws.
>
> Theo

Quadibloc <jsavard@ecn.ab.ca> wrote:
> On Thursday, August 26, 2021 at 1:29:13 AM UTC-6, David Brown wrote:
> > The Pentium 4
> > showed what you get when you use long pipelines to target bragging
> > rights of higher clocks speeds rather than actual real-world
> > performance.
>
> That's what I _thought_ Intel was up to at the time.
>
> However, since then I learned better. The higher clock speeds did
> actually reflect higher performance... in terms of _throughput_,
> the same way that having more cores means more performance.
>
> While a chip with twice the cores and the same clock speed can't
> perform a single thread any faster, it can perform twice the threads.
> A chip with a higher clock speed but more clocks per instructions is
> also able to perform additional threads... during the in-between
> clocks.
>
> And, unlike a multi-core chip, sometimes the additional parallel workload
> can belong to the same thread, thanks to out-of-order execution.

Hmm, IIRC hypethreading was after initial Pentium 4 design. And
Pentium 4 design was attempting to get high _single thread_
performance. One of Pentium 4 innovations was "early release"
and replay: instructions were passed to execution units
before it was known that arguments are available, and
re-issued if execution failed due to missing arguments.
My impression from reported benchmarks is that this mechanizm
wasted nontrivial part of execution capabilities, so would
be detrimental to good hyperthreaded throughput.

Concerning more general question of througput, one of Pentium 4
weaknesess was to small number of "fast" instructions, notably
shifts (or multiply) had to take slow path. Clearly, making
more slower cores gives better througput than one fast core.

--
Waldek Hebisch

(Warning to readers: component-level electronic design is far from my
field of competence, so I may be wrong to an arbitrary amount.)

On 2021-08-27 16:53, Anton Ertl wrote:
> Niklas Holsti <niklas.holsti@tidorum.invalid> writes:
>> On 2021-08-27 9:50, Thomas Koenig wrote:
>>> If you look at, for example,
>>> https://sus.ziti.uni-heidelberg.de/Lehre/WS1617_DST/DST_Fischer_06_Einfache_Bloecke_FF.pptx.pdf
>>> on slide 22 (in German) you will find a 24-transistor inverting full adder
>>> made up of 24 transistors. Page 18 will show you the implementation
>>> based on AOI logic.
>>>
>>> If you implemented the AOI logic with NAND and NOR gates, you would use
>>> many more transistors.
>>
>>
>> Hm. Slide 18, showing the AOI logic, also says "10+2" transistors for
>> the carry, and "14+2" transistors for the sum. That would be a total of
>> 28 transistors, not so many more than 24. But perhaps I misunderstand
>> slide 18, and its transistor counts do not reflect an implementation
>> built from gates?
>
> It says "gemischtes Gatter" (mixed gate) on slide 18, whatever that
> means. If I count 4 transistors for every 2-input gate, 2 for every
> 1-input gate, and 6 for every 3-input gate,

So you are assuming the number of transistors per gate that a CMOS gate
implementation needs, while I assumed the smaller numbers for a non-CMOS
implementation.

> the result is 18 transistors for the C_out part and 22 for the S
> part, totalling 40.

If you assume twice the number of transistors per gate, of course you
get twice the total number that I got.

It now seems to me that the point of the "optimized" circuit on slide 22
is that it gets rid of the complementary transistors that basic CMOS
gates need, and thus halves the total number of transistors for the
whole circuit, compared to a composition of basic CMOS gates. If so, it
could (partly) explain why complex logic could be built efficiently from
basic gates in non-CMOS technology, but is sub-optimal for CMOS.

Niklas Holsti <niklas.holsti@tidorum.invalid> schrieb:
> (Warning to readers: component-level electronic design is far from my
> field of competence, so I may be wrong to an arbitrary amount.)
>
> On 2021-08-27 16:53, Anton Ertl wrote:
>> Niklas Holsti <niklas.holsti@tidorum.invalid> writes:
>>> On 2021-08-27 9:50, Thomas Koenig wrote:
>>>> If you look at, for example,
>>>> https://sus.ziti.uni-heidelberg.de/Lehre/WS1617_DST/DST_Fischer_06_Einfache_Bloecke_FF.pptx.pdf
>>>> on slide 22 (in German) you will find a 24-transistor inverting full adder
>>>> made up of 24 transistors. Page 18 will show you the implementation
>>>> based on AOI logic.
>>>>
>>>> If you implemented the AOI logic with NAND and NOR gates, you would use
>>>> many more transistors.
>>>
>>>
>>> Hm. Slide 18, showing the AOI logic, also says "10+2" transistors for
>>> the carry, and "14+2" transistors for the sum. That would be a total of
>>> 28 transistors, not so many more than 24. But perhaps I misunderstand
>>> slide 18, and its transistor counts do not reflect an implementation
>>> built from gates?
>>
>> It says "gemischtes Gatter" (mixed gate) on slide 18, whatever that
>> means. If I count 4 transistors for every 2-input gate, 2 for every
>> 1-input gate, and 6 for every 3-input gate,
>

> So you are assuming the number of transistors per gate that a CMOS gate
> implementation needs, while I assumed the smaller numbers for a non-CMOS
> implementation.

[not addressed to me, but I'll reply anyway]

The examples slides I posted are about CMOS. It is clear that you can
save transistors going to a NMOS-only implementation, for example

>
>
>> the result is 18 transistors for the C_out part and 22 for the S
>> part, totalling 40.
>
>
> If you assume twice the number of transistors per gate, of course you
> get twice the total number that I got.

That is not what happened.

On slide 21, you can see on the left hand side a normal CMOS variant
for the generation of the inverted carry using 10 transistors.
On the top of slide 18, you see the "mixed gate" (in this case,
an "or-and-or-invert" gate) for doing the same thing which is
realized on on slide 21.

Realizing the mixed gate out of AND and OR gates in CMOS would have
taken far more transistors, as Anton explained.

You could realize the lower half of what is on slide 21 in NMOS
only and would need five transistors plus one pullup resistor
(or one depletion mode transistor fulfilling the same role).

If you realized the OAOI gate on the top of slide 18 using NMOS
using just AND and OR (or NAND and NOR) you would need far mor
transistors than five plus one, including more pullup resistors
respective depletion load transistors (I didn't count).

> It now seems to me that the point of the "optimized" circuit on slide 22
> is that it gets rid of the complementary transistors that basic CMOS
> gates need,

No. What the optimized circuit on slide 22 (or the left hand of
slide 21) does is to use an (under the circumstances) logically
equivalent, but different circuit on the positive side in order
to avoid a gate delay for the carry propagation.

Slide 21 explains the transoformation. Let me just run the
text though DeepL for a translation:

* The carry is given by Cout = AB + (A+B)Cin.
* This function can be implemented with the mixed gate Y = !(AB+(A+B)Cin).
* Problem: 3 PMOS on top of each other ('Stack height' = 3)
* Since two of each of the 5 inputs of the Y gate are identical, not all input combinations occur!

* The PMOS branch can be transformed:
(!A+!B)(!A!B+!C) = !A(!A!B+!C) + !B(!A!B+!C)
= !A!B+!A!C+!A!B+!B!C = !A!B + (!A+!B)!C.
* This leads to a NOT-CMOS gate:

.... where we are currently depating if this is indeed "not CMOS"
or not. It certainly fulfills the logical requirement for CMOS,
but not the normal design principle.

antispam@math.uni.wroc.pl <antispam@math.uni.wroc.pl> schrieb:

> Clearly, making
> more slower cores gives better througput than one fast core.

Depends very much on the application.
>

MitchAlsup <MitchAlsup@aol.com> wrote:
> This "duality" of which you speak is simply using deMorgan's laws.

DeMorgan's laws operate in the two-level logic of 0 and 1. CMOS transistors
operate in the four-level logic of 0, 1, z and x. The argument goes that
you can optimise a circuit at the transistor level by making judicious use
of z and x, which breaks the 1:1 correspondence between NMOS and PMOS
transistors.

Theo

antispam@math.uni.wroc.pl wrote:
> Quadibloc <jsavard@ecn.ab.ca> wrote:
>> On Thursday, August 26, 2021 at 1:29:13 AM UTC-6, David Brown wrote:
>>> The Pentium 4
>>> showed what you get when you use long pipelines to target bragging
>>> rights of higher clocks speeds rather than actual real-world
>>> performance.
>> That's what I _thought_ Intel was up to at the time.
>>
>> However, since then I learned better. The higher clock speeds did
>> actually reflect higher performance... in terms of _throughput_,
>> the same way that having more cores means more performance.
>>
>> While a chip with twice the cores and the same clock speed can't
>> perform a single thread any faster, it can perform twice the threads.
>> A chip with a higher clock speed but more clocks per instructions is
>> also able to perform additional threads... during the in-between
>> clocks.
>>
>> And, unlike a multi-core chip, sometimes the additional parallel workload
>> can belong to the same thread, thanks to out-of-order execution.
>
> Hmm, IIRC hypethreading was after initial Pentium 4 design. And
> Pentium 4 design was attempting to get high _single thread_
> performance. One of Pentium 4 innovations was "early release"
> and replay: instructions were passed to execution units
> before it was known that arguments are available, and
> re-issued if execution failed due to missing arguments.
> My impression from reported benchmarks is that this mechanizm
> wasted nontrivial part of execution capabilities, so would
> be detrimental to good hyperthreaded throughput.

This effect was called a "replay cyclone/tornado/typhoon".

IIRC the wire transit time from the scheduler to function units was
more than 1 clock so it performed "speculative instruction scheduling"
and guessed when a cache hit would be returned or that resources
would be available, and launched the uOp in anticipation.
Then if the load missed or there was a resource conflict,
the uOp at a minimum all its dependents that also were
speculatively launched had to be replayed.

This forms a positive feedback loop that results in replays over and over.

Tornado Warning: the Perils of Selective Replay
in Multithreaded Processors, 2005
http://web.cs.ucla.edu/~reinman/mars/papers/ICS-05-Zephyr.pdf

The Calm Before the Storm: Reducing Replays in
the Cyclone Scheduler, 2004
http://web.cs.ucla.edu/~reinman/mars/papers/PACS-04-Cyclone.pdf

There was also the issue of a big centralized scheduler trying
to take all the different considerations into account.
They became so complex they had to be pipelined.

This was one reason I preferred a design wherein distributed reservation
stations each make their own local simple decision on scheduling.

Theo Markettos <theom+news@chiark.greenend.org.uk> writes:
>MitchAlsup <MitchAlsup@aol.com> wrote:
>> This "duality" of which you speak is simply using deMorgan's laws.
>
>DeMorgan's laws operate in the two-level logic of 0 and 1. CMOS transistors
>operate in the four-level logic of 0, 1, z and x. The argument goes that
>you can optimise a circuit at the transistor level by making judicious use
>of z and x, which breaks the 1:1 correspondence between NMOS and PMOS
>transistors.

However, in the present case the transformation on slide 21 of
<https://sus.ziti.uni-heidelberg.de/Lehre/WS1617_DST/DST_Fischer_06_Einfache_Bloecke_FF.pptx.pdf>
just uses the levels 0 and 1 for the output, and yet Professor Fischer
calls the result non-CMOS. There are some intermediate
high-impendance (Z?) levels in some places in both circuits, so that
cannot be the reason for calling it non-CMOS.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

Anton Ertl wrote:
> Theo Markettos <theom+news@chiark.greenend.org.uk> writes:
>> MitchAlsup <MitchAlsup@aol.com> wrote:
>>> This "duality" of which you speak is simply using deMorgan's laws.
>> DeMorgan's laws operate in the two-level logic of 0 and 1. CMOS transistors
>> operate in the four-level logic of 0, 1, z and x. The argument goes that
>> you can optimise a circuit at the transistor level by making judicious use
>> of z and x, which breaks the 1:1 correspondence between NMOS and PMOS
>> transistors.
>
> However, in the present case the transformation on slide 21 of
> <https://sus.ziti.uni-heidelberg.de/Lehre/WS1617_DST/DST_Fischer_06_Einfache_Bloecke_FF.pptx.pdf>
> just uses the levels 0 and 1 for the output, and yet Professor Fischer
> calls the result non-CMOS. There are some intermediate
> high-impendance (Z?) levels in some places in both circuits, so that
> cannot be the reason for calling it non-CMOS.
>
> - anton

I looked through a bunch of CMOS PDF books and the ones that
mention it at all most commonly call this AOI Logic (AND-OR-INVERT)
or OAI Logic (OR-AND-INVERT). Compound/complex gates was also used.

They appear to treat it as a normal optimization at the
standard cell and transistor circuit synthesis design level.
I did not see any reference to it as "not cmos".

MitchAlsup <MitchAlsup@aol.com> schrieb:
> On Friday, August 27, 2021 at 1:50:09 AM UTC-5, Thomas Koenig wrote:
>> Quadibloc <jsa...@ecn.ab.ca> schrieb:
>> > On Thursday, August 26, 2021 at 5:50:35 AM UTC-6, Theo Markettos wrote:
>> >> Quadibloc <jsa...@ecn.ab.ca> wrote:
>> >> > On Wednesday, August 25, 2021 at 8:57:58 AM UTC-6, vasco...@gmail.com wrote:
>> >
>> >> > > Are processors still designed on top of NAND and NOR gates or what?
>> >
>> >> > Yes. Very much so. NAND and NOR gates are what you build from transistors in
>> >> > CMOS.
>> >
>> >> Yes and no. You /can/ build NAND and NOR gates from transistors, and they
>> >> do get used a lot, but for the last few decades the building blocks have
>> >> been 'standard cells'.
>> >
>> > True, _except_ for highly-optimized designs like the microprocessors from
>> > AMD and Intel. But since standard cells are themselves built from NAND
>> > and NOR gates,
>> Certainly not, we are out of the age of the Apollo guidance computer.
>>
>> If you look at, for example,
>> https://sus.ziti.uni-heidelberg.de/Lehre/WS1617_DST/DST_Fischer_06_Einfache_Bloecke_FF.pptx.pdf
>> on slide 22 (in German) you will find a 24-transistor inverting full adder
>> made up of 24 transistors. Page 18 will show you the implementation
>> based on AOI logic.
><
> What you find on page 22 is a (3-2)-compressor (A.K.A. Full adder) with 2 gates of delay.

I'm not sure how to count a gate delay, but I looked at this
some more. Assuming that A and B are already present, there
is only a single transistor that needs to be switched for
the inverted carry out.

If you make a ripple-carry adder out of this, assume that you want
a carry-in, propagate the inverted carry and add an inverter for
the sum for bit 0,2,4, ... and an inverter for the inputs A1, B1,
A3, B3, ... the number of transistor delays n until the result
is complete is

bits n
1 4
2 5
4 6
6 8
8 10
16 18

The inverted carry has a fan-out of two in that case.

How many gate delays would this translate to?

On Wednesday, August 25, 2021 at 5:45:17 AM UTC-4, vasco...@gmail.com wrote:
[snip]
> I miss anonymous posting in the main RWT.com threads. *sniff*

I did not notice any change in posting requirements. I would prefer people
post under pseudonyms rather than truly anonymously (even anon, anon2,
and Anon are not as easily recognized). (Faking ID has not been a problem
there; most fakes would be fairly quickly detected an deleted, but no
falsification seems better.)

(Since I have no reason to conceal my identity, I use my name. Those
working in the field could have reason for not using their real names, if
only to avoid having to include a disclaimer in every post that the information
is not representative of their employers (and being able to be a little less
restrained in communication — not violating trade secrets or bad-mouthing
the employer but writing personal opinion as personal opinion).)

What prevents anonymous posting?

Thomas Koenig <tkoenig@netcologne.de> writes:
>The inverted carry has a fan-out of two in that case.

I count 6 transistors on page 22 where C_in is used, so for a
ripple-carry-adder this looks to me like a fan-out of 6.

>How many gate delays would this translate to?

The usual metric is an inverter with a fan-out of 4 (FO4), so this is
slower than one FO4 gate.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

On Sunday, August 29, 2021 at 6:47:12 AM UTC-5, Thomas Koenig wrote:
> MitchAlsup <Mitch...@aol.com> schrieb:
> > On Friday, August 27, 2021 at 1:50:09 AM UTC-5, Thomas Koenig wrote:
> >> Quadibloc <jsa...@ecn.ab.ca> schrieb:
> >> > On Thursday, August 26, 2021 at 5:50:35 AM UTC-6, Theo Markettos wrote:
> >> >> Quadibloc <jsa...@ecn.ab.ca> wrote:
> >> >> > On Wednesday, August 25, 2021 at 8:57:58 AM UTC-6, vasco...@gmail.com wrote:
> >> >
> >> >> > > Are processors still designed on top of NAND and NOR gates or what?
> >> >
> >> >> > Yes. Very much so. NAND and NOR gates are what you build from transistors in
> >> >> > CMOS.
> >> >
> >> >> Yes and no. You /can/ build NAND and NOR gates from transistors, and they
> >> >> do get used a lot, but for the last few decades the building blocks have
> >> >> been 'standard cells'.
> >> >
> >> > True, _except_ for highly-optimized designs like the microprocessors from
> >> > AMD and Intel. But since standard cells are themselves built from NAND
> >> > and NOR gates,
> >> Certainly not, we are out of the age of the Apollo guidance computer.
> >>
> >> If you look at, for example,
> >> https://sus.ziti.uni-heidelberg.de/Lehre/WS1617_DST/DST_Fischer_06_Einfache_Bloecke_FF.pptx.pdf
> >> on slide 22 (in German) you will find a 24-transistor inverting full adder
> >> made up of 24 transistors. Page 18 will show you the implementation
> >> based on AOI logic.
> ><
> > What you find on page 22 is a (3-2)-compressor (A.K.A. Full adder) with 2 gates of delay.
<
> I'm not sure how to count a gate delay, but I looked at this
> some more. Assuming that A and B are already present, there
> is only a single transistor that needs to be switched for
> the inverted carry out.
<
The Cin signal created the !Cout signal and !Cout is used to create !S
This is 2 inversions and thus 2 gates of delay.
>
> If you make a ripple-carry adder out of this, assume that you want
> a carry-in, propagate the inverted carry and add an inverter for
> the sum for bit 0,2,4, ... and an inverter for the inputs A1, B1,
> A3, B3, ... the number of transistor delays n until the result
> is complete is
>
> bits n
> 1 4
> 2 5
> 4 6
> 6 8
> 8 10
> 16 18
>
> The inverted carry has a fan-out of two in that case.
>
> How many gate delays would this translate to?

On Sunday, August 29, 2021 at 9:15:16 AM UTC-5, Anton Ertl wrote:
> Thomas Koenig <tko...@netcologne.de> writes:
> >The inverted carry has a fan-out of two in that case.
<
> I count 6 transistors on page 22 where C_in is used, so for a
> ripple-carry-adder this looks to me like a fan-out of 6.
<
Generally an input touches at least 1 p-channel and 1 n-channel
So, I see fan in of 3 and thus fan out of 3 for the previous stage.
<
> >How many gate delays would this translate to?
<
> The usual metric is an inverter with a fan-out of 4 (FO4), so this is
> slower than one FO4 gate.
<
The usual metric is a 4-input NAND driving 4 inputs of other gates.
Generally an inverter is 4× faster than this std. gate.
<
> - anton
> --
> 'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
> Mitch Alsup, <c17fcd89-f024-40e7...@googlegroups.com>

Anton Ertl <anton@mips.complang.tuwien.ac.at> schrieb:
> Thomas Koenig <tkoenig@netcologne.de> writes:
>>The inverted carry has a fan-out of two in that case.
>
> I count 6 transistors on page 22 where C_in is used, so for a
> ripple-carry-adder this looks to me like a fan-out of 6.

By that count, a CMOS inverter driving a single inverter would
have a fan-out of two (because it drives both the p and the
n transistor), and I think that's sort of the definition
of a fan-out of one.

So, counting only the transistors on one side, I get to a fan-out
of three, which would mean it would be a bit faster than a FO4
inverter. That doesn't sound bad (if it is indeed correct).

MitchAlsup <MitchAlsup@aol.com> schrieb:
> On Sunday, August 29, 2021 at 6:47:12 AM UTC-5, Thomas Koenig wrote:
>> MitchAlsup <Mitch...@aol.com> schrieb:
>> > On Friday, August 27, 2021 at 1:50:09 AM UTC-5, Thomas Koenig wrote:
>> >> Quadibloc <jsa...@ecn.ab.ca> schrieb:
>> >> > On Thursday, August 26, 2021 at 5:50:35 AM UTC-6, Theo Markettos wrote:
>> >> >> Quadibloc <jsa...@ecn.ab.ca> wrote:
>> >> >> > On Wednesday, August 25, 2021 at 8:57:58 AM UTC-6, vasco...@gmail.com wrote:
>> >> >
>> >> >> > > Are processors still designed on top of NAND and NOR gates or what?
>> >> >
>> >> >> > Yes. Very much so. NAND and NOR gates are what you build from transistors in
>> >> >> > CMOS.
>> >> >
>> >> >> Yes and no. You /can/ build NAND and NOR gates from transistors, and they
>> >> >> do get used a lot, but for the last few decades the building blocks have
>> >> >> been 'standard cells'.
>> >> >
>> >> > True, _except_ for highly-optimized designs like the microprocessors from
>> >> > AMD and Intel. But since standard cells are themselves built from NAND
>> >> > and NOR gates,
>> >> Certainly not, we are out of the age of the Apollo guidance computer.
>> >>
>> >> If you look at, for example,
>> >> https://sus.ziti.uni-heidelberg.de/Lehre/WS1617_DST/DST_Fischer_06_Einfache_Bloecke_FF.pptx.pdf
>> >> on slide 22 (in German) you will find a 24-transistor inverting full adder
>> >> made up of 24 transistors. Page 18 will show you the implementation
>> >> based on AOI logic.
>> ><
>> > What you find on page 22 is a (3-2)-compressor (A.K.A. Full adder) with 2 gates of delay.
><
>> I'm not sure how to count a gate delay, but I looked at this
>> some more. Assuming that A and B are already present, there
>> is only a single transistor that needs to be switched for
>> the inverted carry out.
><
> The Cin signal created the !Cout signal and !Cout is used to create !S
> This is 2 inversions and thus 2 gates of delay.

That is clear, I think.

What I was interested in is the delay for carry propagation if
you put a few of these together for a ripple-carry adder.

anton@mips.complang.tuwien.ac.at (Anton Ertl) writes:
>Thomas Koenig <tkoenig@netcologne.de> writes:
>>The inverted carry has a fan-out of two in that case.
>
>I count 6 transistors on page 22 where C_in is used, so for a
>ripple-carry-adder this looks to me like a fan-out of 6.

Plus two more that are used directly in the S-computing part of the
circuit (then still called C_out).

However, you need to drive only two transistors for getting the C_in
for the next full adder. So you could drive the other 6 with an
intermediary inverter, reducing the fan-out of the C_out circuit to
two circuits (4 transistors).

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>