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devel / comp.arch / The world is running out of microchips – here’s the solution | New Scientist

SubjectAuthor
* The world is running out of microchips – here’sDingbat
+* Re: The world is running out of microchips – hereQuadibloc
|+* Re: The world is running out of microchips – here’EricP
||`- Re: The world is running out of microchips – heDavid Schultz
|+* Re: The world is running out of microchips – here’s the solution | New ScientistTheo Markettos
||`* Re: The world is running out of microchips – hereMitchAlsup
|| +* Re: The world is running out of microchips – heBGB
|| |+* Re: The world is running out of microchips –Thomas Koenig
|| ||`* Re: The world is running out of microchips – heBGB
|| || `* Re: The world is running out of microchips –Thomas Koenig
|| ||  +* Re: The world is running out of microchips – heBGB
|| ||  |`* Re: The world is running out of microchips – heStephen Fuld
|| ||  | `* Re: The world is running out of microchips – here’EricP
|| ||  |  `* Re: The world is running out of microchips – heBGB
|| ||  |   `* Re: The world is running out of microchips – heStephen Fuld
|| ||  |    `* Re: The world is running out of microchips – hereMitchAlsup
|| ||  |     `* Re: The world is running out of microchips – heStephen Fuld
|| ||  |      `* Re: The world is running out of microchips – heBGB
|| ||  |       `- Re: The world is running out ofBrett
|| ||  `* Re: The world is running out of microchips – hereTerje Mathisen
|| ||   `* Re: The world is running out of microchips – heBGB
|| ||    `* Re: The world is running out of microchips –Thomas Koenig
|| ||     `* Re: The world is running out of microchips _John Dallman
|| ||      +* Re: The world is running out of microchips _Thomas Koenig
|| ||      |`* Re: The world is running out of microchips _David Brown
|| ||      | `- Re: The world is running out of microchips _MitchAlsup
|| ||      `* Re: The world is running out of microchips _Terje Mathisen
|| ||       +- Re: The world is running out of microchips _MitchAlsup
|| ||       +* Re: The world is running out of microchips _David Brown
|| ||       |+* Re: The world is running out of microchips _Thomas Koenig
|| ||       ||+* Re: The world is running out of microchips _Branimir Maksimovic
|| ||       |||`* Re: The world is running out of microchips _MitchAlsup
|| ||       ||| `- Re: The world is running out of microchips _Branimir Maksimovic
|| ||       ||`- Re: The world is running out of microchips _MitchAlsup
|| ||       |+* Re: The world is running out of microchips _Terje Mathisen
|| ||       ||`* Re: The world is running out of microchips _David Brown
|| ||       || +- Re: The world is running out of microchips _BGB
|| ||       || `* Re: The world is running out of microchips _Terje Mathisen
|| ||       ||  +* Re: The world is running out of microchips _David Brown
|| ||       ||  |`* Re: The world is running out of microchips _Stephen Fuld
|| ||       ||  | `- Re: The world is running out of microchips _MitchAlsup
|| ||       ||  `* Re: The world is running out of microchips _clamky
|| ||       ||   +* Re: The world is running out of microchips _Michael S
|| ||       ||   |+- Re: The world is running out of microchips _clamky
|| ||       ||   |`* Re: The world is running out of microchips _David Brown
|| ||       ||   | `- Re: The world is running out of microchips _clamky
|| ||       ||   +* Re: The world is running out of microchips _Terje Mathisen
|| ||       ||   |`- Re: The world is running out of microchips _clamky
|| ||       ||   +* Re: The world is running out of microchips _Ivan Godard
|| ||       ||   |+* Re: The world is running out of microchips _David Brown
|| ||       ||   ||`* Re: The world is running out of microchips _BGB
|| ||       ||   || `* Re: The world is running out of microchips _Stephen Fuld
|| ||       ||   ||  +- Re: The world is running out of microchips _BGB
|| ||       ||   ||  `* Re: The world is running out of microchips _Terje Mathisen
|| ||       ||   ||   `- Re: The world is running out of microchips _BGB
|| ||       ||   |`- Re: The world is running out of microchips _Terje Mathisen
|| ||       ||   `- Re: The world is running out of microchips _Branimir Maksimovic
|| ||       |`* Re: The world is running out of microchips _Stephen Fuld
|| ||       | +- Re: The world is running out of microchips _Ivan Godard
|| ||       | +- Re: The world is running out of microchips _MitchAlsup
|| ||       | `* Re: The world is running out of microchips _David Brown
|| ||       |  +* Re: The world is running out of microchips _clamky
|| ||       |  |`- Re: The world is running out of microchips _Thomas Koenig
|| ||       |  `- Re: The world is running out of microchips _Stephen Fuld
|| ||       `- Re: The world is running out of microchips _Anton Ertl
|| |`* Re: The world is running out of microchips – hereQuadibloc
|| | `* Re: The world is running out of microchips – hereMitchAlsup
|| |  `- Re: The world is running out of microchips – heBGB
|| `* Re: The world is running out of microchips – here’EricP
||  `* Re: The world is running out of microchips – hereMitchAlsup
||   `* Re: The world is running out of microchips – here’EricP
||    +- Re: The world is running out of microchips – hereMitchAlsup
||    `* Re: The world is running out of microchips – here’s the solution | New ScientistAnton Ertl
||     +- Re: The world is running out of microchips – heBGB
||     `- Re: The world is running out ofEricP
|`- Re: The world is running out of microchips – hereDingbat
`* Re: The world is running out of microchips – hereQuadibloc
 `- Re: The world is running out of microchips – hereMitchAlsup

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The world is running out of microchips – here’s the solution | New Scientist

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Subject: The_world_is_running_out_of_microchips_–_here’s_
the_solution_|_New_Scientist
From: ranjit_m...@yahoo.com (Dingbat)
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 by: Dingbat - Sat, 11 Sep 2021 02:20 UTC

The world is running out of microchips – here’s the solution | New Scientisthttps://www.newscientist.com/article/mg25133510-800-the-world-is-running-out-of-microchips-heres-the-solution/

I respond: The problem is a temporary shortage in manufacturing capacity. Being temporary, the problem should resolve itself.

This article proposes a nonsensical solution to a non-problem. There is no dearth of free designs. RISC V is a royalty free ISA (Instruction Set Architecture) from Berkeley U. CORE-V is a series of open-source core Verilog and/or VHDL designs of RISC V processors produced under the OSRC (Open Source RISC-V Core) Initiative and listed on the RISC V Foundation's website..

Those would be your free designs but many Commercial RISC-V core vendors ignore those designs which must be inferior in some way since at significant expense, they develop their own proprietary designs, verify and guarantee them, and provide technical support to paying licensees.

A free SoC (System on Chip) design might be competitive but I hazard a guess that commercial vendors that sponsor or produce free core designs would have a vested interest in preventing that since the purpose of their interest in a free core design might be to ensure a large(r) market for their proprietary product such as an SoC or coprocessor.

Re: The world is running out of microchips – here’s the solution | New Scientist

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Subject: Re:_The_world_is_running_out_of_microchips_–_here
’s_the_solution_|_New_Scientist
From: jsav...@ecn.ab.ca (Quadibloc)
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 by: Quadibloc - Sun, 19 Sep 2021 12:12 UTC

On Friday, September 10, 2021 at 8:20:48 PM UTC-6, Dingbat wrote:
> The world is running out of microchips – here’s the solution | New Scientist
https://www.newscientist.com/article/mg25133510-800-the-world-is-running-out-of-microchips-heres-the-solution/

> I respond: The problem is a temporary shortage in manufacturing capacity. Being temporary, the problem should resolve itself.

> This article proposes a nonsensical solution to a non-problem.

It's certainly true that our dependence on a few companies - TSMC, Samsung, and Intel - that can
put chip designs on silicon...

isn't going to be solved by having an open-source model democratize the production of
more chip designs.

Instead, for the article to be about something that would even *address* the problem,
it would have to be about some new technology that would let everyone and his
uncle practice EUV lithography in his or her basement. That does not appear to be
forthcoming any time soon.

However, with all but the first part of the article being behind a paywall, perhaps I
am being unfair to it.

If chip *design* is democratized, suddenly there are more and smaller customers
for chip foundries. So perhaps the writer envisaged that this would create a
market environment that would foster the emergence of more and smaller
chip foundries.

And the chips needed for automobiles, for example, aren't on the latest process
nodes. So *they* could already come from other companies, like GlobalFoundries.

John Savard

Re: The world is running out of microchips – here’s the solution | New Scientist

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Subject: Re: The world is running out of microchips – here’
s the solution | New Scientist
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 by: EricP - Sun, 19 Sep 2021 15:22 UTC

Quadibloc wrote:
> On Friday, September 10, 2021 at 8:20:48 PM UTC-6, Dingbat wrote:
>> The world is running out of microchips – here’s the solution | New Scientist
> https://www.newscientist.com/article/mg25133510-800-the-world-is-running-out-of-microchips-heres-the-solution/
>
>> I respond: The problem is a temporary shortage in manufacturing capacity. Being temporary, the problem should resolve itself.
>
>> This article proposes a nonsensical solution to a non-problem.
>
> It's certainly true that our dependence on a few companies - TSMC, Samsung, and Intel - that can
> put chip designs on silicon...
>
> isn't going to be solved by having an open-source model democratize the production of
> more chip designs.
>
> Instead, for the article to be about something that would even *address* the problem,
> it would have to be about some new technology that would let everyone and his
> uncle practice EUV lithography in his or her basement. That does not appear to be
> forthcoming any time soon.
>
> However, with all but the first part of the article being behind a paywall, perhaps I
> am being unfair to it.

A paywalled article calling for someone else's
business to be democratized?
Irony and hypocrisy in one neat bundle!

Maybe New Scientist should use 4 billion
of their dollars to get this going.

> If chip *design* is democratized, suddenly there are more and smaller customers
> for chip foundries. So perhaps the writer envisaged that this would create a
> market environment that would foster the emergence of more and smaller
> chip foundries.
>
> And the chips needed for automobiles, for example, aren't on the latest process
> nodes. So *they* could already come from other companies, like GlobalFoundries.
>
> John Savard

There are already a lot of companies that build to older processes.

List of semiconductor fabrication plants
https://en.wikipedia.org/wiki/List_of_semiconductor_fabrication_plants

Re: The world is running out of microchips – here’s the solution | New Scientist

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From: theom+n...@chiark.greenend.org.uk (Theo Markettos)
Newsgroups: comp.arch
Subject: Re: The world is running out of microchips –_here’s the solution | New Scientist
Date: 19 Sep 2021 22:13:19 +0100 (BST)
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 by: Theo Markettos - Sun, 19 Sep 2021 21:13 UTC

Quadibloc <jsavard@ecn.ab.ca> wrote:
> If chip *design* is democratized, suddenly there are more and smaller customers
> for chip foundries. So perhaps the writer envisaged that this would create a
> market environment that would foster the emergence of more and smaller
> chip foundries.

Surely that would go the other way. More designs = more masks = making in
smaller batches. Assuming the number of chips being made doesn't change a
great deal (make your own rather than buying one in) it would cause the fabs
to become less efficient; rather than making 10 million of one chip, make
100K of each of 100 designs. This would seem to make the fab bottleneck
worse not better.

If you can stimulate demand such that we can build 100x more fabs and the
cost for each comes down, then maybe. But ISTM a fab is like a nuclear
power station - you still need to spend 5-10 years building the thing, even
if the design cost has already been paid off. Short of someone coming up
with a 'small modular fab' concept, we're stuck with them being large and
capital-intensive.

Theo

Re: The world is running out of microchips – here’s the solution | New Scientist

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Subject: Re:_The_world_is_running_out_of_microchips_–_here
’s_the_solution_|_New_Scientist
From: MitchAl...@aol.com (MitchAlsup)
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 by: MitchAlsup - Sun, 19 Sep 2021 22:19 UTC

On Sunday, September 19, 2021 at 4:13:24 PM UTC-5, Theo Markettos wrote:
> Quadibloc <jsa...@ecn.ab.ca> wrote:
> > If chip *design* is democratized, suddenly there are more and smaller customers
> > for chip foundries. So perhaps the writer envisaged that this would create a
> > market environment that would foster the emergence of more and smaller
> > chip foundries.
<
> Surely that would go the other way. More designs = more masks = making in
> smaller batches. Assuming the number of chips being made doesn't change a
> great deal (make your own rather than buying one in) it would cause the fabs
> to become less efficient; rather than making 10 million of one chip, make
> 100K of each of 100 designs. This would seem to make the fab bottleneck
> worse not better.
<
To a large first order. chip fabrication is performed in things called Boats. A boat
contains 13-25 wafers. 12 or 24 of which contain chips, the other to confirm the
process conditions the other wafers encountered.
<
A 12" wafer contains 80,000 dies of MIPS R2000 complexity, and down to a
couple of hundred for GB designs such as Intel/AMD x86-64 server chips.
<
For smaller customers, a single wafer might be enough to provide a years worth
of chips, a boat would then contain a lifetime supply.
<
A mask set for a 14nm die with 10 layers of metal is going to cost $10M minimum.
So, it seems to me that this, in an of itself, prices most small designs out of the FAB.
<
A design team capable of an R2000 design point is going to cost $30M (architecture,
modeling, circuit design, system design, verification, manufacturing engineering,
test engineering, and tester time.}
<
If you had a large market for such a small design, you could probably satisfy 1B
chips per year using a fraction of TSMC capability. But at the overheads you
have (HAVE) to be looking at chips for small markets simply fail in the "lets do it"
department.
>
> If you can stimulate demand such that we can build 100x more fabs and the
> cost for each comes down, then maybe. But ISTM a fab is like a nuclear
> power station - you still need to spend 5-10 years building the thing, even
<
More like 2 years if you already have experience and do not need financing.
<
> if the design cost has already been paid off. Short of someone coming up
> with a 'small modular fab' concept, we're stuck with them being large and
> capital-intensive.
>
> Theo

Re: The world is running out of microchips – here’s the solution | New Scientist

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re’s_the_solution_|_New_Scientist
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 by: BGB - Mon, 20 Sep 2021 06:46 UTC

On 9/19/2021 5:19 PM, MitchAlsup wrote:
> On Sunday, September 19, 2021 at 4:13:24 PM UTC-5, Theo Markettos wrote:
>> Quadibloc <jsa...@ecn.ab.ca> wrote:
>>> If chip *design* is democratized, suddenly there are more and smaller customers
>>> for chip foundries. So perhaps the writer envisaged that this would create a
>>> market environment that would foster the emergence of more and smaller
>>> chip foundries.
> <
>> Surely that would go the other way. More designs = more masks = making in
>> smaller batches. Assuming the number of chips being made doesn't change a
>> great deal (make your own rather than buying one in) it would cause the fabs
>> to become less efficient; rather than making 10 million of one chip, make
>> 100K of each of 100 designs. This would seem to make the fab bottleneck
>> worse not better.
> <
> To a large first order. chip fabrication is performed in things called Boats. A boat
> contains 13-25 wafers. 12 or 24 of which contain chips, the other to confirm the
> process conditions the other wafers encountered.
> <
> A 12" wafer contains 80,000 dies of MIPS R2000 complexity, and down to a
> couple of hundred for GB designs such as Intel/AMD x86-64 server chips.
> <
> For smaller customers, a single wafer might be enough to provide a years worth
> of chips, a boat would then contain a lifetime supply.
> <
> A mask set for a 14nm die with 10 layers of metal is going to cost $10M minimum.
> So, it seems to me that this, in an of itself, prices most small designs out of the FAB.
> <
> A design team capable of an R2000 design point is going to cost $30M (architecture,
> modeling, circuit design, system design, verification, manufacturing engineering,
> test engineering, and tester time.}
> <
> If you had a large market for such a small design, you could probably satisfy 1B
> chips per year using a fraction of TSMC capability. But at the overheads you
> have (HAVE) to be looking at chips for small markets simply fail in the "lets do it"
> department.

Probably a dumb idea, but I am left wondering if one could do a
smaller/cheaper fab for small runs of low-density and low-complexity
chips by using DLP for the patterning (in place of masks).

Say, one uses basically about the biggest DLP module they can get in
their fab, uses optics to focus it onto the wafer. Then they move the
DLP image in fixed increments and flash a UV light source or similar to
do the patterning.

Then, when it is time for the next stage, they load the next "mask" into
the DLP, and repeat the process.

Granted, the big obvious limitation is that chip complexity will be
limited by the resolution of the DLP module, and most cinema class
modules are probably pretty weak by these standards.

Well, and/or figure out some way to get fancy with the optics and
"stitch" a bunch of separate DLP modules into a much larger "virtual
module".

Could maybe work for designs in the 200nm - 1200nm range, depending on
things like die size, optics, ...

>>
>> If you can stimulate demand such that we can build 100x more fabs and the
>> cost for each comes down, then maybe. But ISTM a fab is like a nuclear
>> power station - you still need to spend 5-10 years building the thing, even
> <
> More like 2 years if you already have experience and do not need financing.
> <
>> if the design cost has already been paid off. Short of someone coming up
>> with a 'small modular fab' concept, we're stuck with them being large and
>> capital-intensive.
>>
>> Theo

Re: The world is running out of microchips – here’s the solution | New Scientist

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_here’s the solution | New Scientist
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 by: Thomas Koenig - Mon, 20 Sep 2021 10:02 UTC

BGB <cr88192@gmail.com> schrieb:

> Granted, the big obvious limitation is that chip complexity will be
> limited by the resolution of the DLP module, and most cinema class
> modules are probably pretty weak by these standards.

Wikipedia tells me that cinemas have around 4K resolution, so we could
finally make that better 6502 we've been discussing, or maybe even
a 16-bit RISC.

Re: The world is running out of microchips – here’s the solution | New Scientist

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 by: David Schultz - Mon, 20 Sep 2021 11:08 UTC

On 9/19/21 10:22 AM, EricP wrote:
> There are already a lot of companies that build to older processes.
>
> List of semiconductor fabrication plants
> https://en.wikipedia.org/wiki/List_of_semiconductor_fabrication_plants
>
>
Way back in the 90's when I took VLSI design, there was a thing called
TinyChip. A 2 micron process with a chip around 2mm square mostly for
academic purposes. For a modest fee in the hundreds you got four copies
in a 40 pin chip.

I think this service still exists but probably for a slightly more
modern process. I know that the primary tool used then (magic) is still
alive and kicking. So it should be possible to play around with
designing whatever you want.

--
http://davesrocketworks.com
David Schultz

Re: The world is running out of microchips – here’s the solution | New Scientist

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 by: EricP - Mon, 20 Sep 2021 11:37 UTC

MitchAlsup wrote:
> On Sunday, September 19, 2021 at 4:13:24 PM UTC-5, Theo Markettos wrote:
>> Quadibloc <jsa...@ecn.ab.ca> wrote:
>>> If chip *design* is democratized, suddenly there are more and smaller customers
>>> for chip foundries. So perhaps the writer envisaged that this would create a
>>> market environment that would foster the emergence of more and smaller
>>> chip foundries.
> <
>> Surely that would go the other way. More designs = more masks = making in
>> smaller batches. Assuming the number of chips being made doesn't change a
>> great deal (make your own rather than buying one in) it would cause the fabs
>> to become less efficient; rather than making 10 million of one chip, make
>> 100K of each of 100 designs. This would seem to make the fab bottleneck
>> worse not better.
> <
> To a large first order. chip fabrication is performed in things called Boats. A boat
> contains 13-25 wafers. 12 or 24 of which contain chips, the other to confirm the
> process conditions the other wafers encountered.
> <
> A 12" wafer contains 80,000 dies of MIPS R2000 complexity, and down to a
> couple of hundred for GB designs such as Intel/AMD x86-64 server chips.
> <
> For smaller customers, a single wafer might be enough to provide a years worth
> of chips, a boat would then contain a lifetime supply.
> <
> A mask set for a 14nm die with 10 layers of metal is going to cost $10M minimum.
> So, it seems to me that this, in an of itself, prices most small designs out of the FAB.

MIPS R2000 circa 1986 was 110,000 transistors and measured 80 mm^2
in a 2.0 μm double-metal CMOS.

Looking at that list of semi fabs I see that Texas Instruments has a
2000-1000 nm fab in Sherman TX, USA, Microchip 5000-350 nm in Tempe, AZ,
HTE Labs 4000-1000 nm in San Jose, CA.

There are other 1000+ nm fabs in China, Japan, Taiwan, Czech Republic,
Germany, Brazil, India, Israel, and North Korea.

> <
> A design team capable of an R2000 design point is going to cost $30M (architecture,
> modeling, circuit design, system design, verification, manufacturing engineering,
> test engineering, and tester time.}

Stanford MIPS circa 1981-82 was mostly designed by 3 guys without software
tools over 18 months. (The tools they mostly developed themselves.)
Transistor sizing was done by intuition.
Core design team time took 2.3 person-years.
Total design team size was 15 people providing specialty skills
at various points totaling 6.1 person-years.

Design of a High Performance VLSI Processor, Hennessy et al, 1983
http://ai.eecs.umich.edu/people/conway/VLSI/ClassicDesigns/MIPS/MIPS.CT83.pdf

Re: The world is running out of microchips – here’s the solution | New Scientist

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’s_the_solution_|_New_Scientist
From: jsav...@ecn.ab.ca (Quadibloc)
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 by: Quadibloc - Mon, 20 Sep 2021 15:03 UTC

On Monday, September 20, 2021 at 12:46:11 AM UTC-6, BGB wrote:

> Say, one uses basically about the biggest DLP module they can get in
> their fab, uses optics to focus it onto the wafer.

But if you use optics to focus the DLP on the wafer, you might as well
just use a mask. This may have the seed of a good idea in it, however.

For example, illuminate the DLP with a laser. Then, since the laser light
is perfectly collimated, where it will go from the DLP is predetermined,
except for diffraction effects.

John Savard

Re: The world is running out of microchips – here’s the solution | New Scientist

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Subject: Re:_The_world_is_running_out_of_microchips_–_here
’s_the_solution_|_New_Scientist
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 by: MitchAlsup - Mon, 20 Sep 2021 16:04 UTC

On Monday, September 20, 2021 at 6:39:05 AM UTC-5, EricP wrote:
> MitchAlsup wrote:
> > On Sunday, September 19, 2021 at 4:13:24 PM UTC-5, Theo Markettos wrote:
> >> Quadibloc <jsa...@ecn.ab.ca> wrote:
> >>> If chip *design* is democratized, suddenly there are more and smaller customers
> >>> for chip foundries. So perhaps the writer envisaged that this would create a
> >>> market environment that would foster the emergence of more and smaller
> >>> chip foundries.
> > <
> >> Surely that would go the other way. More designs = more masks = making in
> >> smaller batches. Assuming the number of chips being made doesn't change a
> >> great deal (make your own rather than buying one in) it would cause the fabs
> >> to become less efficient; rather than making 10 million of one chip, make
> >> 100K of each of 100 designs. This would seem to make the fab bottleneck
> >> worse not better.
> > <
> > To a large first order. chip fabrication is performed in things called Boats. A boat
> > contains 13-25 wafers. 12 or 24 of which contain chips, the other to confirm the
> > process conditions the other wafers encountered.
> > <
> > A 12" wafer contains 80,000 dies of MIPS R2000 complexity, and down to a
> > couple of hundred for GB designs such as Intel/AMD x86-64 server chips.
> > <
> > For smaller customers, a single wafer might be enough to provide a years worth
> > of chips, a boat would then contain a lifetime supply.
> > <
> > A mask set for a 14nm die with 10 layers of metal is going to cost $10M minimum.
> > So, it seems to me that this, in an of itself, prices most small designs out of the FAB.
> MIPS R2000 circa 1986 was 110,000 transistors and measured 80 mm^2
> in a 2.0 μm double-metal CMOS.
<
Check.
>
> Looking at that list of semi fabs I see that Texas Instruments has a
> 2000-1000 nm fab in Sherman TX, USA, Microchip 5000-350 nm in Tempe, AZ,
> HTE Labs 4000-1000 nm in San Jose, CA.
<
But you don't want to implement it in 1µ or 2µ, you want to implement it in
20nm so the die size shrinks from 80mm^2 to 0.8mm^2 and get thousands
of chips per wafer.
<
You could probably get by with 3-4 layers of metal.
>
> There are other 1000+ nm fabs in China, Japan, Taiwan, Czech Republic,
> Germany, Brazil, India, Israel, and North Korea.
<
If you want dozens of chips from 8" wafers, yes,
If you want thousands of chips per 12" wafer, no.
> > <
> > A design team capable of an R2000 design point is going to cost $30M (architecture,
> > modeling, circuit design, system design, verification, manufacturing engineering,
> > test engineering, and tester time.}
<
> Stanford MIPS circa 1981-82 was mostly designed by 3 guys without software
> tools over 18 months. (The tools they mostly developed themselves.)
> Transistor sizing was done by intuition.
> Core design team time took 2.3 person-years.
> Total design team size was 15 people providing specialty skills
> at various points totaling 6.1 person-years.
<
So what you are saying is that modern tools SLOW DOWN the implementation process !?!
>
> Design of a High Performance VLSI Processor, Hennessy et al, 1983
> http://ai.eecs.umich.edu/people/conway/VLSI/ClassicDesigns/MIPS/MIPS.CT83..pdf

Re: The world is running out of microchips – here’s the solution | New Scientist

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’s_the_solution_|_New_Scientist
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 by: MitchAlsup - Mon, 20 Sep 2021 16:07 UTC

On Monday, September 20, 2021 at 10:03:21 AM UTC-5, Quadibloc wrote:
> On Monday, September 20, 2021 at 12:46:11 AM UTC-6, BGB wrote:
>
> > Say, one uses basically about the biggest DLP module they can get in
> > their fab, uses optics to focus it onto the wafer.
> But if you use optics to focus the DLP on the wafer, you might as well
> just use a mask. This may have the seed of a good idea in it, however.
<
There is always E-Beam lithography.
This is how masks are made, BTW.
The reason they don't use it in production is that it is too slow.
A single mask takes hours on the E-beam machine, where an exposure
using the mask takes fractions of a second. {It actually takes longer
slewing the wafer from chip location to chip location that it does to expose
that chip location.}
>
> For example, illuminate the DLP with a laser. Then, since the laser light
> is perfectly collimated, where it will go from the DLP is predetermined,
> except for diffraction effects.
<
and halation
>
> John Savard

Re: The world is running out of microchips – here’s the solution | New Scientist

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Subject: Re: The world is running out of microchips – here’
s the solution | New Scientist
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 by: EricP - Mon, 20 Sep 2021 17:31 UTC

MitchAlsup wrote:
> On Monday, September 20, 2021 at 6:39:05 AM UTC-5, EricP wrote:
>> MitchAlsup wrote:
>>> On Sunday, September 19, 2021 at 4:13:24 PM UTC-5, Theo Markettos wrote:
>>>> Quadibloc <jsa...@ecn.ab.ca> wrote:
>>>>> If chip *design* is democratized, suddenly there are more and smaller customers
>>>>> for chip foundries. So perhaps the writer envisaged that this would create a
>>>>> market environment that would foster the emergence of more and smaller
>>>>> chip foundries.
>>> <
>>>> Surely that would go the other way. More designs = more masks = making in
>>>> smaller batches. Assuming the number of chips being made doesn't change a
>>>> great deal (make your own rather than buying one in) it would cause the fabs
>>>> to become less efficient; rather than making 10 million of one chip, make
>>>> 100K of each of 100 designs. This would seem to make the fab bottleneck
>>>> worse not better.
>>> <
>>> To a large first order. chip fabrication is performed in things called Boats. A boat
>>> contains 13-25 wafers. 12 or 24 of which contain chips, the other to confirm the
>>> process conditions the other wafers encountered.
>>> <
>>> A 12" wafer contains 80,000 dies of MIPS R2000 complexity, and down to a
>>> couple of hundred for GB designs such as Intel/AMD x86-64 server chips.
>>> <
>>> For smaller customers, a single wafer might be enough to provide a years worth
>>> of chips, a boat would then contain a lifetime supply.
>>> <
>>> A mask set for a 14nm die with 10 layers of metal is going to cost $10M minimum.
>>> So, it seems to me that this, in an of itself, prices most small designs out of the FAB.
>> MIPS R2000 circa 1986 was 110,000 transistors and measured 80 mm^2
>> in a 2.0 μm double-metal CMOS.
> <
> Check.
>> Looking at that list of semi fabs I see that Texas Instruments has a
>> 2000-1000 nm fab in Sherman TX, USA, Microchip 5000-350 nm in Tempe, AZ,
>> HTE Labs 4000-1000 nm in San Jose, CA.
> <
> But you don't want to implement it in 1µ or 2µ, you want to implement it in
> 20nm so the die size shrinks from 80mm^2 to 0.8mm^2 and get thousands
> of chips per wafer.

The complaint was that facilities are not available to the masses.
They are, if you don't require bleeding edge and most don't.
And the more non bleed edge you get, the more resources,
i.e. competition for your business, there is going to be.

> <
> You could probably get by with 3-4 layers of metal.

I would expect that to be cheaper too - less steps.

And 2 metal layers is probably significantly more routing work.
So yeah, 3-4 metal should be enough for low end.

>> There are other 1000+ nm fabs in China, Japan, Taiwan, Czech Republic,
>> Germany, Brazil, India, Israel, and North Korea.
> <
> If you want dozens of chips from 8" wafers, yes,
> If you want thousands of chips per 12" wafer, no.

The point is that such equipment is quite capable of turning
out commercially viable processors, as the R2000 showed,
and is available from multiple sources all over the planet.

With modern tools it should be even cheaper because the design
time is shorter and simulators help minimize errors.

And since this utilizes fab equipment has been depreciated to zero,
and you are only paying the marginal fabrication cost,
those dozens of chips should individually cost less than the thousands.

For something like a RISC-V to go into a cloud-connected toaster oven
this sounds perfect.

>>> <
>>> A design team capable of an R2000 design point is going to cost $30M (architecture,
>>> modeling, circuit design, system design, verification, manufacturing engineering,
>>> test engineering, and tester time.}
> <
>> Stanford MIPS circa 1981-82 was mostly designed by 3 guys without software
>> tools over 18 months. (The tools they mostly developed themselves.)
>> Transistor sizing was done by intuition.
>> Core design team time took 2.3 person-years.
>> Total design team size was 15 people providing specialty skills
>> at various points totaling 6.1 person-years.
> <
> So what you are saying is that modern tools SLOW DOWN the implementation process !?!

It would appear so.
Apparently we've all been grossly mislead by "Big Tool" all these years. :-)

Re: The world is running out of microchips – here’s the solution | New Scientist

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Subject: Re:_The_world_is_running_out_of_microchips_–_here
’s_the_solution_|_New_Scientist
From: MitchAl...@aol.com (MitchAlsup)
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 by: MitchAlsup - Mon, 20 Sep 2021 18:03 UTC

On Monday, September 20, 2021 at 12:32:34 PM UTC-5, EricP wrote:
> MitchAlsup wrote:
> > On Monday, September 20, 2021 at 6:39:05 AM UTC-5, EricP wrote:
> >> MitchAlsup wrote:
> >>> On Sunday, September 19, 2021 at 4:13:24 PM UTC-5, Theo Markettos wrote:
> >>>> Quadibloc <jsa...@ecn.ab.ca> wrote:
> >>>>> If chip *design* is democratized, suddenly there are more and smaller customers
> >>>>> for chip foundries. So perhaps the writer envisaged that this would create a
> >>>>> market environment that would foster the emergence of more and smaller
> >>>>> chip foundries.
> >>> <
> >>>> Surely that would go the other way. More designs = more masks = making in
> >>>> smaller batches. Assuming the number of chips being made doesn't change a
> >>>> great deal (make your own rather than buying one in) it would cause the fabs
> >>>> to become less efficient; rather than making 10 million of one chip, make
> >>>> 100K of each of 100 designs. This would seem to make the fab bottleneck
> >>>> worse not better.
> >>> <
> >>> To a large first order. chip fabrication is performed in things called Boats. A boat
> >>> contains 13-25 wafers. 12 or 24 of which contain chips, the other to confirm the
> >>> process conditions the other wafers encountered.
> >>> <
> >>> A 12" wafer contains 80,000 dies of MIPS R2000 complexity, and down to a
> >>> couple of hundred for GB designs such as Intel/AMD x86-64 server chips.
> >>> <
> >>> For smaller customers, a single wafer might be enough to provide a years worth
> >>> of chips, a boat would then contain a lifetime supply.
> >>> <
> >>> A mask set for a 14nm die with 10 layers of metal is going to cost $10M minimum.
> >>> So, it seems to me that this, in an of itself, prices most small designs out of the FAB.
> >> MIPS R2000 circa 1986 was 110,000 transistors and measured 80 mm^2
> >> in a 2.0 μm double-metal CMOS.
> > <
> > Check.
> >> Looking at that list of semi fabs I see that Texas Instruments has a
> >> 2000-1000 nm fab in Sherman TX, USA, Microchip 5000-350 nm in Tempe, AZ,
> >> HTE Labs 4000-1000 nm in San Jose, CA.
> > <
> > But you don't want to implement it in 1µ or 2µ, you want to implement it in
> > 20nm so the die size shrinks from 80mm^2 to 0.8mm^2 and get thousands
> > of chips per wafer.
> The complaint was that facilities are not available to the masses.
> They are, if you don't require bleeding edge and most don't.
<
20nm is 4 generations away from bleeding edge. it is also 1/10,00 th
the area of 2µ ±
>
> And the more non bleed edge you get, the more resources,
> i.e. competition for your business, there is going to be.
> > <
> > You could probably get by with 3-4 layers of metal.
> I would expect that to be cheaper too - less steps.
>
> And 2 metal layers is probably significantly more routing work.
> So yeah, 3-4 metal should be enough for low end.
> >> There are other 1000+ nm fabs in China, Japan, Taiwan, Czech Republic,
> >> Germany, Brazil, India, Israel, and North Korea.
> > <
> > If you want dozens of chips from 8" wafers, yes,
> > If you want thousands of chips per 12" wafer, no.
<
> The point is that such equipment is quite capable of turning
> out commercially viable processors, as the R2000 showed,
> and is available from multiple sources all over the planet.
<
Except that nobody sells the SRAMs needed by those parts anymore.
>
> With modern tools it should be even cheaper because the design
> time is shorter and simulators help minimize errors.
>
> And since this utilizes fab equipment has been depreciated to zero,
> and you are only paying the marginal fabrication cost,
> those dozens of chips should individually cost less than the thousands.
>
> For something like a RISC-V to go into a cloud-connected toaster oven
> this sounds perfect.
> >>> <
> >>> A design team capable of an R2000 design point is going to cost $30M (architecture,
> >>> modeling, circuit design, system design, verification, manufacturing engineering,
> >>> test engineering, and tester time.}
> > <
> >> Stanford MIPS circa 1981-82 was mostly designed by 3 guys without software
> >> tools over 18 months. (The tools they mostly developed themselves.)
> >> Transistor sizing was done by intuition.
> >> Core design team time took 2.3 person-years.
> >> Total design team size was 15 people providing specialty skills
> >> at various points totaling 6.1 person-years.
<
Oh, and BTW, if anyone is counting, we did 88100 with 12 people over 3 years
while learning the tools, developing the architecture, writing compilers,.......
So I do understand how little one can use to pull off a design. The 88200
(the cache chip) was done by 6 people in slightly less time.
<
On the other hand, 10 more people would have taken a year off the schedule.
7 of these would have been put on verification.
<
On the other other hand, if we had started a year later when we would have had
access to 1.25µ we would have done 64-bit implementation first........
> > <
> > So what you are saying is that modern tools SLOW DOWN the implementation process !?!
> It would appear so.
> Apparently we've all been grossly mislead by "Big Tool" all these years. :-)

Re: The world is running out of microchips – here’s the solution | New Scientist

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From: cr88...@gmail.com (BGB)
Newsgroups: comp.arch
Subject: Re:_The_world_is_running_out_of_microchips_–_he
re’s_the_solution_|_New_Scientist
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 by: BGB - Mon, 20 Sep 2021 21:27 UTC

On 9/20/2021 11:07 AM, MitchAlsup wrote:
> On Monday, September 20, 2021 at 10:03:21 AM UTC-5, Quadibloc wrote:
>> On Monday, September 20, 2021 at 12:46:11 AM UTC-6, BGB wrote:
>>
>>> Say, one uses basically about the biggest DLP module they can get in
>>> their fab, uses optics to focus it onto the wafer.
>> But if you use optics to focus the DLP on the wafer, you might as well
>> just use a mask. This may have the seed of a good idea in it, however.
> <
> There is always E-Beam lithography.
> This is how masks are made, BTW.
> The reason they don't use it in production is that it is too slow.
> A single mask takes hours on the E-beam machine, where an exposure
> using the mask takes fractions of a second. {It actually takes longer
> slewing the wafer from chip location to chip location that it does to expose
> that chip location.}

E-Beam would likely be impractically slow...

A DLP could at least be relatively fast, just seriously hindered by
resolution.

>>
>> For example, illuminate the DLP with a laser. Then, since the laser light
>> is perfectly collimated, where it will go from the DLP is predetermined,
>> except for diffraction effects.
> <
> and halation

It is possible, though AFAIK for any semblance of speed one wants to be
able to do all of the exposure at the same time, rather than have to
scan back and forth with a laser. Could work with a wide-beam laser though.

I suspect though that the weak resolution of the DLP would likely be a
bigger factor than issues due to optical artifacts though.

>>
>> John Savard

Re: The world is running out of microchips – here’s the solution | New Scientist

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Subject: Re:_The_world_is_running_out_of_microchips_–_he
re’s_the_solution_|_New_Scientist
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 by: BGB - Mon, 20 Sep 2021 21:33 UTC

On 9/20/2021 5:02 AM, Thomas Koenig wrote:
> BGB <cr88192@gmail.com> schrieb:
>
>> Granted, the big obvious limitation is that chip complexity will be
>> limited by the resolution of the DLP module, and most cinema class
>> modules are probably pretty weak by these standards.
>
> Wikipedia tells me that cinemas have around 4K resolution, so we could
> finally make that better 6502 we've been discussing, or maybe even
> a 16-bit RISC.
>

AFAIK there are some 8K modules for high-end cinemas.

But, yeah, ideally would need to figure out some way to get higher
resolution from this.

Seems like it could be possible to lay out multiple DLPs in a grid and
then use fancy optics to slightly overlap them in the final output (to
eliminate the seams).

And/or somehow get someone to manufacture some particularly gigantic DLP
modules.

Or something...

Re: The world is running out of microchips – here’s the solution | New Scientist

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Subject: Re: The world is running out of microchips – here’s the solution | New Scientist
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 by: Anton Ertl - Tue, 21 Sep 2021 06:14 UTC

EricP <ThatWouldBeTelling@thevillage.com> writes:
[old processes with big feature sizes]
>And since this utilizes fab equipment has been depreciated to zero,
>and you are only paying the marginal fabrication cost,
>those dozens of chips should individually cost less than the thousands.

If you mean that each old-process dies costs less, that is unlikely.
It's not just the equipment that costs, but the processing as well.
And much of that processing is per wafer. Admittedly, younger
processes tend to use more steps than older processes, but not by as
much a factor as the increase in die output.

Remember that Moore's law is about the number of transistors in
*lowest-cost-per-transistor* chips. If that lowest cost was at
2000nm, Moore's law would have stopped many years ago. And, e.g.,
Intel CPUs or memory chips with their exponentially increasing number
of transistors would have become similarly more expensive (unless you
suggest that the cost of the old process drops exponentially).

Old processes drop in cost, true, but at some point newer processes
tend to be cheaper per-transistor; my impression is that that point
has been relatively soon. E.g., at some point I read that Intel tends
to use older processes for making chipsets, because the performance
and power benefits of newer processes are not that important for
chipsets. But Intel has been making chipsets in 14nm for a few years,
so apparently their 14nm process can make cheaper transistors than
their older processes.

>>> Stanford MIPS circa 1981-82 was mostly designed by 3 guys without software
>>> tools over 18 months. (The tools they mostly developed themselves.)
>>> Transistor sizing was done by intuition.
>>> Core design team time took 2.3 person-years.
>>> Total design team size was 15 people providing specialty skills
>>> at various points totaling 6.1 person-years.
>> <
>> So what you are saying is that modern tools SLOW DOWN the implementation process !?!

Or one could point out that it took until 1986 until the R2000 was
released. My guess is that it took quite a bit more effort to get
from an academic proof-of-concept to a commercial product, not only on
the business side, but also on the technical side.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

Re: The world is running out of microchips – here’s the solution | New Scientist

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Subject: Re: The world is running out of microchips –
_here’s the solution | New Scientist
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 by: Thomas Koenig - Tue, 21 Sep 2021 07:54 UTC

BGB <cr88192@gmail.com> schrieb:
> On 9/20/2021 5:02 AM, Thomas Koenig wrote:
>> BGB <cr88192@gmail.com> schrieb:
>>
>>> Granted, the big obvious limitation is that chip complexity will be
>>> limited by the resolution of the DLP module, and most cinema class
>>> modules are probably pretty weak by these standards.
>>
>> Wikipedia tells me that cinemas have around 4K resolution, so we could
>> finally make that better 6502 we've been discussing, or maybe even
>> a 16-bit RISC.
>>
>
> AFAIK there are some 8K modules for high-end cinemas.
>
> But, yeah, ideally would need to figure out some way to get higher
> resolution from this.
>
> Seems like it could be possible to lay out multiple DLPs in a grid and
> then use fancy optics to slightly overlap them in the final output (to
> eliminate the seams).
>
> And/or somehow get someone to manufacture some particularly gigantic DLP
> modules.
>
> Or something...

Litography isn't all there is to making a chip.

A few decades ago, I interned at the R&D division of company
which made wafers for silicon chips. They had 10% of their
production capacity in R&D, which I found astonishing. Anyway,
the hydrofluroic acid I was handling there to etch the wafers is
a most unpleasant chemical, a powerful, slow-acting contact poison.

I would not want to see that in just any garage.

Re: The world is running out of microchips – here’s the solution | New Scientist

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From: cr88...@gmail.com (BGB)
Newsgroups: comp.arch
Subject: Re:_The_world_is_running_out_of_microchips_–_he
re’s_the_solution_|_New_Scientist
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 by: BGB - Tue, 21 Sep 2021 08:52 UTC

On 9/21/2021 2:54 AM, Thomas Koenig wrote:
> BGB <cr88192@gmail.com> schrieb:
>> On 9/20/2021 5:02 AM, Thomas Koenig wrote:
>>> BGB <cr88192@gmail.com> schrieb:
>>>
>>>> Granted, the big obvious limitation is that chip complexity will be
>>>> limited by the resolution of the DLP module, and most cinema class
>>>> modules are probably pretty weak by these standards.
>>>
>>> Wikipedia tells me that cinemas have around 4K resolution, so we could
>>> finally make that better 6502 we've been discussing, or maybe even
>>> a 16-bit RISC.
>>>
>>
>> AFAIK there are some 8K modules for high-end cinemas.
>>
>> But, yeah, ideally would need to figure out some way to get higher
>> resolution from this.
>>
>> Seems like it could be possible to lay out multiple DLPs in a grid and
>> then use fancy optics to slightly overlap them in the final output (to
>> eliminate the seams).
>>
>> And/or somehow get someone to manufacture some particularly gigantic DLP
>> modules.
>>
>> Or something...
>
> Litography isn't all there is to making a chip.
>
> A few decades ago, I interned at the R&D division of company
> which made wafers for silicon chips. They had 10% of their
> production capacity in R&D, which I found astonishing. Anyway,
> the hydrofluroic acid I was handling there to etch the wafers is
> a most unpleasant chemical, a powerful, slow-acting contact poison.
>
> I would not want to see that in just any garage.
>

From what I have seen in some videos, apparently hydroflouric acid
isn't actually all that hard to get, nor particularly uncommon (one guy
apparently having ordered bottles of the stuff off of aliexpress, *),
but still pretty dangerous in any case.

*: The guy way apparently trying to build optical logic gates built from
interference patterns via specialized glass etching.

But, yeah, I was more imagining a chip fab for short runs of low-density
parts, rather than necessarily a "someones' garage" chip fab...

Eg: If masks are a major part of the cost of doing a run of chips, one
could use DLP and then be able to run a small number of chips without
needing to make a mask, or potentially run multiple different types of
chips on the same wafer assuming the processing is otherwise compatible.

Nevermind if the logic density sucks, but if it is good enough that it
can be comparable to what is typically done on an FPGA, it could be
"good enough".

Re: The world is running out of microchips – here’s the solution | New Scientist

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From: cr88...@gmail.com (BGB)
Newsgroups: comp.arch
Subject: Re:_The_world_is_running_out_of_microchips_–_he
re’s_the_solution_|_New_Scientist
Date: Tue, 21 Sep 2021 04:23:14 -0500
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 by: BGB - Tue, 21 Sep 2021 09:23 UTC

On 9/21/2021 1:14 AM, Anton Ertl wrote:
> EricP <ThatWouldBeTelling@thevillage.com> writes:
> [old processes with big feature sizes]
>> And since this utilizes fab equipment has been depreciated to zero,
>> and you are only paying the marginal fabrication cost,
>> those dozens of chips should individually cost less than the thousands.
>
> If you mean that each old-process dies costs less, that is unlikely.
> It's not just the equipment that costs, but the processing as well.
> And much of that processing is per wafer. Admittedly, younger
> processes tend to use more steps than older processes, but not by as
> much a factor as the increase in die output.
>
> Remember that Moore's law is about the number of transistors in
> *lowest-cost-per-transistor* chips. If that lowest cost was at
> 2000nm, Moore's law would have stopped many years ago. And, e.g.,
> Intel CPUs or memory chips with their exponentially increasing number
> of transistors would have become similarly more expensive (unless you
> suggest that the cost of the old process drops exponentially).
>
> Old processes drop in cost, true, but at some point newer processes
> tend to be cheaper per-transistor; my impression is that that point
> has been relatively soon. E.g., at some point I read that Intel tends
> to use older processes for making chipsets, because the performance
> and power benefits of newer processes are not that important for
> chipsets. But Intel has been making chipsets in 14nm for a few years,
> so apparently their 14nm process can make cheaper transistors than
> their older processes.
>
>>>> Stanford MIPS circa 1981-82 was mostly designed by 3 guys without software
>>>> tools over 18 months. (The tools they mostly developed themselves.)
>>>> Transistor sizing was done by intuition.
>>>> Core design team time took 2.3 person-years.
>>>> Total design team size was 15 people providing specialty skills
>>>> at various points totaling 6.1 person-years.
>>> <
>>> So what you are saying is that modern tools SLOW DOWN the implementation process !?!
>
> Or one could point out that it took until 1986 until the R2000 was
> released. My guess is that it took quite a bit more effort to get
> from an academic proof-of-concept to a commercial product, not only on
> the business side, but also on the technical side.
>

I looked at a chart recently of transistor budget over the years, and
noted a few things:
It is still rising it seems;
Many of the "classic" ARM chips (ARM7, ARM9, ARM11, ...) were roughly a
decade behind the x86 chips in terms of transistor count;
It appears new fancy ARM chips, like the A1, have mostly caught up.

Though, the charts didn't seem to show things like the Cortex-A53 based
chips which remain common in cellphones.

Though, partly this was in the context of information gathering for a
sci-fi story I decided to write, set some decades in the future but
imagining electronics not too dissimilar from modern ones. Then noting
that, ironically, if Moore's law holds, there could be be a bit of
zeerust even with the idea of ~ 1-5 petaflop AI chips and having RAM
modules and SSDs which fit into LGA sockets (mostly thinking that it
could be possible to get considerable more bandwidth via an LGA socketed
modules than via edge connectors; mostly by allowing for a large number
of memory channels).

At first, I was thinking maybe stating a 45mm x 45mm x 5mm module
holding 16TB of non-volatile storage seemed a little absurd, but then I
realized one could achieve this density *already* simply by filling the
same volume with densely packed high-capacity microSD cards...

Then again, the story is sorta trying to be cyberpunk so a certain
amount of retro or zeerust isn't entirely out of place, and some of the
technology described thus far could be argued to be dated even by modern
standards... (or, at least when characters aren't just straight up
stated as using retro-tech, such as doing interplanetary communication
via the use of a radio teletype running at 50 baud...).

Re: The world is running out of microchips – here’s the solution | New Scientist

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Newsgroups: comp.arch
Subject: Re:_The_world_is_running_out_of_microchips_–_here
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 by: Terje Mathisen - Tue, 21 Sep 2021 12:36 UTC

Thomas Koenig wrote:
> A few decades ago, I interned at the R&D division of company
> which made wafers for silicon chips. They had 10% of their
> production capacity in R&D, which I found astonishing. Anyway,
> the hydrofluroic acid I was handling there to etch the wafers is
> a most unpleasant chemical, a powerful, slow-acting contact poison.

HF has the highest possible chemical valence (?) gap, of 4.0 from what
little I remember of my high school chemistry.

I saw a note yesterday about the semi industry promising to turn a bit
greener, including reducing both water and dangerous chemical use.

>
> I would not want to see that in just any garage.

I hope Jeri Ellsworth would have both the first and last garage to do
so: https://en.wikipedia.org/wiki/Jeri_Ellsworth

Terje

--
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"

Re: The world is running out of microchips – here’s the solution | New Scientist

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Newsgroups: comp.arch
Subject: Re:_The_world_is_running_out_of_microchips_–_he
re’s_the_solution_|_New_Scientist
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 by: Stephen Fuld - Tue, 21 Sep 2021 15:22 UTC

On 9/21/2021 1:52 AM, BGB wrote:

snip

> But, yeah, I was more imagining a chip fab for short runs of low-density
> parts, rather than necessarily a "someones' garage" chip fab...

You have a choice of lots of fabs for short runs through MOSIS.

https://www.themosisservice.com/

--
- Stephen Fuld
(e-mail address disguised to prevent spam)

Re: The world is running out of microchips – here’s the solution | New Scientist

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Subject: Re: The world is running out of microchips – here’
s the solution | New Scientist
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 by: EricP - Tue, 21 Sep 2021 15:42 UTC

Stephen Fuld wrote:
> On 9/21/2021 1:52 AM, BGB wrote:
>
> snip
>
>> But, yeah, I was more imagining a chip fab for short runs of
>> low-density parts, rather than necessarily a "someones' garage" chip
>> fab...
>
> You have a choice of lots of fabs for short runs through MOSIS.
>
> https://www.themosisservice.com/

If I understand correctly they organize ride-shares on others fabs.
They indicate
Global Foundries 180-7 nm
TSMC 350-12 nm

Since you are sharing a wafer with others, in the same boat,
the processing would have to be mostly compatible.
I don't know if they allow add and remove wafers to a boat for
certain steps but all die on the same wafer must have the same steps.
i.e. everyone gets the same layers of metal.

Also those fabs are likely state of the art, class 1, robots galore.
You are going to pay for bleeding edge equipment even if you don't need it.

Re: The world is running out of microchips – here’s the solution | New Scientist

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Newsgroups: comp.arch
Subject: Re:_The_world_is_running_out_of_microchips_–_he
re’s_the_solution_|_New_Scientist
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 by: BGB - Tue, 21 Sep 2021 16:37 UTC

On 9/21/2021 7:36 AM, Terje Mathisen wrote:
> Thomas Koenig wrote:
>> A few decades ago, I interned at the R&D division of company
>> which made wafers for silicon chips.  They had 10% of their
>> production capacity in R&D, which I found astonishing.  Anyway,
>> the hydrofluroic acid I was handling there to etch the wafers is
>> a most unpleasant chemical, a powerful, slow-acting contact poison.
>
> HF has the highest possible chemical valence (?) gap, of 4.0 from what
> little I remember of my high school chemistry.
>
> I saw a note yesterday about the semi industry promising to turn a bit
> greener, including reducing both water and dangerous chemical use.
>

Not entirely sure off-hand what some substitutes would be; not a whole
lot of stuff capable of dissolving silicon.

>>
>> I would not want to see that in just any garage.
>
> I hope Jeri Ellsworth would have both the first and last garage to do
> so: https://en.wikipedia.org/wiki/Jeri_Ellsworth
>

There are some others, from what I have seen.

> Terje
>

Re: The world is running out of microchips – here’s the solution | New Scientist

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Newsgroups: comp.arch
Subject: Re:_The_world_is_running_out_of_microchips_–_he
re’s_the_solution_|_New_Scientist
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 by: BGB - Tue, 21 Sep 2021 17:01 UTC

On 9/21/2021 10:42 AM, EricP wrote:
> Stephen Fuld wrote:
>> On 9/21/2021 1:52 AM, BGB wrote:
>>
>> snip
>>
>>> But, yeah, I was more imagining a chip fab for short runs of
>>> low-density parts, rather than necessarily a "someones' garage" chip
>>> fab...
>>
>> You have a choice of lots of fabs for short runs through MOSIS.
>>
>> https://www.themosisservice.com/
>
> If I understand correctly they organize ride-shares on others fabs.
> They indicate
>   Global Foundries 180-7 nm
>   TSMC 350-12 nm
>
> Since you are sharing a wafer with others, in the same boat,
> the processing would have to be mostly compatible.
> I don't know if they allow add and remove wafers to a boat for
> certain steps but all die on the same wafer must have the same steps.
> i.e. everyone gets the same layers of metal.
>
> Also those fabs are likely state of the art, class 1, robots galore.
> You are going to pay for bleeding edge equipment even if you don't need it.

Yeah. My idea was to try to make it cheap.

It seems like major elements are:
silicon-containing sand (fairly common);
processing said sand into silicon ingots (likely variable);
cutting ingots into wafers, polishing, ...;
doing lithography and processing steps;
...

With the relative cost of these stages depending somewhat on the purity
of silicon needed, etc. At a lower density, one could get by with lower
purity, less polishing, looser controls on environmental conditions, ...

Likewise, something like DLP would allow the masks to be done entirely
in software. Harder part being to get it up to a usable level of detail.

Though, I guess an option I didn't consider previously is that it could
still be possible to do multiple exposures.

Say:
DLP images onto one spot, flashes, moves over slightly, flashes again
(with another part of the mask), ... With a single chip containing
between, say, 1 and 64 exposures.

Seems like potentially part of this process could be achieved by
translating one of the lenses, but would require that no stray light can
shine outside of the target, and that the translation be pixel-exact.

Another possibility could also be to use multiple DLPs operating in
parallel, drawing sub-pieces and translating but also effectively
drawing the whole wafer in parallel (so, for example, 64 exposures is
sufficient to cover the entire wafer surface).

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