The Burroughs Scientific Processor employed a unique design with 17
memory banks running in parallel so that matrix multiplication could be
highly efficient; a matrix could have power-of-two dimensions, and the
required stride wouldn't cause clashes in memory accesses.

Maybe the idea doesn't really make sense, because surely it is trivial to pad
an array with an extra row and/or column if necessary.

But ignoring that for now, if one's goal is really high LINPACK scores...

from the previous discussion of odd-length memory accesses, I've come up
with some thoughts as to how such a machine would look.

Basically, I see a bus which is mostly shared between two memory
subsystems.

On the left is DRAM. The DRAM is 16 modules, each 72 bits wide, in width.

On the right is external static RAM. This is 17 modules, each 72 bits wide, in
width.

Coming out of the chip... there are 33 address buses. Except that the low-
order bits of corresponding buses on the left and right belong to the same
bus.

And, similarly, there are 33 data buses. But here the pin count is much
closer to only having 17 data buses, because only the four high-order bits
of corresponding buses on the left and right are independent and go to
separate pins on the processor.

The R/W pins are completely separate for the buses on the two sides of the
chip.

For "normal" operation - that is, computation not involving vectors - the
high-order bits of corresponding left and right buses are just passed through
the chip. The seventeenth bank of static RAM is not used.

On both sides of the CPU, ECC is employed on pairs of memory modules,
so that 16 bits of ECC are used with 128 bits of data. (The data bus lines for ECC are also separate for the left, DRAM, side and the right, static
RAM, side.)

The option exists to divide the 16-channel memory into two 8-channel
memories or four 4-channel memories. This allows programs that don't
use vectors to avoid wasting bandwith on data they won't use; instead,
more programs can run at the same time without interfering with each
other, and the memory bandwidth is employed more efficiently.

Four 4-channel memories is the maximum because 128 bits of data,
due to the ECC, is the irreducible unit, and two of those buses are needed
to provide efficient access to unaligned data.

However, the chip has ways to deal with a different memory organization
in other parts of the memory.

In the BSP mode... ECC is still 16 bits per 128 bits of data on the left side.

On the right side, it is 12 bits per 60 bits of data on the right side.

So the top four data bits are now used for ECC, and the same four bits
from the left side are routed to the seventeenth bank of memory modules
on the right side.

Twelve bits of ECC are enough for DECTED; I don't know if chipkill can
be managed that way. Maybe if the chips are 8 bits wide instead of 4
bits so there are fewer possibilities to take care of.

So on the DRAM side, the vector data is 'packed', on the static RAM
side it is unpacked into a seventeen-wide form with seventeen
independent address buses, just what's needed for BSP-style operation.

This means, though, that we need to use 60-bit floating-point.

But what if one needs greater than 64-bit floats instead of that?

Well, given that with DRAM, at least, it is most effective if one is
fetching data from 16 consecutive addresses at once... an obvious
strategy suggests itself.

Use 120 bit floats, put the first half of the float in one word, the second
half of the float in the following word, within a single memory module...

and deem the next 120 bits of memory space to be the first two words
in the next memory module over.

So the memory structure is a bit interleaved here.

Perhaps this verbal description, without diagrams, of such a complicated
setup is as clear as mud. I hope at least that Mitch Alsup can understand
it, although he may deem it to be the veriest insanity.

John Savard