The Massive Gate Simulation Instruction works as follows:

In main memory there is a InputBitArray and OutputBitArray

N can be any ammount of bits which will be stored in consecutive bytes.

BitArray = 0..N-1 bits.

There will be an A operand 64 times:

BitIndexA1..BitIndexA64

There will be an B operand 64 times:

BitIndexB1..BitIndexB64

(Alternatively a 32 operand, or 16 operand, or 8 operand version could be created if 64 is too much)

GateSelection1..GateSelection64

Gates:

G1 to G6 is and,or,xor,nand,nor,nxor
G7 is not

For G7 the B operand is ignored.

These were the input operands.

The output operand is:

BitIndexC1...BitIndexC64

So 64 output operands, should match the ammount as in A and B.

So now the instruction looks like:

GateSimulation InputBitArray, BitIndexAoperands, BitIndexBoperands, GateSelection, BitIndexCoperands, OutputBitArray

^ This is one hell of a big instruction ! ;)

The gate simulation instruction should:

Fetch all bits for operands A and all bits for operands B from InputBitArray

Fetch all gate selections

Distribute the A and B towards the gates capable of executing the selected gates. <- difficult !

Collect the output

Re-route output to OutputArray using BitIndexC operand.

Pascal pseudo code:

for Operand:= 0 to 63 do
begin
// load input indexes
LocalBitIndexA := OperandBitIndexA[Operand];
LocalBitIndexB := OperandBitIndexB[Operand];

// load input gate selection
LocalGateOperation := GateSelection[Operand];

// load output index
LocalBitIndexC := OperandBitIndexC[Operand];

// load input bits from input array, indexed by local input indexes a and b
LocalBitValueA := BitInputArray[LocalBitIndexA];
LocalBitValueB := BitInputArray[LocalBitIndexB];

// execute gate with a, b inputs and c output.
ExecuteGate( LocalBitValueA, LocalBitValueB, LocalGateOperation, LocalBitValueC );

// save local output to output array, via output index
BitOutputArray[LocalIndexC] := LocalBitValue
end;

The difficulty with the above code is it only executes 2 bits and produces 1 bit.

Bits could be collected and stored in 32 bit or 64 bit registers if they have the same operation.

Once one of the seven 32 bit of 64 bit registers is fully it can be executed to make room, hint don't forget to zero stuff for next run ! ;)

Code is available perhaps for a small ammount of bitcoin hehe, for this as well if interested or develop your own.

Now let's suppose you are capable of designing circuitry to run this much faster than that could be interesting.

The real question though is what is the bottleneck:

Retrieving 64 x 64 bit registers + Retrieving 64 x 64 bit registers + Retrieving 64x64 bit registers + retrieving 64x 1 bit, retrieving 64 x 1 bit, executing 64 gates and storing 64x1 bit.

I think this computation is mostly RETRIEVE-BOUND.

To accelerate this perhaps allow some kind of CACHE or special RAM ONCHIP which can store enough of these indexes and bits for faster operation.

There are some application for this:

1. Simulation of logic gates and processors and other circuitry.

2. Simulation of logic brains instead of neural brains.

Topic 2 is perhaps somewhat new and perhaps ill-explored but could become interesting in future.

This instruction could allow some more comfortable and faster research into topic 2.

Comparing neural brain vs logic gate brain.

Neural brain can work on 8 bit, 16 bit, 32 bit or 64 bit quantities.

Logic gate brain only works on 2to1 bit quantities and has major drawback of requiring most likely more logic gates to simulate what a neural brain can do.

However perhaps logic gate brains can work more exact and reliably than neural brains.

Because of the large quantities of logic gates necessary it would be diserable to simulate this faster in hardware/circuits.

Bye for now,
Skybuck.

On Wednesday, December 29, 2021 at 11:44:49 AM UTC+1, skybuck2000 wrote:
> The Massive Gate Simulation Instruction works as follows:
>
> In main memory there is a InputBitArray and OutputBitArray
>
> N can be any ammount of bits which will be stored in consecutive bytes.
>
> BitArray = 0..N-1 bits.
>
> There will be an A operand 64 times:
>
> BitIndexA1..BitIndexA64
>
> There will be an B operand 64 times:
>
> BitIndexB1..BitIndexB64
>
> (Alternatively a 32 operand, or 16 operand, or 8 operand version could be created if 64 is too much)
>
> GateSelection1..GateSelection64
>
> Gates:
>
> G1 to G6 is and,or,xor,nand,nor,nxor
> G7 is not
>
> For G7 the B operand is ignored.
>
> These were the input operands.
>
> The output operand is:
>
> BitIndexC1...BitIndexC64
>
> So 64 output operands, should match the ammount as in A and B.
>
> So now the instruction looks like:
>
> GateSimulation InputBitArray, BitIndexAoperands, BitIndexBoperands, GateSelection, BitIndexCoperands, OutputBitArray
>
> ^ This is one hell of a big instruction ! ;)
>
> The gate simulation instruction should:
>
> Fetch all bits for operands A and all bits for operands B from InputBitArray
>
> Fetch all gate selections
>
> Distribute the A and B towards the gates capable of executing the selected gates. <- difficult !
>
> Collect the output
>
> Re-route output to OutputArray using BitIndexC operand.
>
> Pascal pseudo code:
>
> for Operand:= 0 to 63 do
> begin
> // load input indexes
> LocalBitIndexA := OperandBitIndexA[Operand];
> LocalBitIndexB := OperandBitIndexB[Operand];
>
> // load input gate selection
> LocalGateOperation := GateSelection[Operand];
>
> // load output index
> LocalBitIndexC := OperandBitIndexC[Operand];
>
> // load input bits from input array, indexed by local input indexes a and b
> LocalBitValueA := BitInputArray[LocalBitIndexA];
> LocalBitValueB := BitInputArray[LocalBitIndexB];
>
> // execute gate with a, b inputs and c output.
> ExecuteGate( LocalBitValueA, LocalBitValueB, LocalGateOperation, LocalBitValueC );
>
> // save local output to output array, via output index
> BitOutputArray[LocalIndexC] := LocalBitValueC

^ forgot the C in the end ! ;)
> end;
>
> The difficulty with the above code is it only executes 2 bits and produces 1 bit.
>
> Bits could be collected and stored in 32 bit or 64 bit registers if they have the same operation.
>
> Once one of the seven 32 bit of 64 bit registers is fully it can be executed to make room, hint don't forget to zero stuff for next run ! ;)
>
> Code is available perhaps for a small ammount of bitcoin hehe, for this as well if interested or develop your own.
>
> Now let's suppose you are capable of designing circuitry to run this much faster than that could be interesting.
>
> The real question though is what is the bottleneck:
>
> Retrieving 64 x 64 bit registers + Retrieving 64 x 64 bit registers + Retrieving 64x64 bit registers + retrieving 64x 1 bit, retrieving 64 x 1 bit, executing 64 gates and storing 64x1 bit.
>
> I think this computation is mostly RETRIEVE-BOUND.
>
> To accelerate this perhaps allow some kind of CACHE or special RAM ONCHIP which can store enough of these indexes and bits for faster operation.
>
> There are some application for this:
>
> 1. Simulation of logic gates and processors and other circuitry.
>
> 2. Simulation of logic brains instead of neural brains.
>
> Topic 2 is perhaps somewhat new and perhaps ill-explored but could become interesting in future.
>
> This instruction could allow some more comfortable and faster research into topic 2.
>
> Comparing neural brain vs logic gate brain.
>
> Neural brain can work on 8 bit, 16 bit, 32 bit or 64 bit quantities.
>
> Logic gate brain only works on 2to1 bit quantities and has major drawback of requiring most likely more logic gates to simulate what a neural brain can do.
>
> However perhaps logic gate brains can work more exact and reliably than neural brains.
>
> Because of the large quantities of logic gates necessary it would be diserable to simulate this faster in hardware/circuits.
>
> Bye for now,
> Skybuck.