The "computer of the future" thread of Feb. 15: https://groups.google.com/g/comp.arch/c/R_lTDgkHdlA
started a line of thought that now has a name:
programmable packet processor
The line of thought combined several "goals":
What to do with register files having registers of more than 512 bits?
Is there a path for a direct assualt on the parallel programming problem?
Examine "computer of the future" from way "outside of the box"?

Some interesting approximate coincidences:
Time span of a 512-bit to 15Kb packet is ~ tens of nanoseconds for a 100GHz fiber speed, for DRAM access time and for a 3GHz pipeline rate on 64-bit data. It is also within reach of a wide FPGA buss (250-500 MHz clock rate).

The conclusion is that a unification of communication and computation is possible. With a packet of ~4k bits as the register size, both data and instructions could be arranged in such chunks, with the internal fragmentation being ignored or considered unimportant.

The remaining question is: how will such and architecture affect the parallel programming problem, that is the difficulty of utilizing high levels of parallel computational units. Again, think out of the box: computation is distributed among thousands of packet processors. Some processors will be memory oriented, some will be computational. There can be great diversity in computational facilities (think hundreds or thousands of distinct ISAs)?

The world wide web doing more than web page servers?

On Tuesday, April 5, 2022 at 1:29:40 PM UTC-5, JimBrakefield wrote:
> The "computer of the future" thread of Feb. 15: https://groups.google.com/g/comp.arch/c/R_lTDgkHdlA
> started a line of thought that now has a name:
> programmable packet processor
> The line of thought combined several "goals":
> What to do with register files having registers of more than 512 bits?
> Is there a path for a direct assualt on the parallel programming problem?
> Examine "computer of the future" from way "outside of the box"?
>
> Some interesting approximate coincidences:
> Time span of a 512-bit to 15Kb packet is ~ tens of nanoseconds for a 100GHz fiber speed, for DRAM access time and for a 3GHz pipeline rate on 64-bit data. It is also within reach of a wide FPGA buss (250-500 MHz clock rate)..
>
> The conclusion is that a unification of communication and computation is possible. With a packet of ~4k bits as the register size, both data and instructions could be arranged in such chunks, with the internal fragmentation being ignored or considered unimportant.
>
> The remaining question is: how will such and architecture affect the parallel programming problem, that is the difficulty of utilizing high levels of parallel computational units. Again, think out of the box: computation is distributed among thousands of packet processors. Some processors will be memory oriented, some will be computational. There can be great diversity in computational facilities (think hundreds or thousands of distinct ISAs)?
>
> The world wide web doing more than web page servers?
<
The cynic in me will state that Amdahl's Law will restrict such "matrixization" to 10× better than scalar.
<
The realist in me will state that Virtual Vector Method provides for the SIMD-width you are looking for
without costing you a register file (of any width).
<
And in any event--don't build HW that is scarcely used.