Hi,

If I use a typical I2S MEMS microphone (CMM-4030D-261-I2S for
reference), the sample width is 24 bits per the datasheet. At, say,
44100 samples/second, the required digital I2S bandwidth would then be
24*44.1e3=~1.06Mbit/s. On the other hand, the PDM variant (say,
CMM-4030DB-26354) requires clock frequency between 1 and 3.2MHz, with
the 2.4MHz recommended value. That gives 2.4Mbit/s digital bandwidth,
i.e. 226% of the I2S one. Putting aside how many of these 24 bits are
actually useful and whether these mics can provide sufficiently flat
44.1ksps frequency response: I want to implement a distributed
decimating filter for the PDM part using the I2S bandwidth. The part of
the structure close to the mic should be simple, while the complexity at
the other end of the digital link is less a concern. What decimating
filter is amenable to this kind of splitting? One obvious answer is a
complete CIC decimator at the mic end transmitting full 24-bit frames at
44.1kHz. But what if I wanted to move a significant part of the
structure to the receiver? What structure/where should I split to remain
within the I2S BW *and* maintain the accuracy of the original decimating
filter? My intuition tells me this should be doable at an early stage,
but something escapes me.

Best regards, Piotr