Or so it seems, given the list of the countries where the victims are located.

https://www.techspot.com/news/95425-years-gigabyte-asus-motherboards-carried-uefi-malware.html

Anyways, it seems obvious to me how to fix this.

Some motherboards let you flash the BIOS by inserting a thumb
drive in a given USB port on the back, so that you can do this even
if the operating system won't boot.

All that's needed is to refine this somewhat: instead of code _in_ the
BIOS performing this function, which is what malware like this would
corrupt, instead put a hardware switch on the back, and have flashing
the BIOS taken care of by code in genuine ROM.

John Savard

Quadibloc <jsavard@ecn.ab.ca> wrote:
> Or so it seems, given the list of the countries where the victims are located.
>
> https://www.techspot.com/news/95425-years-gigabyte-asus-motherboards-carried-uefi-malware.html
>
> Anyways, it seems obvious to me how to fix this.

Put virus bootloader in CPU ROM. Before starting code from
external ROM check cyptographically strong checksum. For
added security one may add on the fly encryption of RAM.
That way virus will be non-removable and non-detectable
(without messing with internal CPU wiring, which probaby
is beyond capabilities of potential targets).

--
Waldek Hebisch

Quadibloc <jsavard@ecn.ab.ca> schrieb:
> Or so it seems, given the list of the countries where the victims are located.
>
> https://www.techspot.com/news/95425-years-gigabyte-asus-motherboards-carried-uefi-malware.html

Seems like RaptorCS is onto something - a completely open system
has its advantages.

Unfortunately, Power10 shipped with a binary blob, but maybe Power11
may be better again.

Seems like we need to be able to come out of reset already running
with TLB and and other systems protections up and running at the
very first instruction executed.
<
Luckily My 66000 does exactly that.

On 7/27/2022 12:09 PM, MitchAlsup wrote:
> Seems like we need to be able to come out of reset already running
> with TLB and and other systems protections up and running at the
> very first instruction executed.
> <
> Luckily My 66000 does exactly that.

Us too. Hard to imagine any new-from-scratch design that wouldn't.

On Wednesday, July 27, 2022 at 6:20:46 PM UTC-5, Ivan Godard wrote:
> On 7/27/2022 12:09 PM, MitchAlsup wrote:
> > Seems like we need to be able to come out of reset already running
> > with TLB and and other systems protections up and running at the
> > very first instruction executed.
> > <
> > Luckily My 66000 does exactly that.
> Us too. Hard to imagine any new-from-scratch design that wouldn't.
<
RISC-V anyone ?

On 7/27/2022 4:24 PM, MitchAlsup wrote:
> On Wednesday, July 27, 2022 at 6:20:46 PM UTC-5, Ivan Godard wrote:
>> On 7/27/2022 12:09 PM, MitchAlsup wrote:
>>> Seems like we need to be able to come out of reset already running
>>> with TLB and and other systems protections up and running at the
>>> very first instruction executed.
>>> <
>>> Luckily My 66000 does exactly that.
>> Us too. Hard to imagine any new-from-scratch design that wouldn't.
> <
> RISC-V anyone ?

Inapplicable: RISCV is not new-from-scratch; it is old-from-theology.

On Wednesday, July 27, 2022 at 6:40:13 PM UTC-5, Ivan Godard wrote:
> On 7/27/2022 4:24 PM, MitchAlsup wrote:
> > On Wednesday, July 27, 2022 at 6:20:46 PM UTC-5, Ivan Godard wrote:
> >> On 7/27/2022 12:09 PM, MitchAlsup wrote:
> >>> Seems like we need to be able to come out of reset already running
> >>> with TLB and and other systems protections up and running at the
> >>> very first instruction executed.
> >>> <
> >>> Luckily My 66000 does exactly that.
> >> Us too. Hard to imagine any new-from-scratch design that wouldn't.
> > <
> > RISC-V anyone ?
<
> Inapplicable: RISCV is not new-from-scratch; it is old-from-theology.
<
ISA is new from scratch--but you can argue that the major difference
is that the OpCode is positioned at the 'other' end of the instruction
word--and other fields are moved appropriately.
<
Control register model is new from scratch--but you can argue that it
remains similar to lots of older machine control register models--and
subject to the same attack means.
<
Data-Path assumptions are from the past
Exception model is right out of MIPS
<
Use model is new in that anyone can get IP and build their own.

MitchAlsup <MitchAlsup@aol.com> schrieb:
> Seems like we need to be able to come out of reset already running
> with TLB and and other systems protections up and running at the
> very first instruction executed.
><
> Luckily My 66000 does exactly that.

Does this help if somebody manipulates the bootcode (as in
this case)?

On Thursday, July 28, 2022 at 3:24:28 AM UTC+3, MitchAlsup wrote:
> On Wednesday, July 27, 2022 at 6:40:13 PM UTC-5, Ivan Godard wrote:
> > On 7/27/2022 4:24 PM, MitchAlsup wrote:
> > > On Wednesday, July 27, 2022 at 6:20:46 PM UTC-5, Ivan Godard wrote:
> > >> On 7/27/2022 12:09 PM, MitchAlsup wrote:
> > >>> Seems like we need to be able to come out of reset already running
> > >>> with TLB and and other systems protections up and running at the
> > >>> very first instruction executed.
> > >>> <
> > >>> Luckily My 66000 does exactly that.
> > >> Us too. Hard to imagine any new-from-scratch design that wouldn't.
> > > <
> > > RISC-V anyone ?
> <
> > Inapplicable: RISCV is not new-from-scratch; it is old-from-theology.
> <
> ISA is new from scratch--but you can argue that the major difference
> is that the OpCode is positioned at the 'other' end of the instruction
> word--and other fields are moved appropriately.
> <
> Control register model is new from scratch--but you can argue that it
> remains similar to lots of older machine control register models--and
> subject to the same attack means.
> <
> Data-Path assumptions are from the past
> Exception model is right out of MIPS
> <
> Use model is new in that anyone can get IP and build their own.

IANAL
W.r.t. user-mode ISA it is not different from SPARC.
For system part, it's probably different from SPARC of 80s and 90s,
but not different from SPARC of mid 2000s (OpenSPARC era).
I am not sure what happened after Oracle acquisition.

IANAL
For last decade, POWER follows more or less the same model, if not
in legal theory then at least in practice.

IANAL
IANAL
IANAL

On Thursday, July 28, 2022 at 3:24:28 AM UTC+3, MitchAlsup wrote:
> On Wednesday, July 27, 2022 at 6:40:13 PM UTC-5, Ivan Godard wrote:
> > On 7/27/2022 4:24 PM, MitchAlsup wrote:
> > > On Wednesday, July 27, 2022 at 6:20:46 PM UTC-5, Ivan Godard wrote:
> > >> On 7/27/2022 12:09 PM, MitchAlsup wrote:
> > >>> Seems like we need to be able to come out of reset already running
> > >>> with TLB and and other systems protections up and running at the
> > >>> very first instruction executed.
> > >>> <
> > >>> Luckily My 66000 does exactly that.
> > >> Us too. Hard to imagine any new-from-scratch design that wouldn't.
> > > <
> > > RISC-V anyone ?
> <
> > Inapplicable: RISCV is not new-from-scratch; it is old-from-theology.
> <
> ISA is new from scratch--but you can argue that the major difference
> is that the OpCode is positioned at the 'other' end of the instruction
> word--and other fields are moved appropriately.

That is, if we compare to MIPS.
If we consider Altera Nios2 as immediate predecessor then the difference
is even slimmer.

Nios2:
I-type
bits[31:27] RegA
bits[26:22] RegB
bits[21:6] Imm16
bits[5:0] OP

J-type
bits[31:6] RegA
bits[5:0] OP

R-type
bits[31:27] RegA
bits[26:22] RegB
bits[21:17] RegC
bits[16:6] OPX
bits[5:0] OP (=0x3A)

RISC-V
R-format
bits[31:25] func7
bits[24:20] Rs2
bits[19:15] Rs1
bits[14:12] func3
bits[11:17] Rd
bits[6:0] OP (=0x33)

I-format
bits[31:20] imm12
bits[19:15] Rs1
bits[14:12] func3
bits[11:17] Rd
bits[6:0] OP

S/SB-format
bits[31:25] imm12_hi/imm12_rot_hi
bits[24:20] Rs2
bits[19:15] Rs1
bits[14:12] imm12_lo/imm12_rot_lo
bits[11:17] Rd
bits[6:0] OP

U/UJ-format
bits[31:12] imm20/imm20_shuff
bits[11:17] Rd
bits[6:0] OP

Michael S <already5chosen@yahoo.com> schrieb:
> On Thursday, July 28, 2022 at 3:24:28 AM UTC+3, MitchAlsup wrote:

>> Use model is new in that anyone can get IP and build their own.

[...]

> IANAL
> For last decade, POWER follows more or less the same model, if not
> in legal theory then at least in practice.

The Power ISA is indeed open, anybody can design a POWER-compatible
chip if they so desire (or modify Microwatt).

Since the 3.1 version of the ISA, they are also doing subsets,
but in a much more sane way than RISC-V (although that is
not saying much).