It was designed at the turn of the century, apparently influenced by
Itanium and Transmeta. It's described as a 512-bit wide VLIW, with
software to JIT x86 code into its own instruction set, like Transmeta's
Crusoe. It's Russian, designed at the Moscow Centre of SPARC Technology,
although it has little to do with SPARC architecture.

It seems unlikely to me that this approach would run fast, given the
failures of Transmeta and Itanium, but I'm curious if anyone here knows
much about it.

John

On Friday, August 19, 2022 at 2:43:45 PM UTC-5, John Dallman wrote:
> It was designed at the turn of the century, apparently influenced by
> Itanium and Transmeta. It's described as a 512-bit wide VLIW, with
> software to JIT x86 code into its own instruction set, like Transmeta's
> Crusoe. It's Russian, designed at the Moscow Centre of SPARC Technology,
> although it has little to do with SPARC architecture.
>
> It seems unlikely to me that this approach would run fast, given the
> failures of Transmeta and Itanium, but I'm curious if anyone here knows
> much about it.
>
> John
<
I saw some of its interior.
<
The 20-port register file was a turn-off (circa 2003)
In my opinion::
The forwarding logic would have taken more than 1 cycle

On 8/19/2022 12:50 PM, MitchAlsup wrote:
> On Friday, August 19, 2022 at 2:43:45 PM UTC-5, John Dallman wrote:
>> It was designed at the turn of the century, apparently influenced by
>> Itanium and Transmeta. It's described as a 512-bit wide VLIW, with
>> software to JIT x86 code into its own instruction set, like Transmeta's
>> Crusoe. It's Russian, designed at the Moscow Centre of SPARC Technology,
>> although it has little to do with SPARC architecture.
>>
>> It seems unlikely to me that this approach would run fast, given the
>> failures of Transmeta and Itanium, but I'm curious if anyone here knows
>> much about it.
>>
>> John
> <
> I saw some of its interior.
> <
> The 20-port register file was a turn-off (circa 2003)
> In my opinion::
> The forwarding logic would have taken more than 1 cycle

Agreed about 20-way forwarding, unless you go for cascaded. I was a
little surprised that nobody had done cascade before we patented it.

Ivan Godard <ivan@millcomputing.com> schrieb:
> On 8/19/2022 12:50 PM, MitchAlsup wrote:
>> On Friday, August 19, 2022 at 2:43:45 PM UTC-5, John Dallman wrote:
>>> It was designed at the turn of the century, apparently influenced by
>>> Itanium and Transmeta. It's described as a 512-bit wide VLIW, with
>>> software to JIT x86 code into its own instruction set, like Transmeta's
>>> Crusoe. It's Russian, designed at the Moscow Centre of SPARC Technology,
>>> although it has little to do with SPARC architecture.
>>>
>>> It seems unlikely to me that this approach would run fast, given the
>>> failures of Transmeta and Itanium, but I'm curious if anyone here knows
>>> much about it.
>>>
>>> John
>> <
>> I saw some of its interior.
>> <
>> The 20-port register file was a turn-off (circa 2003)
>> In my opinion::
>> The forwarding logic would have taken more than 1 cycle
>
> Agreed about 20-way forwarding, unless you go for cascaded. I was a
> little surprised that nobody had done cascade before we patented it.

Would you mind sharing the nunber for that patent? I'm sure that would
make interesting reading (or as interesting as a patent ever can be).

On 8/19/2022 3:29 PM, Thomas Koenig wrote:
> Ivan Godard <ivan@millcomputing.com> schrieb:
>> On 8/19/2022 12:50 PM, MitchAlsup wrote:
>>> On Friday, August 19, 2022 at 2:43:45 PM UTC-5, John Dallman wrote:
>>>> It was designed at the turn of the century, apparently influenced by
>>>> Itanium and Transmeta. It's described as a 512-bit wide VLIW, with
>>>> software to JIT x86 code into its own instruction set, like Transmeta's
>>>> Crusoe. It's Russian, designed at the Moscow Centre of SPARC Technology,
>>>> although it has little to do with SPARC architecture.
>>>>
>>>> It seems unlikely to me that this approach would run fast, given the
>>>> failures of Transmeta and Itanium, but I'm curious if anyone here knows
>>>> much about it.
>>>>
>>>> John
>>> <
>>> I saw some of its interior.
>>> <
>>> The 20-port register file was a turn-off (circa 2003)
>>> In my opinion::
>>> The forwarding logic would have taken more than 1 cycle
>>
>> Agreed about 20-way forwarding, unless you go for cascaded. I was a
>> little surprised that nobody had done cascade before we patented it.
>
> Would you mind sharing the nunber for that patent? I'm sure that would
> make interesting reading (or as interesting as a patent ever can be).

It's on our website millcomputing.com.
TL;DR: there are direct paths for all the one-cycle ops, which can be
one per slot. Longer ops (mul for example) first select down to three,
and the three compete with the one-cycles'. So it's (for example)
((17->3)+ 8)->1. There's nearly always leftover time in the last stage
of a multicycle op to fit the first stage of the cascade; the gates to
select among the one-cycle drops (plus the 3) constrains either the
gates-per-stage or the number of one-cycle slots. Why 3, not one?
because we do our pick operation (C's ?: operation) in the crossbar, and
that needs three inputs.

On Friday, August 19, 2022 at 10:43:45 PM UTC+3, John Dallman wrote:
> It was designed at the turn of the century, apparently influenced by
> Itanium and Transmeta.

I'd guess, influence of Transmeta was secondary and of Itanium close to none.
The main influence was Elbrus-3.

> It's described as a 512-bit wide VLIW, with
> software to JIT x86 code into its own instruction set, like Transmeta's
> Crusoe. It's Russian, designed at the Moscow Centre of SPARC Technology,
> although it has little to do with SPARC architecture.
>
> It seems unlikely to me that this approach would run fast, given the
> failures of Transmeta and Itanium, but I'm curious if anyone here knows
> much about it.
>
> John