Here is a (probably incomplete) list of operations which would
require more than three registers on a load/store machine
(however these are implemented, with condition flags, split
instructions, Mitch's CARRY instruction, or any other way).
I am also leaving out load/store instructions.

Integer Addition with carry:
(carry_out, res) = (a + b + carry_in)

More generally, integer three - way addition:
(carry_out, res) = (a + b + c)

Integer multiplication:
(high, low) = a * b

Integer multiply + add:
(high, low) = a * b + c

Select:
res = cond ? a : b

or, related, bit selction:
res = (a & mask) | (b & ~mask)

Bit insertion:
This can be quite complex, one example could be
a<a_from,a_from+len-1> = b<b_from,b_from+len-1>

Floating point multiply + add:
res = a*b + c

The new IEEE augmented operations:

(high, low) = a + b

What else?

On 8/21/2022 2:02 AM, Thomas Koenig wrote:
> Here is a (probably incomplete) list of operations which would
> require more than three registers on a load/store machine
> (however these are implemented, with condition flags, split
> instructions, Mitch's CARRY instruction, or any other way).
> I am also leaving out load/store instructions.
>
> Integer Addition with carry:
> (carry_out, res) = (a + b + carry_in)
>
> More generally, integer three - way addition:
> (carry_out, res) = (a + b + c)
>
> Integer multiplication:
> (high, low) = a * b
>
> Integer multiply + add:
> (high, low) = a * b + c
>
> Select:
> res = cond ? a : b
>
> or, related, bit selction:
> res = (a & mask) | (b & ~mask)
>
> Bit insertion:
> This can be quite complex, one example could be
> a<a_from,a_from+len-1> = b<b_from,b_from+len-1>
>
> Floating point multiply + add:
> res = a*b + c
>
> The new IEEE augmented operations:
>
> (high, low) = a + b
>
> What else?

Dynamic bit field select: res = a[b..c] where b and c are bit indices
into a scalar

divrem: q,r = a/b

SIMD compose: S = {a,b,c...}
SIMD decompose: {a,b,c,...} = S

bound: res = a < b ? b : a > c ? c : a
bound check: res = (a < b) | a > c) ? !@@#$ : a

On Sunday, August 21, 2022 at 5:02:55 AM UTC-4, Thomas Koenig wrote:
> Here is a (probably incomplete) list of operations which would
> require more than three registers on a load/store machine
> (however these are implemented, with condition flags, split
> instructions, Mitch's CARRY instruction, or any other way).
> I am also leaving out load/store instructions.
>
> Integer Addition with carry:
> (carry_out, res) = (a + b + carry_in)
>
> More generally, integer three - way addition:
> (carry_out, res) = (a + b + c)
>
> Integer multiplication:
> (high, low) = a * b
>
> Integer multiply + add:
> (high, low) = a * b + c
>
> Select:
> res = cond ? a : b
>
> or, related, bit selction:
> res = (a & mask) | (b & ~mask)
>
> Bit insertion:
> This can be quite complex, one example could be
> a<a_from,a_from+len-1> = b<b_from,b_from+len-1>
>
> Floating point multiply + add:
> res = a*b + c
>
> The new IEEE augmented operations:
>
> (high, low) = a + b
>
> What else?

Fused dot product: (a * b) + (c * d)
I believe there are some crypto functions that could use three arguments.
Some graphics operations: color blend, point transform

Minimum and maximum of three values.
Majority logic eval

Thomas Koenig <tkoenig@netcologne.de> writes:
>Here is a (probably incomplete) list of operations which would
>require more than three registers on a load/store machine
>(however these are implemented, with condition flags, split
>instructions, Mitch's CARRY instruction, or any other way).
>I am also leaving out load/store instructions.
>
>Integer Addition with carry:
>(carry_out, res) = (a + b + carry_in)

Can be covered with a 65th bit, as discussed earlier
<2021Mar10.110220@mips.complang.tuwien.ac.at> ff. That would mean
that you would have either

res=a+b
res=res carry+ c

or a three-operand

res = a + b carry+ c

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

On Sunday, August 21, 2022 at 4:02:55 AM UTC-5, Thomas Koenig wrote:
> Here is a (probably incomplete) list of operations which would
> require more than three registers on a load/store machine
> (however these are implemented, with condition flags, split
> instructions, Mitch's CARRY instruction, or any other way).
> I am also leaving out load/store instructions.
>
> Integer Addition with carry:
> (carry_out, res) = (a + b + carry_in)
<
; Rcarry contains carry_in
CARRY Rcarry,{{IO}}
ADD Rd,Ra,Rb
; Rcarry contains carry_out
>
> More generally, integer three - way addition:
> (carry_out, res) = (a + b + c)
>
> Integer multiplication:
> (high, low) = a * b
<
CARRY Rhigh,{{O}}
MUL Rlow,Rs,Rb
>
> Integer multiply + add:
> (high, low) = a * b + c
<
CARRY Rc,{{IO}}
MUL Rlow,Rs,Rb
>
>
> Select:
> res = cond ? a : b
<
depending on how cond is evaluated, CMOV or MUX; typically:
<
CMOV Rres,Ra,Rb,Rcond
>
> or, related, bit selction:
> res = (a & mask) | (b & ~mask)
<
This is MUX
>
> Bit insertion:
> This can be quite complex, one example could be
> a<a_from,a_from+len-1> = b<b_from,b_from+len-1>
<
INS Ra,Ra,Rbits,field_def
<
A constant field_def is written <length:offset>
>
> Floating point multiply + add:
> res = a*b + c
<
FMAC Rres,Ra,Rb,Rc
>
> The new IEEE augmented operations:
>
> (high, low) = a + b
<
CARRY Rlow,{{O}}
FADD Rhigh,Ra,Rb
>
> What else?

Thomas Koenig wrote:
> Here is a (probably incomplete) list of operations which would
> require more than three registers on a load/store machine
[snip]
> Integer multiply + add:
> (high, low) = a * b + c

Variable shift and add would merely be a strength reduced version
of MADD (probably with limited utility). Shift and [logical
operation] seems even less likely to be broadly useful.

In the original ARM instruction set any instruction can specify four registers. You can write something like

adds r2, r5, r1, LSL r3

meaning

r2 = r5 + ( r1 << r3 ) and update the status bits

-- Jecel

On Tuesday, August 23, 2022 at 9:10:25 PM UTC-5, je...@merlintec.com wrote:
> In the original ARM instruction set any instruction can specify four registers. You can write something like
>
> adds r2, r5, r1, LSL r3
>
> meaning
>
> r2 = r5 + ( r1 << r3 ) and update the status bits
>
> -- Jecel
<
We quit "anointing" this stuff when we realized the << takes at least
as much gate-delays as +, so either it takes 2 pipe stages, or the
whole machine runs slow.

On Wednesday, August 24, 2022 at 1:20:40 PM UTC-3, MitchAlsup wrote:
> On Tuesday, August 23, 2022 at 9:10:25 PM UTC-5, Jecel wrote:
> > In the original ARM instruction set any instruction can specify four registers. You can write something like
> >
> > adds r2, r5, r1, LSL r3
> >
> > meaning
> >
> > r2 = r5 + ( r1 << r3 ) and update the status bits
> >
> > -- Jecel
> <
> We quit "anointing" this stuff when we realized the << takes at least
> as much gate-delays as +, so either it takes 2 pipe stages, or the
> whole machine runs slow.

Like branch delay slots, this was one of the ideas that looked cute at the time but which made life more complicated for future implementers. I tried to look up if this had been abandoned in Aarch64 or not but gave up after running into too much vague documentation. I do know that conditional execution of all instructions was removed. Having the PC be a normal register was also eliminated.

My point was that being able to specify four registers in general was considered interesting in at least one commercial processor.

-- Jecel

On Saturday, August 27, 2022 at 4:08:31 AM UTC+3, je...@merlintec.com wrote:
> On Wednesday, August 24, 2022 at 1:20:40 PM UTC-3, MitchAlsup wrote:
> > On Tuesday, August 23, 2022 at 9:10:25 PM UTC-5, Jecel wrote:
> > > In the original ARM instruction set any instruction can specify four registers. You can write something like
> > >
> > > adds r2, r5, r1, LSL r3
> > >
> > > meaning
> > >
> > > r2 = r5 + ( r1 << r3 ) and update the status bits
> > >
> > > -- Jecel
> > <
> > We quit "anointing" this stuff when we realized the << takes at least
> > as much gate-delays as +, so either it takes 2 pipe stages, or the
> > whole machine runs slow.
> Like branch delay slots, this was one of the ideas that looked cute at the time but which made life more complicated for future implementers. I tried to look up if this had been abandoned in Aarch64 or not but gave up after running into too much vague documentation. I do know that conditional execution of all instructions was removed. Having the PC be a normal register was also eliminated.

I find "ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile"
quite clear/well written.
Left shift by Immediate count is here for all common reg--to-reg arithmetic and
logic operations.
Shift by count in register is gone except, of course, in dedicate shift instructions.

>
> My point was that being able to specify four registers in general was considered interesting in at least one commercial processor.
>

Helped by having 32-bit instructions, but only 16 GPRs. And by lack of experience.
Considering the later, end result was astonishingly good. But not without faults.

> -- Jecel

On 8/26/2022 8:08 PM, Jecel Assumpção Jr wrote:
> On Wednesday, August 24, 2022 at 1:20:40 PM UTC-3, MitchAlsup wrote:
>> On Tuesday, August 23, 2022 at 9:10:25 PM UTC-5, Jecel wrote:
>>> In the original ARM instruction set any instruction can specify four registers. You can write something like
>>>
>>> adds r2, r5, r1, LSL r3
>>>
>>> meaning
>>>
>>> r2 = r5 + ( r1 << r3 ) and update the status bits
>>>
>>> -- Jecel
>> <
>> We quit "anointing" this stuff when we realized the << takes at least
>> as much gate-delays as +, so either it takes 2 pipe stages, or the
>> whole machine runs slow.
>
> Like branch delay slots, this was one of the ideas that looked cute at the time but which made life more complicated for future implementers. I tried to look up if this had been abandoned in Aarch64 or not but gave up after running into too much vague documentation. I do know that conditional execution of all instructions was removed. Having the PC be a normal register was also eliminated.
>

Yes. One can also observe that a lot of the ARM based soft-core
processors tend to have lower clock speeds than those for some other ISAs.

The implicit shift and full condition-code predication are very possibly
some of the cause of this.

Also, one spends 12-bits on a "clever" shifted-constant representation
that manages to be less effective on average than a 12-bit integer would
have been.

And, a 4-bit register field which effectively loses 5 of the registers
(4 to the hardware, one to the OS), isn't ideal either.

Being able to encode PC is sometimes useful, but probably not enough to
burn a register.

Possible cases where it is useful:
PC relative Load/Store;
If one encodes register-branch or RTS by overloading MOV;
...

Though, there are other ways to approach these:
Dedicated encodings;
Only certain registers are special in specific contexts;
...

> My point was that being able to specify four registers in general was considered interesting in at least one commercial processor.
>
> -- Jecel