I have been wondering for some time what a RICS machine would
have looked like implemented only with standard TTL chips, and
what impact it would have had had it been released in the late
1970s instead of, or in competition with, the VAX.

I've now found the answer to the first question. HP first released
its HP-PA architecture with a CPU made from MSI TTL chips, described
in https://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1987-03.pdf ,
first shipping its HP 3000/930 in 1986. Its CPU had six printed
circuit boards, running at 8 MHz, and performing around 4-5 million
of its own instructions per second.

Such a machine (with smaller caches, probably) in 1978 would have
been entirely possible, and would have outperformed the VAX by a
reasonable factor, leading to a less CISC-y microprocessor world.

On Sunday, October 16, 2022 at 8:08:26 AM UTC-5, Thomas Koenig wrote:
> I have been wondering for some time what a RICS machine would
> have looked like implemented only with standard TTL chips, and
> what impact it would have had had it been released in the late
> 1970s instead of, or in competition with, the VAX.
>
> I've now found the answer to the first question. HP first released
> its HP-PA architecture with a CPU made from MSI TTL chips, described
> in https://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1987-03.pdf ,
> first shipping its HP 3000/930 in 1986. Its CPU had six printed
> circuit boards, running at 8 MHz, and performing around 4-5 million
> of its own instructions per second.
<
The 1st generation of RISC machines used SAMs (for caches) that
ran 2× the pipeline stage delay.
<
This HP design used SRAMs that were 5× and 4× as fast as the
pipeline itself. The pipeline used would have 2× as many stages
in a modern design.
>
> Such a machine (with smaller caches, probably) in 1978 would have
> been entirely possible, and would have outperformed the VAX by a
> reasonable factor, leading to a less CISC-y microprocessor world.
<
DEC would still have had an advantage in caché if nothing else.
And with the TTL available in 1978 it is not clear that HP would have
had "that much" of a performance advantage.
<
Whether (or not) this would have lead to a less CISCy future is
entirely unclear, as x86 was already here and PCs were too. The
only thing (I can see) that would have altered the course of history
is a price structure competitive with PCs. Neither VAX not HP would
have fit in that space. Perhaps HP could have out-competed VAX
11/780 in the time sharing (back room) space, but workstations
were already making inroads and soon lead to everyone having
a computer on their desk.

Thomas Koenig <tkoenig@netcologne.de> wrote:
> I've now found the answer to the first question. HP first released
> its HP-PA architecture with a CPU made from MSI TTL chips, described
> in https://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1987-03.pdf ,
> first shipping its HP 3000/930 in 1986. Its CPU had six printed
> circuit boards, running at 8 MHz, and performing around 4-5 million
> of its own instructions per second.

That's interesting. It feels like a nice hobbyist project for somebody to
try today...

> Such a machine (with smaller caches, probably) in 1978 would have
> been entirely possible, and would have outperformed the VAX by a
> reasonable factor, leading to a less CISC-y microprocessor world.

Surely the enabler for the 'RISC revolution' was falling memory costs, which
enabled RISC's less-dense machine code and thus a simpler, faster CPU? I'm
not sure you'd get very far with a RISC CPU at 1978 DRAM prices.

Theo

On Sunday, October 16, 2022 at 11:19:11 AM UTC-5, Theo wrote:
> Thomas Koenig <tko...@netcologne.de> wrote:
> > I've now found the answer to the first question. HP first released
> > its HP-PA architecture with a CPU made from MSI TTL chips, described
> > in https://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1987-03.pdf ,
> > first shipping its HP 3000/930 in 1986. Its CPU had six printed
> > circuit boards, running at 8 MHz, and performing around 4-5 million
> > of its own instructions per second.
> That's interesting. It feels like a nice hobbyist project for somebody to
> try today...
> > Such a machine (with smaller caches, probably) in 1978 would have
> > been entirely possible, and would have outperformed the VAX by a
> > reasonable factor, leading to a less CISC-y microprocessor world.
<
> Surely the enabler for the 'RISC revolution' was falling memory costs, which
> enabled RISC's less-dense machine code and thus a simpler, faster CPU? I'm
> not sure you'd get very far with a RISC CPU at 1978 DRAM prices.
<
As I saw it::
<
The enabler for RISC 1st generation was the ability to put a whole 32-bit
pipelined data path on a single chip -- combined with the inability to put
a CISC ISA microcode control engine on the same chip.
<
Falling SRAM prices may have helped, but were not that big a contributing
factor.
>
> Theo

MitchAlsup <MitchAlsup@aol.com> schrieb:
> On Sunday, October 16, 2022 at 11:19:11 AM UTC-5, Theo wrote:
>> Thomas Koenig <tko...@netcologne.de> wrote:
>> > I've now found the answer to the first question. HP first released
>> > its HP-PA architecture with a CPU made from MSI TTL chips, described
>> > in https://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1987-03.pdf ,
>> > first shipping its HP 3000/930 in 1986. Its CPU had six printed
>> > circuit boards, running at 8 MHz, and performing around 4-5 million
>> > of its own instructions per second.
>> That's interesting. It feels like a nice hobbyist project for somebody to
>> try today...
>> > Such a machine (with smaller caches, probably) in 1978 would have
>> > been entirely possible, and would have outperformed the VAX by a
>> > reasonable factor, leading to a less CISC-y microprocessor world.
><
>> Surely the enabler for the 'RISC revolution' was falling memory costs, which
>> enabled RISC's less-dense machine code and thus a simpler, faster CPU? I'm
>> not sure you'd get very far with a RISC CPU at 1978 DRAM prices.
><
> As I saw it::
><
> The enabler for RISC 1st generation was the ability to put a whole 32-bit
> pipelined data path on a single chip -- combined with the inability to put
> a CISC ISA microcode control engine on the same chip.

Neither the 801 nor the first HP-PA implementations were single-chip
implementations, and yet they had performance advantages over their
CISCy relations implemented with a similar technology.

Does that make them 0th generation RISC?

> Falling SRAM prices may have helped, but were not that big a contributing
> factor.

Paradoxically enough, falling RAM prices first enabled, then
helped destroy the minis. Once you had performance _and_ memory
on a workstation matching the expensive mini, why buy the expensive
mini?

MitchAlsup <MitchAlsup@aol.com> writes:
>DEC would still have had an advantage in cach=C3=A9 if nothing else.
>And with the TTL available in 1978 it is not clear that HP would have
>had "that much" of a performance advantage.

The RISC would have benefited from the pipelining advantage. The VAX
ran at 5MHz with 10 cycles per instruction on average. Would a RISC
in the same technology have a significantly slower clock?

Concerning the "advantage in cache": I expect that the RISC would have
outperformed the VAX even without cache: The Nova 800 had
semiconductor memory with 800ns cycle time in 1971. So a RISC could
have run at at least 1.25MHz (the ARM1 ran at 6MHz without cache in
1985). Assuming a CPI of 1.25, the VAX would have needed to reduce
the instructions by a factor of 2 with it's CISC features, and AFAIK
it did not.

>Whether (or not) this would have lead to a less CISCy future is
>entirely unclear, as x86 was already here and PCs were too. The
>only thing (I can see) that would have altered the course of history
>is a price structure competitive with PCs.

But such a RISC would needed a too-expensive system compared to PCs,
because it would have needed a 32-bit memory interface; and of course
the CPU itself would have been far too expensive in TTL.

But there was a RISC around at the time: the IBM 801 (well, first
implementation in 1980, and it was in ECL, not TTL). But it seems
that at first only academia and Acorn took notice, quickly developing
Stanford MIPS, Berkeley RISC, and ARM, while Motorola apparently still
saw the VAX as the ideal, and made the 68020 more VAX-like. Intel
pursued BiiN and the i960 (supposedly a RISC with register windows,
but I have never seen the instruction set) at the time, with the i386
as a side project that became the main project when the PCs took off;
at least the i386 did not add any VAX features beyond those already
present in the 80286 (some might consider scaled addressing modes
CISC, but there are RISC CPUs that have them).

Overall, it seems to me that the RISC revolution managed to upset the
industry pretty soon after the IBM 801 became public, except that
Motorola continued on its VAX trajectory for some time; an alternative
history where Motorola would have developed the 68k in a more RISCy
direction earlier might be interesting. Maybe Apple would not have
gone for PPC, the Amiga and Atari would have had a better fate, and
maybe other PC competitors using the 68k would have sprung up.

An alternative history where the computer architects of the 70s were
given the RISC papers from the 80s would also be interesting. I
expect that the VAX would have looked much different, and the
microprocessors, too.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

Theo <theom+news@chiark.greenend.org.uk> writes:
>Surely the enabler for the 'RISC revolution' was falling memory costs, which
>enabled RISC's less-dense machine code

Here's code density results from
<2017Aug9.140559@mips.complang.tuwien.ac.at>:

bash grep gzip
398384 88084 47944 armhf
584340 130872 68276 armel
588972 129096 66892 amd64
604656 131804 66268 i386
637620 133868 72712 s390
638912 140544 71744 sparc
674912 141120 74032 mipsel
674912 141168 74112 mips
680928 139664 74272 powerpc
688052 150680 75908 s390x
1539872 322432 158656 ia64

As you can see, armhf (a RISC) has smaller code size than i386 and
s390 (CISCs). Unfortunatly, I don't have 68k or VAX results. Also,
one problem with these results is that they are based on modern
compilers, which are tuned for modern RAM and cache sizes.

- anton.
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

anton@mips.complang.tuwien.ac.at (Anton Ertl) writes:
>Theo <theom+news@chiark.greenend.org.uk> writes:
>>Surely the enabler for the 'RISC revolution' was falling memory costs, which
>>enabled RISC's less-dense machine code
>
>Here's code density results from
><2017Aug9.140559@mips.complang.tuwien.ac.at>:
>
> bash grep gzip
> 398384 88084 47944 armhf
> 584340 130872 68276 armel
> 588972 129096 66892 amd64
> 604656 131804 66268 i386
> 637620 133868 72712 s390
> 638912 140544 71744 sparc
> 674912 141120 74032 mipsel
> 674912 141168 74112 mips
> 680928 139664 74272 powerpc
> 688052 150680 75908 s390x
> 1539872 322432 158656 ia64
>
>As you can see, armhf (a RISC) has smaller code size than i386 and
>s390 (CISCs). Unfortunatly, I don't have 68k or VAX results. Also,
>one problem with these results is that they are based on modern
>compilers, which are tuned for modern RAM and cache sizes.

I found an earlier measurement (from
<2002Dec18.173217@a0.complang.tuwien.ac.at>) that includes m68k; the
order of architectures is quite different, which I explain with
differences in compiler tuning.

gzip_1.3.5-1 grep_2.4.2_3
text data bss text data bss
40566 3012 328956 39030 1212 1916 m68k
44258 3100 329264 43772 1212 2068 i386
54419 3012 329000 53238 1224 1948 s390
55384 3012 332960 52012 1224 1896 arm
58228 2884 329024 58144 1036 1960 sparc
58312 3356 328992 55886 1504 1940 powerpc
60045 2832 329000 60643 988 1956 hppa
73691 7760 329088 67542 3913 2152 alpha
86766 3432 329088 78886 1212 2004 mipsel
86846 3432 329088 78918 1212 2004 mips
112417 7344 329144 109004 3768 2200 ia64

"text" is the code size (and possibly read-only data).

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

On Sun, 16 Oct 2022 13:08:23 -0000 (UTC), Thomas Koenig wrote:

> I have been wondering for some time what a RICS machine would have
> looked like implemented only with standard TTL chips, and what impact it
> would have had had it been released in the late 1970s instead of, or in
> competition with, the VAX.

I presumed that the Pyramid 90x was build from separate chips, never seen
the boards from one though.

On 17.10.2022 09:56, Anton Ertl wrote:
> Intel
> pursued BiiN and the i960 (supposedly a RISC with register windows,
> but I have never seen the instruction set)

This can be remedied:
http://www.nj7p.org/Manuals/PDFs/Intel/270710-003.pdf

Regards,
Bernd

Robert Swindells <rjs@fdy2.co.uk> writes:
>On Sun, 16 Oct 2022 13:08:23 -0000 (UTC), Thomas Koenig wrote:
>
>> I have been wondering for some time what a RICS machine would have
>> looked like implemented only with standard TTL chips, and what impact it
>> would have had had it been released in the late 1970s instead of, or in
>> competition with, the VAX.
>
>I presumed that the Pyramid 90x was build from separate chips, never seen
>the boards from one though.

1983 (P90x) may have been a bit early for gate arrays, although we (at Burroughs)
were starting the gate array designs that shipped in 1987 during that
timeframe.

On Monday, October 17, 2022 at 3:41:39 AM UTC-5, Anton Ertl wrote:
> MitchAlsup <Mitch...@aol.com> writes:
> >DEC would still have had an advantage in cach=C3=A9 if nothing else.
> >And with the TTL available in 1978 it is not clear that HP would have
> >had "that much" of a performance advantage.
> The RISC would have benefited from the pipelining advantage. The VAX
> ran at 5MHz with 10 cycles per instruction on average. Would a RISC
> in the same technology have a significantly slower clock?
>
> Concerning the "advantage in cache": I expect that the RISC would have
<
The word I used would be pronounced cash-shay not cache
It is an aura of respect not a place to store things.
<
> outperformed the VAX even without cache: The Nova 800 had
> semiconductor memory with 800ns cycle time in 1971. So a RISC could
> have run at at least 1.25MHz (the ARM1 ran at 6MHz without cache in
> 1985). Assuming a CPI of 1.25, the VAX would have needed to reduce
> the instructions by a factor of 2 with it's CISC features, and AFAIK
> it did not.
> >Whether (or not) this would have lead to a less CISCy future is
> >entirely unclear, as x86 was already here and PCs were too. The
> >only thing (I can see) that would have altered the course of history
> >is a price structure competitive with PCs.
> But such a RISC would needed a too-expensive system compared to PCs,
> because it would have needed a 32-bit memory interface; and of course
> the CPU itself would have been far too expensive in TTL.
>
> But there was a RISC around at the time: the IBM 801 (well, first
> implementation in 1980, and it was in ECL, not TTL). But it seems
> that at first only academia and Acorn took notice, quickly developing
> Stanford MIPS, Berkeley RISC, and ARM, while Motorola apparently still
> saw the VAX as the ideal, and made the 68020 more VAX-like. Intel
> pursued BiiN and the i960 (supposedly a RISC with register windows,
> but I have never seen the instruction set) at the time, with the i386
> as a side project that became the main project when the PCs took off;
> at least the i386 did not add any VAX features beyond those already
> present in the 80286 (some might consider scaled addressing modes
> CISC, but there are RISC CPUs that have them).
>
> Overall, it seems to me that the RISC revolution managed to upset the
> industry pretty soon after the IBM 801 became public, except that
> Motorola continued on its VAX trajectory for some time; an alternative
> history where Motorola would have developed the 68k in a more RISCy
<
At the time RISC 1st generation started, Motorola already had done the
damage to the 68K with the '020. {That is: put in the extra CISCy stuff
that was more of a pain to pipeline than the '000}
<
> direction earlier might be interesting. Maybe Apple would not have
> gone for PPC, the Amiga and Atari would have had a better fate, and
> maybe other PC competitors using the 68k would have sprung up.
>
> An alternative history where the computer architects of the 70s were
> given the RISC papers from the 80s would also be interesting. I
> expect that the VAX would have looked much different, and the
> microprocessors, too.
<
We look back on the VAX as if it were horrible, but if you go back to
the time of the PDP-11/45 and /70, VAX looked like a significant step
forward. In effect, VAX and 432 started the pendulum swinging away
from CISC towards RISC.
>
> - anton
> --
> 'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
> Mitch Alsup, <c17fcd89-f024-40e7...@googlegroups.com>

On Sunday, October 16, 2022 at 6:03:27 PM UTC-5, MitchAlsup wrote:
> On Sunday, October 16, 2022 at 11:19:11 AM UTC-5, Theo wrote:
> > Thomas Koenig <tko...@netcologne.de> wrote:
> > > I've now found the answer to the first question. HP first released
> > > its HP-PA architecture with a CPU made from MSI TTL chips, described
> > > in https://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1987-03.pdf ,
> > > first shipping its HP 3000/930 in 1986. Its CPU had six printed
> > > circuit boards, running at 8 MHz, and performing around 4-5 million
> > > of its own instructions per second.
> > That's interesting. It feels like a nice hobbyist project for somebody to
> > try today...
> > > Such a machine (with smaller caches, probably) in 1978 would have
> > > been entirely possible, and would have outperformed the VAX by a
> > > reasonable factor, leading to a less CISC-y microprocessor world.
> <
> > Surely the enabler for the 'RISC revolution' was falling memory costs, which
> > enabled RISC's less-dense machine code and thus a simpler, faster CPU? I'm
> > not sure you'd get very far with a RISC CPU at 1978 DRAM prices.
> <
> As I saw it::
> <
> The enabler for RISC 1st generation was the ability to put a whole 32-bit
> pipelined data path on a single chip -- combined with the inability to put
> a CISC ISA microcode control engine on the same chip.
> <
> Falling SRAM prices may have helped, but were not that big a contributing
> factor.
> >
> > Theo

RISC also pipelined the instruction flow. Even if 32-bit instructions are half as dense,
the instruction flow matches the memory interface. And a small instruction cache helps.
The reduction in data flow due to having a register file is a bigger benefit than the savings
from more compact instructions of non-RISC ISAs.
So from a memory bandwidth point of view, register files and larger instructions win over
micro-programming and higher density instructions?

Today's transistor budgets allow OOO micro-architecture and the trade-offs are not as simple.

Anton Ertl <anton@mips.complang.tuwien.ac.at> schrieb:
> MitchAlsup <MitchAlsup@aol.com> writes:
>>DEC would still have had an advantage in cach=C3=A9 if nothing else.
>>And with the TTL available in 1978 it is not clear that HP would have
>>had "that much" of a performance advantage.
>
> The RISC would have benefited from the pipelining advantage. The VAX
> ran at 5MHz with 10 cycles per instruction on average. Would a RISC
> in the same technology have a significantly slower clock?

The TTL implementation of the first HP-PA would suggest not. They
clocked it at 8 MHz, with a complex RISC pipeline.

This is also the sort of cycle that looks reasonable when browsing
through TI TTL handbooks from the era. Addition certainly was
fast enough for that kind of cycle.

Now, building a Dadda-style multipliers out of the four-by-four
multipliers (74274) plus the full adders (74275) and final summation
with 74181/74182 would have looked daunting from the number of
chips and circuit area used, but it would sound doable with a few
cycles of latency, and doubtless TI would have approved :-)

> Concerning the "advantage in cache": I expect that the RISC would have
> outperformed the VAX even without cache: The Nova 800 had
> semiconductor memory with 800ns cycle time in 1971. So a RISC could
> have run at at least 1.25MHz (the ARM1 ran at 6MHz without cache in
> 1985). Assuming a CPI of 1.25, the VAX would have needed to reduce
> the instructions by a factor of 2 with it's CISC features, and AFAIK
> it did not.

No reason why a RISC would have had to have lower cycle time than
a VAX. HP had a CPI of around 1.75 at the time of their TTL PA-RISC
implementation.

MitchAlsup <MitchAlsup@aol.com> writes:
>At the time RISC 1st generation started, Motorola already had done the
>damage to the 68K with the '020. {That is: put in the extra CISCy stuff
>that was more of a pain to pipeline than the '000}

When was that? "The case for the reduced instruction set computer"
was published in October 1980, so the cat was out of the bag at that
point at the latest.

>> An alternative history where the computer architects of the 70s were
>> given the RISC papers from the 80s would also be interesting. I
>> expect that the VAX would have looked much different, and the
>> microprocessors, too.
><
>We look back on the VAX as if it were horrible, but if you go back to
>the time of the PDP-11/45 and /70, VAX looked like a significant step
>forward.

And it was, it just was a step into the wrong direction. And I think
that if the VAX architects had the RISC papers available, they would
have recognized that and designed the VAX differently. Maybe not as a
RISC (after all, it should also support PDP-11 code), but maybe more
like a 32-bit PDP-11 with more registers and maybe some addressing
modes deprecated.

>In effect, VAX and 432 started the pendulum swinging away
>from CISC towards RISC.

By moving it even further in the other direction. It's interesting
that PDP-11 is somewhat similar to the IA-32 and S/360 architectures,
with all of them having load-and-op and read-modify-write
instructions, while VAX with its three-general-operands was quite
different. In particular, PDP-11, IA-32, and S/360 (and original 68K)
have only one memory address for most instructions (better would be,
if all instructions had that property, but these architectures were
all introduced or extended processors without MMUs).

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

Bernd Linsel <bl1-removethis@gmx.com> writes:
>On 17.10.2022 09:56, Anton Ertl wrote:
>> Intel
>> pursued BiiN and the i960 (supposedly a RISC with register windows,
>> but I have never seen the instruction set)
>
>This can be remedied:
>http://www.nj7p.org/Manuals/PDFs/Intel/270710-003.pdf

Thanks. Yes, it's a RISC. A load/store architecture with register
windows, with instructions that are generally 32-bit wide, but may
have a 32-bit displacement appended.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

On 17 Oct 2022, MitchAlsup wrote
(in article<48fc8f3d-7901-4de0-a0d5-dbe501d862d7n@googlegroups.com>):

> On Monday, October 17, 2022 at 3:41:39 AM UTC-5, Anton Ertl wrote:
> > MitchAlsup <Mitch...@aol.com> writes:
> > > DEC would still have had an advantage in cach=C3=A9 if nothing else.
> > > And with the TTL available in 1978 it is not clear that HP would have
> > > had "that much" of a performance advantage.
> > The RISC would have benefited from the pipelining advantage. The VAX
> > ran at 5MHz with 10 cycles per instruction on average. Would a RISC
> > in the same technology have a significantly slower clock?
> >
> > Concerning the "advantage in cache": I expect that the RISC would have
> <
> The word I used would be pronounced cash-shay not cache
> It is an aura of respect not a place to store things.
> <
Actually, Mitch, while it would be so pronounced,
it means 'hidden'. The word you needed is 'cachet'.

Oh, and BTW, it's 'Spectre', not 'Spectré'. 8-)

--
Bill Findlay

Theo <theom+news@chiark.greenend.org.uk> schrieb:
> Thomas Koenig <tkoenig@netcologne.de> wrote:
>> I've now found the answer to the first question. HP first released
>> its HP-PA architecture with a CPU made from MSI TTL chips, described
>> in https://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1987-03.pdf ,
>> first shipping its HP 3000/930 in 1986. Its CPU had six printed
>> circuit boards, running at 8 MHz, and performing around 4-5 million
>> of its own instructions per second.
>
> That's interesting. It feels like a nice hobbyist project for somebody to
> try today...

Today, it would be possible to work from one of the published design
documents for earlier RISC architectures, but it would still be
a tall order (unless somebody wrote a VHDL-to-74xx converter :-)

On Monday, October 17, 2022 at 12:04:50 PM UTC-5, JimBrakefield wrote:
> On Sunday, October 16, 2022 at 6:03:27 PM UTC-5, MitchAlsup wrote:
> > On Sunday, October 16, 2022 at 11:19:11 AM UTC-5, Theo wrote:
> > > Thomas Koenig <tko...@netcologne.de> wrote:
> > > > I've now found the answer to the first question. HP first released
> > > > its HP-PA architecture with a CPU made from MSI TTL chips, described
> > > > in https://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1987-03.pdf ,
> > > > first shipping its HP 3000/930 in 1986. Its CPU had six printed
> > > > circuit boards, running at 8 MHz, and performing around 4-5 million
> > > > of its own instructions per second.
> > > That's interesting. It feels like a nice hobbyist project for somebody to
> > > try today...
> > > > Such a machine (with smaller caches, probably) in 1978 would have
> > > > been entirely possible, and would have outperformed the VAX by a
> > > > reasonable factor, leading to a less CISC-y microprocessor world.
> > <
> > > Surely the enabler for the 'RISC revolution' was falling memory costs, which
> > > enabled RISC's less-dense machine code and thus a simpler, faster CPU? I'm
> > > not sure you'd get very far with a RISC CPU at 1978 DRAM prices.
> > <
> > As I saw it::
> > <
> > The enabler for RISC 1st generation was the ability to put a whole 32-bit
> > pipelined data path on a single chip -- combined with the inability to put
> > a CISC ISA microcode control engine on the same chip.
> > <
> > Falling SRAM prices may have helped, but were not that big a contributing
> > factor.
> > >
> > > Theo
> RISC also pipelined the instruction flow.
<
So did Stretch, 360-91, 1108, ...
<
> Even if 32-bit instructions are half as dense,
> the instruction flow matches the memory interface. And a small instruction cache helps.
> The reduction in data flow due to having a register file is a bigger benefit than the savings
> from more compact instructions of non-RISC ISAs.
<
The 32-entry register file allows a good compiler to get rid of 1/3rd of all memory refs
compared to <say> a VAX-11/780.
<
> So from a memory bandwidth point of view, register files and larger instructions win over
> micro-programming and higher density instructions?
<
It was said (?Hennessey?} that the original MIPS (Stanford) ran 50% more instructions
6× faster for an overall 4× performance advantage. {I forgot whether this was x86, 68K
or VAX as the comparison}.
<
>
> Today's transistor budgets allow OOO micro-architecture and the trade-offs are not as simple.
<
Todays transistor budgets allow for may thing to be handled with brute force.

Anton Ertl <anton@mips.complang.tuwien.ac.at> wrote:
> anton@mips.complang.tuwien.ac.at (Anton Ertl) writes:
>> Theo <theom+news@chiark.greenend.org.uk> writes:
>>> Surely the enabler for the 'RISC revolution' was falling memory costs, which
>>> enabled RISC's less-dense machine code
>>
>> Here's code density results from
>> <2017Aug9.140559@mips.complang.tuwien.ac.at>:
>>
>> bash grep gzip
>> 398384 88084 47944 armhf
>> 584340 130872 68276 armel
>> 588972 129096 66892 amd64
>> 604656 131804 66268 i386
>> 637620 133868 72712 s390
>> 638912 140544 71744 sparc
>> 674912 141120 74032 mipsel
>> 674912 141168 74112 mips
>> 680928 139664 74272 powerpc
>> 688052 150680 75908 s390x
>> 1539872 322432 158656 ia64
>>
>> As you can see, armhf (a RISC) has smaller code size than i386 and
>> s390 (CISCs). Unfortunatly, I don't have 68k or VAX results. Also,
>> one problem with these results is that they are based on modern
>> compilers, which are tuned for modern RAM and cache sizes.
>
> I found an earlier measurement (from
> <2002Dec18.173217@a0.complang.tuwien.ac.at>) that includes m68k; the
> order of architectures is quite different, which I explain with
> differences in compiler tuning.
>
> gzip_1.3.5-1 grep_2.4.2_3
> text data bss text data bss
> 40566 3012 328956 39030 1212 1916 m68k
> 44258 3100 329264 43772 1212 2068 i386
> 54419 3012 329000 53238 1224 1948 s390
> 55384 3012 332960 52012 1224 1896 arm
> 58228 2884 329024 58144 1036 1960 sparc
> 58312 3356 328992 55886 1504 1940 powerpc
> 60045 2832 329000 60643 988 1956 hppa
> 73691 7760 329088 67542 3913 2152 alpha
> 86766 3432 329088 78886 1212 2004 mipsel
> 86846 3432 329088 78918 1212 2004 mips
> 112417 7344 329144 109004 3768 2200 ia64
>
> "text" is the code size (and possibly read-only data).
>
> - anton

VAX has horrible code density, as bad as RISC.

In article <2022Oct17.190335@mips.complang.tuwien.ac.at>,
anton@mips.complang.tuwien.ac.at (Anton Ertl) wrote:

> MitchAlsup <MitchAlsup@aol.com> writes:
> >At the time RISC 1st generation started, Motorola already had done
> >the damage to the 68K with the '020. {That is: put in the extra CISCy
> >stuff that was more of a pain to pipeline than the '000}
>
> When was that? "The case for the reduced instruction set computer"
> was published in October 1980, so the cat was out of the bag at that
> point at the latest.

How long does it takes a large company, with a successful product and
plans to improve it, to realise and accept that they're heading for a
dead end?

Research papers are easy for commercial managers to discount. The
commercial impact of RISC started in 1985-86 as MIPS and SPARC
demonstrated that RISC worked and would sell. 68020 appeared in 1984 and
the 88000 in 1988.

John

On Monday, October 17, 2022 at 3:14:02 PM UTC-5, John Dallman wrote:
> In article <2022Oct1...@mips.complang.tuwien.ac.at>,
> an...@mips.complang.tuwien.ac.at (Anton Ertl) wrote:
>
> > MitchAlsup <Mitch...@aol.com> writes:
> > >At the time RISC 1st generation started, Motorola already had done
> > >the damage to the 68K with the '020. {That is: put in the extra CISCy
> > >stuff that was more of a pain to pipeline than the '000}
> >
> > When was that? "The case for the reduced instruction set computer"
> > was published in October 1980, so the cat was out of the bag at that
> > point at the latest.
<
> How long does it takes a large company, with a successful product and
> plans to improve it, to realise and accept that they're heading for a
> dead end?
>
> Research papers are easy for commercial managers to discount. The
> commercial impact of RISC started in 1985-86 as MIPS and SPARC
> demonstrated that RISC worked and would sell. 68020 appeared in 1984 and
> the 88000 in 1988.
<
68020 was "on the drawing boards" in '81 and basically in concrete in '82
Seeing tapeout late in '82 and chips inside Moto in '83. So, even if they read
the papers on the day it was published, and convinced management that
this was the direction of the future the day after; the '020 would have still
been the plan for sales in '84 through '87. You cannot "create" a RISC ISA,
a pipeline, do a compiler, and port an OS is less time--especially if your
current design team was "all on" the current project.
<
When I interviewed at Moto in Aug '83, Murry Goldman ask me my opinion
of RISC and where it was going.......
>
> John

MitchAlsup <MitchAlsup@aol.com> schrieb:

> When I interviewed at Moto in Aug '83, Murry Goldman ask me my opinion
> of RISC and where it was going.......

What did you answer, and what was his reaction?

On Monday, October 17, 2022 at 4:10:27 PM UTC-5, Thomas Koenig wrote:
> MitchAlsup <Mitch...@aol.com> schrieb:
> > When I interviewed at Moto in Aug '83, Murry Goldman ask me my opinion
> > of RISC and where it was going.......
<
> What did you answer, and what was his reaction?
<
I lied:: I said "I think the Jury is still out".
<
He liked that answer.

MitchAlsup <MitchAlsup@aol.com> schrieb:
> On Monday, October 17, 2022 at 4:10:27 PM UTC-5, Thomas Koenig wrote:
>> MitchAlsup <Mitch...@aol.com> schrieb:
>> > When I interviewed at Moto in Aug '83, Murry Goldman ask me my opinion
>> > of RISC and where it was going.......
><
>> What did you answer, and what was his reaction?
><
> I lied:: I said "I think the Jury is still out".

Very diplomatic - no manager likes to be told that he'd been
backing the wrong horse, and that he should have known
(especially since the 68020 was released the next year).

><
> He liked that answer.

I can well believe that.