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devel / comp.arch / Re: Another use for R0

Another use for R0

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Subject: Another use for R0
From: robfi...@gmail.com (robf...@gmail.com)
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by: robf...@gmail.com - Mon, 24 Oct 2022 04:34 UTC

In the rfPhoenix core any register may be used as a vector mask register.
So, then I hit upon the idea of having R0 act as the value -1 for the vector
mask, meaning the operation is unmasked.

I just switched the ISA to 48-bit instructions from 40. In part to reduce the number of different instruction formats. Having four six-bit register fields in
an instruction, plus a size or precision specifier and a format specifier ate
up a lot of bits. There are now a few extra bits in instructions rather than
having a more complex decoder.

Re: Another use for R0

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Subject: Re: Another use for R0
From: MitchAl...@aol.com (MitchAlsup)
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by: MitchAlsup - Mon, 24 Oct 2022 19:34 UTC

On Sunday, October 23, 2022 at 11:34:05 PM UTC-5, robf...@gmail.com wrote:
> In the rfPhoenix core any register may be used as a vector mask register.
> So, then I hit upon the idea of having R0 act as the value -1 for the vector
> mask, meaning the operation is unmasked.
<
a) If you had sign control on register operands--this would be straightforward.
b) if you had your vector compare deliver {1,0} instead of {0,1} it would be
unnecessary.
>
> I just switched the ISA to 48-bit instructions from 40. In part to reduce the number of different instruction formats. Having four six-bit register fields in
> an instruction, plus a size or precision specifier and a format specifier ate
> up a lot of bits. There are now a few extra bits in instructions rather than
> having a more complex decoder.

Subject	Author
Another use for R0	robf...@gmail.com
Re: Another use for R0	MitchAlsup