This YouTube video

https://www.youtube.com/watch?v=vQ5JPqeFitM

is saying that while logic is still scaling, cache on CPUs is failing to
scale with new processes, meaning that chips have come to the
end of the line.

John Savard

On Thursday, December 22, 2022 at 5:07:02 PM UTC-6, Quadibloc wrote:
> This YouTube video
>
> https://www.youtube.com/watch?v=vQ5JPqeFitM
>
> is saying that while logic is still scaling, cache on CPUs is failing to
> scale with new processes, meaning that chips have come to the
> end of the line.
<
SRAMs have always been dependent on transistor sizing. The SRAM
is needs the n-channel pull down to carry 3× the current of the p-channel
pull up transistor and that the p-channel pull up can avoid collapse when
the word line is asserted.
<
What is happening in Gate-all-around is that you do not have any way left
to size the transistors. and thus, you have to use more copies of the transistors.
So the 6-T SRAM cell now contains 10-12 transistors so that the various
above rules are maintained.
<
And then you get in to bit-line leakage, drain-induced-barrier-lowering,
lack of sensitivity in the SRAM sense amplifier, and other effects.
>
> John Savard

MitchAlsup <MitchAlsup@aol.com> wrote:
> On Thursday, December 22, 2022 at 5:07:02 PM UTC-6, Quadibloc wrote:
> > This YouTube video
> >
> > https://www.youtube.com/watch?v=vQ5JPqeFitM
> >
> > is saying that while logic is still scaling, cache on CPUs is failing to
> > scale with new processes, meaning that chips have come to the
> > end of the line.
> <
> SRAMs have always been dependent on transistor sizing. The SRAM
> is needs the n-channel pull down to carry 3? the current of the p-channel
> pull up transistor and that the p-channel pull up can avoid collapse when
> the word line is asserted.
> <
> What is happening in Gate-all-around is that you do not have any way left
> to size the transistors. and thus, you have to use more copies of the transistors.
> So the 6-T SRAM cell now contains 10-12 transistors so that the various
> above rules are maintained.
> <
> And then you get in to bit-line leakage, drain-induced-barrier-lowering,
> lack of sensitivity in the SRAM sense amplifier, and other effects.

AFAICS the ultimate limit of traditional semiconductors would be
to place each atom at desired place. Of course, this can not be
done in arbitrary way, one has to design atomic configuration so
that it is stable. On manufacturing side there is a lot experience
here: chemical industry is making many complex molecules. "Defect
rates" from chemical style processing may be too high for logic,
but error correction and/or disabling faulty parts should be able
to tolerate attainable defect rates.

Designing molecules with good properties may be tricky. One question
is which confuguration would give smallest memory cell. But power
also is important, so one may prefer bigger cell if it leads to
operation at lower power level.

Once we get at atomic level, there seem to be no easy way forward.
I mean, one may seek for somewhat better configurations, but that
is likely to lead to limited gain. IIUC appropriate linear structures
are expected to be superconductive at room temperature. Having
chips with superconductive wires could resolve current troubles
with RC transmission lines and lead to higher speeds. But all
this is likely to hit rather fundamental limits within 10-20
years.

More radical progress may require going to subatomic level. But
everyting there seem to be short lived. So basically, one would
build computer, and do some computations hoping that computation
finishes before computer becomes non-functional due to radioactive
decay. And big question is if we ever manage enough control on
subatomic level to build useful structures...

BTW: Idea of building computer components as molecules is kind of
obvious. I would expect at least some research labs to do work in
this direction. Yet, there seem to be complete silence in public
media. Nothing to show or fears of hinting competitors?

--
Waldek Hebisch

On Saturday, December 24, 2022 at 4:30:13 PM UTC-6, anti...@math.uni.wroc.pl wrote:
> MitchAlsup <Mitch...@aol.com> wrote:
> > On Thursday, December 22, 2022 at 5:07:02 PM UTC-6, Quadibloc wrote:
> > > This YouTube video
> > >
> > > https://www.youtube.com/watch?v=vQ5JPqeFitM
> > >
> > > is saying that while logic is still scaling, cache on CPUs is failing to
> > > scale with new processes, meaning that chips have come to the
> > > end of the line.
> > <
> > SRAMs have always been dependent on transistor sizing. The SRAM
> > is needs the n-channel pull down to carry 3? the current of the p-channel
> > pull up transistor and that the p-channel pull up can avoid collapse when
> > the word line is asserted.
> > <
> > What is happening in Gate-all-around is that you do not have any way left
> > to size the transistors. and thus, you have to use more copies of the transistors.
> > So the 6-T SRAM cell now contains 10-12 transistors so that the various
> > above rules are maintained.
> > <
> > And then you get in to bit-line leakage, drain-induced-barrier-lowering,
> > lack of sensitivity in the SRAM sense amplifier, and other effects.
<
> AFAICS the ultimate limit of traditional semiconductors would be
> to place each atom at desired place. Of course, this can not be
> done in arbitrary way, one has to design atomic configuration so
> that it is stable. On manufacturing side there is a lot experience
> here: chemical industry is making many complex molecules. "Defect
> rates" from chemical style processing may be too high for logic,
> but error correction and/or disabling faulty parts should be able
> to tolerate attainable defect rates.
<
Semiconductors are not atoms, but crystals. Back when I was familiar
with the processes, we would use a dose of 10**18 dopant atoms
(a rather strong dose in 65nm planar transistors.) But 10**18 per what ?
It ends up to be Avagadro's number 6.02*10**23 of silicon atoms with
10**18 dopant atoms.
<
Dopant concentrations have been increasing since 6µ, but this still means
that you need 1 dopant atom for every 5,000-10,000 silicon atoms. Back
when a source or drain contained 100,000 atoms (65nm planar) we would
get a dozen doping atoms on one side with a dozen±3 on the other side
of the transistor. In the FinFET era there are not 10,000 atoms in the
transistor--but transistors source/drains are no longer doped, the metal
used to form the gate is doped, instead.
>
> Designing molecules with good properties may be tricky. One question
> is which confuguration would give smallest memory cell. But power
> also is important, so one may prefer bigger cell if it leads to
> operation at lower power level.
>
> Once we get at atomic level, there seem to be no easy way forward.
<
7nm FinFETs are only a dozen atoms wide, with gate oxides in the
4 atomic layers level. Strictly speaking we have been at/near the atomic
level since 14nm........
<
> I mean, one may seek for somewhat better configurations, but that
> is likely to lead to limited gain. IIUC appropriate linear structures
> are expected to be superconductive at room temperature. Having
> chips with superconductive wires could resolve current troubles
> with RC transmission lines and lead to higher speeds. But all
> this is likely to hit rather fundamental limits within 10-20
> years.
<
Superconductors have the property that they displace the magnetic field.
>
> More radical progress may require going to subatomic level. But
> everyting there seem to be short lived. So basically, one would
> build computer, and do some computations hoping that computation
> finishes before computer becomes non-functional due to radioactive
> decay. And big question is if we ever manage enough control on
> subatomic level to build useful structures...
>
> BTW: Idea of building computer components as molecules is kind of
> obvious. I would expect at least some research labs to do work in
> this direction. Yet, there seem to be complete silence in public
> media. Nothing to show or fears of hinting competitors?
>
> --
> Waldek Hebisch