The Sun 68000 workstation was often called a 3M machine,
a million pixel display, a million instructions per second and a mega byte of memory.
It is clear we have been in the 3G era for some time. Leading to the question of the first 3Tera machine and the first 3K machine?
Are we now in the 3T era (the many GPU and DNN machines)?

On Monday, March 6, 2023 at 5:11:22 PM UTC-6, JimBrakefield wrote:
> The Sun 68000 workstation was often called a 3M machine,
<
3M was a name I first heard in 1973 at CMU having to do with a 1M pixel display,
1 MegaByte of main memory, and 1M instructions per second of performance.
{not necessarily in that order.}
<
> a million pixel display, a million instructions per second and a mega byte of memory.
> It is clear we have been in the 3G era for some time. Leading to the question of the first 3Tera machine and the first 3K machine?
> Are we now in the 3T era (the many GPU and DNN machines)?
<
I do not know of any single display with a billion pixels.
I do not know of any display with significantly more than 32M pixels.
Camera sensors seem to have stopped in the 60M pixel range.
Still a factor of 30 away (unless you want to alter the name......)
I do not see displays ever getting much above 16K UHDTV.
I do not see the electronics being capable of driving 16K from
a single cable (frequency of cable wire limits)
<
So, to me, and under the original definitions::
<
We are in the 2G34M era
or
maybe we are in the 2G8M era for home computers
and
maybe we are in the 1T34M era for cabinet sized servers

On Monday, March 6, 2023 at 6:07:44 PM UTC-6, MitchAlsup wrote:
> On Monday, March 6, 2023 at 5:11:22 PM UTC-6, JimBrakefield wrote:
> > The Sun 68000 workstation was often called a 3M machine,
> <
> 3M was a name I first heard in 1973 at CMU having to do with a 1M pixel display,
> 1 MegaByte of main memory, and 1M instructions per second of performance.
> {not necessarily in that order.}
> <
> > a million pixel display, a million instructions per second and a mega byte of memory.
> > It is clear we have been in the 3G era for some time. Leading to the question of the first 3Tera machine and the first 3K machine?
> > Are we now in the 3T era (the many GPU and DNN machines)?
> <
> I do not know of any single display with a billion pixels.
> I do not know of any display with significantly more than 32M pixels.
> Camera sensors seem to have stopped in the 60M pixel range.
> Still a factor of 30 away (unless you want to alter the name......)
> I do not see displays ever getting much above 16K UHDTV.
> I do not see the electronics being capable of driving 16K from
> a single cable (frequency of cable wire limits)
> <
> So, to me, and under the original definitions::
> <
> We are in the 2G34M era
> or
> maybe we are in the 2G8M era for home computers
> and
> maybe we are in the 1T34M era for cabinet sized servers
Will accept CMU as the source for the 3M term.

For a 4K display at 60 frames/sec yields about 0.5B pixels/sec leading to 20 minutes for one Tera pixels.
For compute power on a 4GHz machine with 16 cores and 256 bit MMX registers doing two MACs per clock,
comes in at 64*2*8 = 1T single precision adds and 1T multiplies/sec?
Solid state "disk" memory is readily available at the 1TB size.

So a little bit of redefinition gets 2T ops, 1T solid state memory, and a 20 minute wait for 1T pixels.
As for the first 3K or 3M machine, ugh, it's an open question.
A CDC 6500 or 6700 with two consoles and full memory would be a 3M machine?

On Monday, March 6, 2023 at 7:31:51 PM UTC-6, JimBrakefield wrote:
> On Monday, March 6, 2023 at 6:07:44 PM UTC-6, MitchAlsup wrote:
> > On Monday, March 6, 2023 at 5:11:22 PM UTC-6, JimBrakefield wrote:
> > > The Sun 68000 workstation was often called a 3M machine,
> > <
> > 3M was a name I first heard in 1973 at CMU having to do with a 1M pixel display,
> > 1 MegaByte of main memory, and 1M instructions per second of performance.
> > {not necessarily in that order.}
> > <
> > > a million pixel display, a million instructions per second and a mega byte of memory.
> > > It is clear we have been in the 3G era for some time. Leading to the question of the first 3Tera machine and the first 3K machine?
> > > Are we now in the 3T era (the many GPU and DNN machines)?
> > <
> > I do not know of any single display with a billion pixels.
> > I do not know of any display with significantly more than 32M pixels.
> > Camera sensors seem to have stopped in the 60M pixel range.
> > Still a factor of 30 away (unless you want to alter the name......)
> > I do not see displays ever getting much above 16K UHDTV.
> > I do not see the electronics being capable of driving 16K from
> > a single cable (frequency of cable wire limits)
> > <
> > So, to me, and under the original definitions::
> > <
> > We are in the 2G34M era
> > or
> > maybe we are in the 2G8M era for home computers
> > and
> > maybe we are in the 1T34M era for cabinet sized servers
<
> Will accept CMU as the source for the 3M term.
<
It was either Bell, or Grayson, or Newell who coined the phrase, as I understand it.
>
> For a 4K display at 60 frames/sec yields about 0.5B pixels/sec leading to 20 minutes for one Tera pixels.
<
The digital effects for the movie Tron (1982) were done on S.E.L 32/65 minicomputer and displayed on a Techtronic's 4K by 4K color screen mounted vertically in a dark "box". Screen draw time was about 3 minutes: blank screen, open shutter, compute and draw image, close shutter, blank screen. {Circa 1980}
<
> For compute power on a 4GHz machine with 16 cores and 256 bit MMX registers doing two MACs per clock,
> comes in at 64*2*8 = 1T single precision adds and 1T multiplies/sec?
> Solid state "disk" memory is readily available at the 1TB size.
<
I have no problem assigning 1T compute rates, but the original 2M statement was instructions
that the average program would be using. Cat is an average program and uses nothing of SIMD
extensions.
<
Likewise, I have no trouble assigning 1T storage, but only serious servers have this in DRAM
while anyone can get it in DISK or solid state form.
>
> So a little bit of redefinition gets 2T ops, 1T solid state memory, and a 20 minute wait for 1T pixels.
> As for the first 3K or 3M machine, ugh, it's an open question.
<
Do modern compilers compile at 1T instruction rates ???
I, personally, don't think so; more like in the neighborhood of 2-8 GI/s,
Even when multiplied by 8-16 cores if falls a decimal order of magnitude short.
< ---------------------------------------------------------------------------------------------------------
{Pet peave:: a long time ago when hypercube was the rage:: every time its professor stated
that he never found an application that would not run well on his hypercube machines. I ask
if he had ever tried to run m×n compilations on his hypercube.
The audience laughed.
The professor had no reply.}
<
I think you are trying a bit too hard to alter the underlying meaning to fit you narrative.
< ----------------------------------------------------------------------------------------------------------
GPUs on the other hand have been at/near/above 1Tops since about 2015.
<
> A CDC 6500 or 6700 with two consoles and full memory would be a 3M machine?
<
Not quite:: A CDC 6600 (with the scoreboard) was a 100ns machine (10MHz) that was
averaging 6-cycles per instruction*. The 6400 was the same chassis without scoreboard
and was about 2.5× slower--this would fail the 1MI/s criteria by a little, whereas 6600
was just over the hump.
<
(*) certain kernels ran significantly better getting close to averaging 2.5I/cycle.
<
And then there is that 128Word memory not being a full 1MB.

On Monday, March 6, 2023 at 8:03:11 PM UTC-6, MitchAlsup wrote:
> On Monday, March 6, 2023 at 7:31:51 PM UTC-6, JimBrakefield wrote:
> > On Monday, March 6, 2023 at 6:07:44 PM UTC-6, MitchAlsup wrote:
> > > On Monday, March 6, 2023 at 5:11:22 PM UTC-6, JimBrakefield wrote:
> > > > The Sun 68000 workstation was often called a 3M machine,
> > > <
> > > 3M was a name I first heard in 1973 at CMU having to do with a 1M pixel display,
> > > 1 MegaByte of main memory, and 1M instructions per second of performance.
> > > {not necessarily in that order.}
> > > <
> > > > a million pixel display, a million instructions per second and a mega byte of memory.
> > > > It is clear we have been in the 3G era for some time. Leading to the question of the first 3Tera machine and the first 3K machine?
> > > > Are we now in the 3T era (the many GPU and DNN machines)?
> > > <
> > > I do not know of any single display with a billion pixels.
> > > I do not know of any display with significantly more than 32M pixels.
> > > Camera sensors seem to have stopped in the 60M pixel range.
> > > Still a factor of 30 away (unless you want to alter the name......)
> > > I do not see displays ever getting much above 16K UHDTV.
> > > I do not see the electronics being capable of driving 16K from
> > > a single cable (frequency of cable wire limits)
> > > <
> > > So, to me, and under the original definitions::
> > > <
> > > We are in the 2G34M era
> > > or
> > > maybe we are in the 2G8M era for home computers
> > > and
> > > maybe we are in the 1T34M era for cabinet sized servers
> <
> > Will accept CMU as the source for the 3M term.
> <
> It was either Bell, or Grayson, or Newell who coined the phrase, as I understand it.
> >
> > For a 4K display at 60 frames/sec yields about 0.5B pixels/sec leading to 20 minutes for one Tera pixels.
> <
> The digital effects for the movie Tron (1982) were done on S.E.L 32/65 minicomputer and displayed on a Techtronic's 4K by 4K color screen mounted vertically in a dark "box". Screen draw time was about 3 minutes: blank screen, open shutter, compute and draw image, close shutter, blank screen. {Circa 1980}
> <
> > For compute power on a 4GHz machine with 16 cores and 256 bit MMX registers doing two MACs per clock,
> > comes in at 64*2*8 = 1T single precision adds and 1T multiplies/sec?
> > Solid state "disk" memory is readily available at the 1TB size.
> <
> I have no problem assigning 1T compute rates, but the original 2M statement was instructions
> that the average program would be using. Cat is an average program and uses nothing of SIMD
> extensions.
> <
> Likewise, I have no trouble assigning 1T storage, but only serious servers have this in DRAM
> while anyone can get it in DISK or solid state form.
> >
> > So a little bit of redefinition gets 2T ops, 1T solid state memory, and a 20 minute wait for 1T pixels.
> > As for the first 3K or 3M machine, ugh, it's an open question.
> <
> Do modern compilers compile at 1T instruction rates ???
> I, personally, don't think so; more like in the neighborhood of 2-8 GI/s,
> Even when multiplied by 8-16 cores if falls a decimal order of magnitude short.
> < ---------------------------------------------------------------------------------------------------------
> {Pet peave:: a long time ago when hypercube was the rage:: every time its professor stated
> that he never found an application that would not run well on his hypercube machines. I ask
> if he had ever tried to run m×n compilations on his hypercube.
> The audience laughed.
> The professor had no reply.}
> <
> I think you are trying a bit too hard to alter the underlying meaning to fit you narrative.
> < ----------------------------------------------------------------------------------------------------------
> GPUs on the other hand have been at/near/above 1Tops since about 2015.
> <
> > A CDC 6500 or 6700 with two consoles and full memory would be a 3M machine?
> <
> Not quite:: A CDC 6600 (with the scoreboard) was a 100ns machine (10MHz) that was
> averaging 6-cycles per instruction*. The 6400 was the same chassis without scoreboard
> and was about 2.5× slower--this would fail the 1MI/s criteria by a little, whereas 6600
> was just over the hump.
> <
> (*) certain kernels ran significantly better getting close to averaging 2..5I/cycle.
> <
> And then there is that 128Word memory not being a full 1MB.

|> trying a bit too hard to alter the underlying meaning to fit you narrative.
Yes, so much for the 3K-3M-3G-3T summary of computer history
Ugh, a radar chart would work:
(log axis in radial direction with K-M-G-T circles, decade contours, small number of processors shown)

On 3/6/2023 6:03 PM, MitchAlsup wrote:

snip

---------------------------------------------------------------------------------------------------------
> {Pet peave:: a long time ago when hypercube was the rage:: every time its professor stated
> that he never found an application that would not run well on his hypercube machines. I ask
> if he had ever tried to run m×n compilations on his hypercube.
> The audience laughed.
> The professor had no reply.}

At one point, I was asked to evaluate putting a large database system on
a hypercube based design (NCUBE). It quickly became apparent that the
lack of a large readily addressable memory was a performance killer.

--
- Stephen Fuld
(e-mail address disguised to prevent spam)

On 3/7/2023 1:12 AM, Stephen Fuld wrote:
> On 3/6/2023 6:03 PM, MitchAlsup wrote:
>
> snip
>
>
> ---------------------------------------------------------------------------------------------------------
>> {Pet peave:: a long time ago when hypercube was the rage:: every time
>> its professor stated
>> that he never found an application that would not run well on his
>> hypercube machines. I ask
>> if he had ever tried to run m×n compilations on his hypercube.
>> The audience laughed.
>> The professor had no reply.}
>
> At one point, I was asked to evaluate putting a large database system on
> a hypercube based design (NCUBE).  It quickly became apparent that the
> lack of a large readily addressable memory was a performance killer.
>

Yeah.

I am recently left with a sort of inverse situation.

I am recently left with the wonkiness that, despite an early 2000s
laptop beating my BJX2 Core (at 50 MHz) on nearly every metric, for "big
ASM blob representing a neural net" vs "naive C version using x87 ops",
they manage to more or less reach parity.

Seemingly crossing the gulf that the laptop has around 34x the clock
speed...

While the BJX2 core is still falling a little short of its theoretical
limit of 200 MFLOPs.

And, this is with:
4x SIMD MUL + ADD
An op to load a vector in 1 cycle;
Shuffle ops;
...

But, the laptop also falls a little short of this, despite its
clock-speed advantage... I suspect it is because basically every
(scalar) FPU operation also involves loading and storing values to
memory and similar.

I had recently been pondering a few other ops that could possibly
further speed this case up, say:
PADD.H Rm, Imm56fv, Rn //4x S.E5.F8
PMUL.H Rm, Imm56fv, Rn //4x S.E5.F8
PMULSH.H Rm, Imm48fv8sh, Rn //4x S.E5.F6.I2
PMACSH.H Rm, Imm48fv8sh, Rn //4x S.E5.F6.I2
...

Which have an immediate vector, and possibly an integrated shuffle.

Possibly add SIMD FMAC operators, but likely at low precision. I have
come up with a possible way to do FMAC in a 3 cycle latency, but its
precision would kinda suck.

Even without this, a PMUL+Shuffle op could do well, as it would avoid
the issue that having a large-immediate PMUL would knock out the ability
to run shuffles in parallel with anything.

As well as, say:
PMULSH.H Rm, Ro, Imm10v, Rn
...

Which would just perform a shuffle (essentially an 8b shuffle, with two
extra bits to indicate which registers it applies to):
00: Reserved
01: Shuffle Rm
10: Shuffle Ro
11: Shuffle Rm&Ro (effectively reorders Rn)

This could get things possibly a little closer to the 200 MFLOP hard
limit at 50MHz.

But, would likely be borderline useless for most normal code (that is
not NN's). So, it is debatable of if it would be worthwhile to spend
more LUTs on this stuff...

Laptop still somewhat beats my BJX2 core in terms of memory copy speeds,
but nowhere near as much as one would guess by the difference in clock
speed.

Say, despite my Ryzen only having ~ 3x the clock speed, it has nearly
20x as much "memcpy()" bandwidth (for DRAM, for a single thread on the
Ryzen), and 30x as much for in-cache memcpy (oddly enough, for L1
memcpy, the difference between the laptop and BJX2 core is only around
3x; implying that it is on-average pushing around nearly 10x as much
data per clock cycle).

Granted, memcpy on my BJX2 core is typically moving 64 bytes per loop
iteration (this being what is needed to avoid pipeline stalls).

And, even then, when it was new (early WinXP era), this laptop was still
pretty fast vs what I remember of typical Win98 machines (still pretty
common at the time).

But, performance gets wonky...

If one asks Doom, Quake, or Dhrystone, it is seemingly performing not
that much better than a 486...

Granted, it depends a lot on coding style, and code with a bunch of
tight loops and mostly 32-bit scalar operations will not make effective
use of the CPU in this case...

So, alas...

On Monday, March 6, 2023 at 8:31:51 PM UTC-5, JimBrakefield wrote:
> On Monday, March 6, 2023 at 6:07:44 PM UTC-6, MitchAlsup wrote:
> > On Monday, March 6, 2023 at 5:11:22 PM UTC-6, JimBrakefield wrote:
> > > The Sun 68000 workstation was often called a 3M machine,
> > <
> > 3M was a name I first heard in 1973 at CMU having to do with a 1M pixel display,
> > 1 MegaByte of main memory, and 1M instructions per second of performance.
> > {not necessarily in that order.}
> > <
> > > a million pixel display, a million instructions per second and a mega byte of memory.
> > > It is clear we have been in the 3G era for some time. Leading to the question of the first 3Tera machine and the first 3K machine?
> > > Are we now in the 3T era (the many GPU and DNN machines)?
> > <
> > I do not know of any single display with a billion pixels.
> > I do not know of any display with significantly more than 32M pixels.
> > Camera sensors seem to have stopped in the 60M pixel range.
> > Still a factor of 30 away (unless you want to alter the name......)
> > I do not see displays ever getting much above 16K UHDTV.
> > I do not see the electronics being capable of driving 16K from
> > a single cable (frequency of cable wire limits)
> > <
> > So, to me, and under the original definitions::
> > <
> > We are in the 2G34M era
> > or
> > maybe we are in the 2G8M era for home computers
> > and
> > maybe we are in the 1T34M era for cabinet sized servers
> Will accept CMU as the source for the 3M term.
>
> For a 4K display at 60 frames/sec yields about 0.5B pixels/sec leading to 20 minutes for one Tera pixels.
> For compute power on a 4GHz machine with 16 cores and 256 bit MMX registers doing two MACs per clock,
> comes in at 64*2*8 = 1T single precision adds and 1T multiplies/sec?
> Solid state "disk" memory is readily available at the 1TB size.
>
> So a little bit of redefinition gets 2T ops, 1T solid state memory, and a 20 minute wait for 1T pixels.
> As for the first 3K or 3M machine, ugh, it's an open question.
> A CDC 6500 or 6700 with two consoles and full memory would be a 3M machine?

Each screen on the CDC 6000 series console was two 512*512 addressable (being a caligraphic display means they
were not really "pixels"), 2^19 addressable dots.

I did hear of a Tektronix 4014 connected to a CDC Cyber via a channel (special adapter), so 12M Pixels in mid-70s.

Also, CDC had ECS (extended core storage), which could be configured to at least 512K words (I think 1M or 2M was the limit).

- Tim