Of course, I speak of Gordon Moore, who did not live to see Moore's Law
come to an end:

https://www.cbc.ca/news/business/gordon-moore-intel-obituary-1.6791176

John Savard

Quadibloc <jsavard@ecn.ab.ca> writes:
>Of course, I speak of Gordon Moore, who did not live to see Moore's Law
>come to an end:

At Intel it has slowed down since about 2015:

32nm 2010 Westmere (2011 Sandy Bridge)
22nm 2012 Ivy Bridge (2013 Haswell)
14nm 2014 Broadwell
10nm 2019 Ice Lake (2018 Cannon Lake)

Abd 10nm (renamed into Intel 7) is what they are still delivering (of
course, with improvements since 2019).

DRAM growth also has slowed down: In 2015 I bought 2 x 8GB DIMMs
because 2 x 16GB was 1.5 times more expensive per Byte (not sure if
4GB DIMMs were cheaper at the time); nowadays the cheapest DIMM kits per
GB I see are:

EUR/GB
1.706 2 x 8GB DDR3-1333
1.775 2 x 16GB DDR4-2400
1.791 1 x 8GB DDR4-2133
1.799 2 x 8GB DDR3-1600
1.809 1 x 32GB DDR4-2666

So 32GB/DIMM is almost at the cheapest cost point, but if it's the
same position that 8GB DIMMs had in in 2015, that's still a doubling
in 4 years, much slower growth than in earlier times. One sign that
the growth has slowed down is the introduction of 24Gb DRAM devices.
In earlier times DRAM grew so fast that nobody bothered with that kind
of stuff, but now, with 32Gb devices maybe 2 years away, they have a
place in the market.

Back to Moore: his predictions were for 10 years, so the 1975 version
of his law only predicted the development until 1985. And I think it
held up much longer than that.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

anton@mips.complang.tuwien.ac.at (Anton Ertl) writes:
>Quadibloc <jsavard@ecn.ab.ca> writes:
>>Of course, I speak of Gordon Moore, who did not live to see Moore's Law
>>come to an end:
>
>At Intel it has slowed down since about 2015:
>
>32nm 2010 Westmere (2011 Sandy Bridge)
>22nm 2012 Ivy Bridge (2013 Haswell)
>14nm 2014 Broadwell
>10nm 2019 Ice Lake (2018 Cannon Lake)
>
>Abd 10nm (renamed into Intel 7) is what they are still delivering (of
>course, with improvements since 2019).

Our latest chip taped out at 5nm. The next will be 3nm. The rest of
the world is head of Intel.

AMD tapes out the processor chiplet at the most advanced node, and
the I/O chiplet at the next older node.

On Sunday, March 26, 2023 at 6:29:03 PM UTC+3, Scott Lurndal wrote:
> an...@mips.complang.tuwien.ac.at (Anton Ertl) writes:
> >Quadibloc <jsa...@ecn.ab.ca> writes:
> >>Of course, I speak of Gordon Moore, who did not live to see Moore's Law
> >>come to an end:
> >
> >At Intel it has slowed down since about 2015:
> >
> >32nm 2010 Westmere (2011 Sandy Bridge)
> >22nm 2012 Ivy Bridge (2013 Haswell)
> >14nm 2014 Broadwell
> >10nm 2019 Ice Lake (2018 Cannon Lake)
> >
> >Abd 10nm (renamed into Intel 7) is what they are still delivering (of
> >course, with improvements since 2019).
> Our latest chip taped out at 5nm. The next will be 3nm. The rest of
> the world is head of Intel.
>
> AMD tapes out the processor chiplet at the most advanced node, and
> the I/O chiplet at the next older node.

7nm,5nm,3nm - those are just names.
TSMC 3nm is not even close to being 5.4 times denser than their 7nm.
Especially for SRAM, but for logic too.

Besides, Moore's Law was never about density. It was about number of
transistors that is economically beneficial to put on a single piece
of silicon. This number nowadays doubles much much slower than predicted
by original (12 months) or modified (18 months) Moore's Law.
For all manufacturers, not just for Intel.
If it wasn't the case then nobody would bother with chiplets.

On 3/26/2023 9:18 AM, Michael S wrote:
> On Sunday, March 26, 2023 at 6:29:03 PM UTC+3, Scott Lurndal wrote:
>> an...@mips.complang.tuwien.ac.at (Anton Ertl) writes:
>>> Quadibloc <jsa...@ecn.ab.ca> writes:
>>>> Of course, I speak of Gordon Moore, who did not live to see Moore's Law
>>>> come to an end:
>>>
>>> At Intel it has slowed down since about 2015:
>>>
>>> 32nm 2010 Westmere (2011 Sandy Bridge)
>>> 22nm 2012 Ivy Bridge (2013 Haswell)
>>> 14nm 2014 Broadwell
>>> 10nm 2019 Ice Lake (2018 Cannon Lake)
>>>
>>> Abd 10nm (renamed into Intel 7) is what they are still delivering (of
>>> course, with improvements since 2019).
>> Our latest chip taped out at 5nm. The next will be 3nm. The rest of
>> the world is head of Intel.
>>
>> AMD tapes out the processor chiplet at the most advanced node, and
>> the I/O chiplet at the next older node.
>
> 7nm,5nm,3nm - those are just names.
> TSMC 3nm is not even close to being 5.4 times denser than their 7nm.
> Especially for SRAM, but for logic too.
>
> Besides, Moore's Law was never about density. It was about number of
> transistors that is economically beneficial to put on a single piece
> of silicon. This number nowadays doubles much much slower than predicted
> by original (12 months) or modified (18 months) Moore's Law.

His 1965 prediction was 18 months, His 1975 update was to two years.

https://en.wikipedia.org/wiki/Moore%27s_law

It is obvious that such exponential growth/shrinkage can't go on forever
(Eventually the size would become much less than one atom at some
point), so the rate should slow down.

Let's see how things work out if we continue Moore's rate reduction or
time to double increase were to continue. I know extrapolating from two
points is very dangerous, but lets see where it takes us. Based on
those two points, the doubling time increases by six months every ten years.

So in 1985, the doubling time would go to 2.5 years.
in 1995, it increases to 3 years, etc.

I am not going to do the "curve fitting", but it might be a better
approximation of reality.

> For all manufacturers, not just for Intel.
> If it wasn't the case then nobody would bother with chiplets.

Yes.

--
- Stephen Fuld
(e-mail address disguised to prevent spam)

On Sunday, March 26, 2023 at 7:39:42 PM UTC+3, Stephen Fuld wrote:
> On 3/26/2023 9:18 AM, Michael S wrote:
> > On Sunday, March 26, 2023 at 6:29:03 PM UTC+3, Scott Lurndal wrote:
> >> an...@mips.complang.tuwien.ac.at (Anton Ertl) writes:
> >>> Quadibloc <jsa...@ecn.ab.ca> writes:
> >>>> Of course, I speak of Gordon Moore, who did not live to see Moore's Law
> >>>> come to an end:
> >>>
> >>> At Intel it has slowed down since about 2015:
> >>>
> >>> 32nm 2010 Westmere (2011 Sandy Bridge)
> >>> 22nm 2012 Ivy Bridge (2013 Haswell)
> >>> 14nm 2014 Broadwell
> >>> 10nm 2019 Ice Lake (2018 Cannon Lake)
> >>>
> >>> Abd 10nm (renamed into Intel 7) is what they are still delivering (of
> >>> course, with improvements since 2019).
> >> Our latest chip taped out at 5nm. The next will be 3nm. The rest of
> >> the world is head of Intel.
> >>
> >> AMD tapes out the processor chiplet at the most advanced node, and
> >> the I/O chiplet at the next older node.
> >
> > 7nm,5nm,3nm - those are just names.
> > TSMC 3nm is not even close to being 5.4 times denser than their 7nm.
> > Especially for SRAM, but for logic too.
> >
> > Besides, Moore's Law was never about density. It was about number of
> > transistors that is economically beneficial to put on a single piece
> > of silicon. This number nowadays doubles much much slower than predicted
> > by original (12 months) or modified (18 months) Moore's Law.
> His 1965 prediction was 18 months, His 1975 update was to two years.
>
> https://en.wikipedia.org/wiki/Moore%27s_law
>
> It is obvious that such exponential growth/shrinkage can't go on forever
> (Eventually the size would become much less than one atom at some
> point), so the rate should slow down.
>
> Let's see how things work out if we continue Moore's rate reduction or
> time to double increase were to continue. I know extrapolating from two
> points is very dangerous, but lets see where it takes us. Based on
> those two points, the doubling time increases by six months every ten years.
>
> So in 1985, the doubling time would go to 2.5 years.
> in 1995, it increases to 3 years, etc.
>
> I am not going to do the "curve fitting", but it might be a better
> approximation of reality.

I don't think so.
1990 to 2005 were years of very quick doublings. At least as quick as
1975-1990 if not faster.

> > For all manufacturers, not just for Intel.
> > If it wasn't the case then nobody would bother with chiplets.
> Yes.
>
>
>
> --
> - Stephen Fuld
> (e-mail address disguised to prevent spam)

Stephen Fuld <sfuld@alumni.cmu.edu.invalid> writes:
>On 3/26/2023 9:18 AM, Michael S wrote:
>
>> For all manufacturers, not just for Intel.
>> If it wasn't the case then nobody would bother with chiplets.
>
>Yes.

It seems to me that it is as much _area_ as _density_ that is driving
chiplets. Flexibility, as well. And cost. And fab capacity.

Need more cores? Add
a chiplet. Need custom I/O devices or coprocessors? Use one
or more I/O chiplet(s) with an existing processor chiplet.
Given modern SERDES (e.g. 112Gb XSR), chiplet to chiplet
latency is more than managable.

Mix and match 14nm/10nm/7nm/3nm chiplets in the same package for
cost savings (3nm/2nm masks aren't cheap).

On 3/26/2023 10:34 AM, Michael S wrote:
> On Sunday, March 26, 2023 at 7:39:42 PM UTC+3, Stephen Fuld wrote:
>> On 3/26/2023 9:18 AM, Michael S wrote:
>>> On Sunday, March 26, 2023 at 6:29:03 PM UTC+3, Scott Lurndal wrote:
>>>> an...@mips.complang.tuwien.ac.at (Anton Ertl) writes:
>>>>> Quadibloc <jsa...@ecn.ab.ca> writes:
>>>>>> Of course, I speak of Gordon Moore, who did not live to see Moore's Law
>>>>>> come to an end:
>>>>>
>>>>> At Intel it has slowed down since about 2015:
>>>>>
>>>>> 32nm 2010 Westmere (2011 Sandy Bridge)
>>>>> 22nm 2012 Ivy Bridge (2013 Haswell)
>>>>> 14nm 2014 Broadwell
>>>>> 10nm 2019 Ice Lake (2018 Cannon Lake)
>>>>>
>>>>> Abd 10nm (renamed into Intel 7) is what they are still delivering (of
>>>>> course, with improvements since 2019).
>>>> Our latest chip taped out at 5nm. The next will be 3nm. The rest of
>>>> the world is head of Intel.
>>>>
>>>> AMD tapes out the processor chiplet at the most advanced node, and
>>>> the I/O chiplet at the next older node.
>>>
>>> 7nm,5nm,3nm - those are just names.
>>> TSMC 3nm is not even close to being 5.4 times denser than their 7nm.
>>> Especially for SRAM, but for logic too.
>>>
>>> Besides, Moore's Law was never about density. It was about number of
>>> transistors that is economically beneficial to put on a single piece
>>> of silicon. This number nowadays doubles much much slower than predicted
>>> by original (12 months) or modified (18 months) Moore's Law.
>> His 1965 prediction was 18 months, His 1975 update was to two years.
>>
>> https://en.wikipedia.org/wiki/Moore%27s_law
>>
>> It is obvious that such exponential growth/shrinkage can't go on forever
>> (Eventually the size would become much less than one atom at some
>> point), so the rate should slow down.
>>
>> Let's see how things work out if we continue Moore's rate reduction or
>> time to double increase were to continue. I know extrapolating from two
>> points is very dangerous, but lets see where it takes us. Based on
>> those two points, the doubling time increases by six months every ten years.
>>
>> So in 1985, the doubling time would go to 2.5 years.
>> in 1995, it increases to 3 years, etc.
>>
>> I am not going to do the "curve fitting", but it might be a better
>> approximation of reality.
>
> I don't think so.
> 1990 to 2005 were years of very quick doublings. At least as quick as
> 1975-1990 if not faster.

So that would favor an S shaped curve, perhaps something like the Bass
diffusion model, or the modeling of things like infection rates.

I am not sure how important it is to model the growth, but it is fun! :-)

--
- Stephen Fuld
(e-mail address disguised to prevent spam)

Stephen Fuld wrote:
> On 3/26/2023 9:18 AM, Michael S wrote:
>> On Sunday, March 26, 2023 at 6:29:03 PM UTC+3, Scott Lurndal wrote:
>>> an...@mips.complang.tuwien.ac.at (Anton Ertl) writes:
>>>> Quadibloc <jsa...@ecn.ab.ca> writes:
>>>>> Of course, I speak of Gordon Moore, who did not live to see Moore's
>>>>> Law
>>>>> come to an end:
>>>>
>>>> At Intel it has slowed down since about 2015:
>>>>
>>>> 32nm 2010 Westmere (2011 Sandy Bridge)
>>>> 22nm 2012 Ivy Bridge (2013 Haswell)
>>>> 14nm 2014 Broadwell
>>>> 10nm 2019 Ice Lake (2018 Cannon Lake)
>>>>
>>>> Abd 10nm (renamed into Intel 7) is what they are still delivering (of
>>>> course, with improvements since 2019).
>>> Our latest chip taped out at 5nm. The next will be 3nm. The rest of
>>> the world is head of Intel.
>>>
>>> AMD tapes out the processor chiplet at the most advanced node, and
>>> the I/O chiplet at the next older node.
>>
>> 7nm,5nm,3nm - those are just names.
>> TSMC 3nm is not even close to being 5.4 times denser than their 7nm.
>> Especially for SRAM, but for logic too.
>>
>> Besides, Moore's Law was never about density. It was about number of
>> transistors that is economically beneficial to put on a single piece
>> of silicon. This number nowadays doubles much much slower than predicted
>> by original (12 months) or modified (18 months) Moore's Law.
>
> His 1965 prediction was 18 months,  His 1975 update was to two years.
>
> https://en.wikipedia.org/wiki/Moore%27s_law
>
> It is obvious that such exponential growth/shrinkage can't go on forever
> (Eventually the size would become much less than one atom at some
> point), so the rate should slow down.
>
> Let's see how things work out if we continue Moore's rate reduction or
> time to double increase were to continue.  I know extrapolating from two
> points is very dangerous, but lets see where it takes us.  Based on
> those two points, the doubling time increases by six months every ten
> years.
>
> So in 1985, the doubling time would go to 2.5 years.
> in 1995, it increases to 3 years, etc.
>
> I am not going to do the "curve fitting", but it might be a better
> approximation of reality.

Internally in Intel x86 development, the law was taken not just as a
prediction but as an absolute requirement.

I once did a curve fitting of the number of transistors in each new x86,
from the original 8086 up to 2000(+?), and on a log scale this was
extremely close to a straight line, with a doubling time of 2.00 years:

A single small dip when single-core ran out of headroom, but then dual
and quad cores picked right up as if nothing had happened.

Obviously, any new model wasn't done until they managed to hit that line.

Terje

--
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"

On 3/26/2023 1:35 PM, Stephen Fuld wrote:
> On 3/26/2023 10:34 AM, Michael S wrote:
>> On Sunday, March 26, 2023 at 7:39:42 PM UTC+3, Stephen Fuld wrote:
>>> On 3/26/2023 9:18 AM, Michael S wrote:
>>>> On Sunday, March 26, 2023 at 6:29:03 PM UTC+3, Scott Lurndal wrote:
>>>>> an...@mips.complang.tuwien.ac.at (Anton Ertl) writes:
>>>>>> Quadibloc <jsa...@ecn.ab.ca> writes:
>>>>>>> Of course, I speak of Gordon Moore, who did not live to see
>>>>>>> Moore's Law
>>>>>>> come to an end:
>>>>>>
>>>>>> At Intel it has slowed down since about 2015:
>>>>>>
>>>>>> 32nm 2010 Westmere (2011 Sandy Bridge)
>>>>>> 22nm 2012 Ivy Bridge (2013 Haswell)
>>>>>> 14nm 2014 Broadwell
>>>>>> 10nm 2019 Ice Lake (2018 Cannon Lake)
>>>>>>
>>>>>> Abd 10nm (renamed into Intel 7) is what they are still delivering (of
>>>>>> course, with improvements since 2019).
>>>>> Our latest chip taped out at 5nm. The next will be 3nm. The rest of
>>>>> the world is head of Intel.
>>>>>
>>>>> AMD tapes out the processor chiplet at the most advanced node, and
>>>>> the I/O chiplet at the next older node.
>>>>
>>>> 7nm,5nm,3nm - those are just names.
>>>> TSMC 3nm is not even close to being 5.4 times denser than their 7nm.
>>>> Especially for SRAM, but for logic too.
>>>>
>>>> Besides, Moore's Law was never about density. It was about number of
>>>> transistors that is economically beneficial to put on a single piece
>>>> of silicon. This number nowadays doubles much much slower than
>>>> predicted
>>>> by original (12 months) or modified (18 months) Moore's Law.
>>> His 1965 prediction was 18 months, His 1975 update was to two years.
>>>
>>> https://en.wikipedia.org/wiki/Moore%27s_law
>>>
>>> It is obvious that such exponential growth/shrinkage can't go on forever
>>> (Eventually the size would become much less than one atom at some
>>> point), so the rate should slow down.
>>>
>>> Let's see how things work out if we continue Moore's rate reduction or
>>> time to double increase were to continue. I know extrapolating from two
>>> points is very dangerous, but lets see where it takes us. Based on
>>> those two points, the doubling time increases by six months every ten
>>> years.
>>>
>>> So in 1985, the doubling time would go to 2.5 years.
>>> in 1995, it increases to 3 years, etc.
>>>
>>> I am not going to do the "curve fitting", but it might be a better
>>> approximation of reality.
>>
>> I don't think so.
>> 1990 to 2005 were years of very quick doublings. At least as quick as
>> 1975-1990 if not faster.
>
>
> So that would favor an S shaped curve, perhaps something like the Bass
> diffusion model, or the modeling of things like infection rates.
>
> I am not sure how important it is to model the growth, but it is fun!  :-)
>

My experience also seems to imply a more S-curve shaped model.

During my childhood, PCs changed rapidly, but by the time I was in
high-school until now, changes are more minor:
More RAM, Bigger HDDs;
More cores;
The CRT -> LCD transition;
Loss of 3.5" floppy drives and similar.

However, I have noted that despite CPU MHz mostly hitting a wall 2
decades ago, a modern CPU is still somewhat faster than something from
20 years ago (noting the seemingly massive speed difference between them).

Though, the main "obvious" difference in terms of benchmarks is that my
current PC has well over an order of magnitude more RAM bandwidth,
besides also having a 96 times more RAM, ...

Whereas, say, BJX2 core (on my newer QMTECH board), vs laptop:
MHz: 34x difference (74x vs modern PC);
RAM size: 2x difference (192x vs modern PC);
DRAM speed: 9x difference (235x vs modern PC);
L1 memcpy speed: ~ 3x (161x vs modern PC).
...

In terms of running a neural net on BJX2 via SIMD vs x87 on the laptop,
it is pretty close to break-even (somehow). It seems like all the
relative overheads of x87 are enough to offset the CPU clock-speed
difference.

Doing Binary16 math via software emulation is seemingly enough of a
handicap to get my Ryzen into this area as well (though, for native
floating point, it is "no contest").

Despite having a slower CPU, a RasPi2 is competitive in terms of general
performance with the laptop, though benchmarks also showed the RasPi2 as
having somewhat better memory performance than the laptop.

I suspect for L1 copies, it is partly a factor of being mostly limited
to 32 bit load/store operations and a limited number of CPU registers
(being able to load/store 128 bits per clock-cycle and fit ~ 16x more
data into a fully pipelined block-copy seemingly offsetting some of the
clock-speed difference for this task).

Laptop is generally fast enough to run Quake 3 and Half-Life pretty well
(Half-Life 2 sorta, but it is a bit prone to having generally poor
framerates; much newer: unusable or doesn't run).

A newer (Vista era) laptop has seemingly significantly better CPU
performance (and much faster memcpy as well), though is kinda limited
due to its (kinda terrible) Intel GMA graphics chip (so still doesn't
effectively run games much newer than Quake 3 and Half-Life...). Between
them, there is a roughly 24% difference in terms of CPU clock speed.

This being because RAM and HDDs have been continuing to improve until a
lot more recently.

But, it doesn't quite make sense, as working backwards, it implies that
the actual PCs from my childhood "totally sucked" in terms of
performance, but they still did an OK job at running Doom and Quake and
similar.

Though, Doom and Quake seem to care a lot more about cache miss latency
than memcpy bandwidth or similar (and this is currently a weak area in
my case).

But, I don't really have any RAM benchmark numbers for early 90s PCs to
compare against.

Though, distant childhood memories were that Quake was still mostly
unplayable on a 486DX2 as well, so maybe I am not "that" far behind.

But, I guess some of this maybe also implies I probably couldn't make
something like my current BJX2 core on an early 90s process node either
(and/or, this might be "pretty hardcore" if it could actually run as-is
at more modern clock-speeds).

....

Stephen Fuld <sfuld@alumni.cmu.edu.invalid> writes:
>On 3/26/2023 9:18 AM, Michael S wrote:
>> Besides, Moore's Law was never about density. It was about number of
>> transistors that is economically beneficial to put on a single piece
>> of silicon. This number nowadays doubles much much slower than predicted
>> by original (12 months) or modified (18 months) Moore's Law.
>
>His 1965 prediction was 18 months, His 1975 update was to two years.
>
>https://en.wikipedia.org/wiki/Moore%27s_law

Actually that source says: 1965 doubling every 12 months, 1975 every 2
years.

IIRC his 1965 prediction claimed that the following components double every three years:

1) minimum feature size

2) design cleverness (reflected in more transistors per feature-size-scaled area).

3) bigger dies

Intel had a pretty steady pace at a new process (smaller feature size)
every two years for a long time, they even did the tick-tock model
based on this pace. From what I read, the actual minimum feature size
in recent processes is no longer in line with the name, but the design
cleverness (and more metal layers) let the transistor density still
increase by a factor of 2 or so with each process. I wonder how much
it increased while the process name still reflected minimum feature
size. Interestingly, IIRC Moore wrote in 1975 that the design
cleverness component had been exhausted by 1975.

Die size has not really increased. Reticle size has been limited to
similar sizes for many years, and even when not running into reticle
limits, die sizes tended not to increase; actually the dies for
Intel's mainstream CPUs became smaller and smaller until it reached a
low with Skylake and Kaby Lake; then, it seems, competetive forces (i.e., Ryzen) and
the troubles with Intels 10nm process forced the dies to grow again.

>Let's see how things work out if we continue Moore's rate reduction or
>time to double increase were to continue. I know extrapolating from two
>points is very dangerous, but lets see where it takes us. Based on
>those two points, the doubling time increases by six months every ten years.

No, Intel's shrinks followed the 2-year schedule for a long time, and
only ran into trouble in the 2010s; and as mentioned above, this might
have meant more than a factor of 2 in transistors every two years.

It seems to me that the slowdown is much more sudden, like it was for
clock rate: In the 1990s we had very fast doubling of clock rates,
then it slowed down a lot when feature sizes became smaller than
180nm. 130nm still saw a nice speedup, but less, and 90nm saw very
little speedup
<http://www.complang.tuwien.ac.at/anton/cpu-clocks.html>.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

On Sunday, March 26, 2023 at 4:47:34 PM UTC-5, Anton Ertl wrote:
> Stephen Fuld <sf...@alumni.cmu.edu.invalid> writes:
> >On 3/26/2023 9:18 AM, Michael S wrote:
> >> Besides, Moore's Law was never about density. It was about number of
> >> transistors that is economically beneficial to put on a single piece
> >> of silicon. This number nowadays doubles much much slower than predicted
> >> by original (12 months) or modified (18 months) Moore's Law.
> >
> >His 1965 prediction was 18 months, His 1975 update was to two years.
> >
> >https://en.wikipedia.org/wiki/Moore%27s_law
> Actually that source says: 1965 doubling every 12 months, 1975 every 2
> years.
>
> IIRC his 1965 prediction claimed that the following components double every three years:
>
> 1) minimum feature size
>
> 2) design cleverness (reflected in more transistors per feature-size-scaled area).
>
> 3) bigger dies
>
> Intel had a pretty steady pace at a new process (smaller feature size)
> every two years for a long time, they even did the tick-tock model
> based on this pace. From what I read, the actual minimum feature size
> in recent processes is no longer in line with the name, but the design
> cleverness (and more metal layers) let the transistor density still
> increase by a factor of 2 or so with each process. I wonder how much
> it increased while the process name still reflected minimum feature
> size. Interestingly, IIRC Moore wrote in 1975 that the design
> cleverness component had been exhausted by 1975.
<
That is a surprise to we down in the trenches..........
>
> Die size has not really increased. Reticle size has been limited to
> similar sizes for many years, and even when not running into reticle
> limits, die sizes tended not to increase; actually the dies for
> Intel's mainstream CPUs became smaller and smaller until it reached a
> low with Skylake and Kaby Lake; then, it seems, competetive forces (i.e., Ryzen) and
> the troubles with Intels 10nm process forced the dies to grow again.
<
Die sizes pretty much stayed the same due to the economy of yields
(1980-1995) then power dissipation (1995-2010), then pure cost
(mask sets and FAB costs smaller than 14nm)
<
Recently (post 2015) die sizes are on the move again.
<
> >Let's see how things work out if we continue Moore's rate reduction or
> >time to double increase were to continue. I know extrapolating from two
> >points is very dangerous, but lets see where it takes us. Based on
> >those two points, the doubling time increases by six months every ten years.
<
> No, Intel's shrinks followed the 2-year schedule for a long time, and
> only ran into trouble in the 2010s; and as mentioned above, this might
> have meant more than a factor of 2 in transistors every two years.
<
When I was at AMD we got better transistors 3 or 4 times per year (this
was pre Global Foundry) and frequency increases at about the same rate.
>
> It seems to me that the slowdown is much more sudden, like it was for
> clock rate: In the 1990s we had very fast doubling of clock rates,
<
This is an outgrowth of having a whole generation of fully pipeline
architectures (RISC revolution) kicking the CISC guys and their cubic
dollars budgets into high gear.
<
> then it slowed down a lot when feature sizes became smaller than
> 180nm. 130nm still saw a nice speedup, but less, and 90nm saw very
> little speedup
<
Power and wire delay.
<
> <http://www.complang.tuwien.ac.at/anton/cpu-clocks.html>.
> - anton
> --
> 'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
> Mitch Alsup, <c17fcd89-f024-40e7...@googlegroups.com>

On 3/26/2023 2:16 PM, Anton Ertl wrote:
> Stephen Fuld <sfuld@alumni.cmu.edu.invalid> writes:
>> On 3/26/2023 9:18 AM, Michael S wrote:
>>> Besides, Moore's Law was never about density. It was about number of
>>> transistors that is economically beneficial to put on a single piece
>>> of silicon. This number nowadays doubles much much slower than predicted
>>> by original (12 months) or modified (18 months) Moore's Law.
>>
>> His 1965 prediction was 18 months, His 1975 update was to two years.
>>
>> https://en.wikipedia.org/wiki/Moore%27s_law
>
> Actually that source says: 1965 doubling every 12 months, 1975 every 2
> years.

You're right, of course. Sorry for the error.

--
- Stephen Fuld
(e-mail address disguised to prevent spam)