ALLFILES.TXT says:
(http://greyghost.mooo.com/pccbbs/allfiles.txt)

> disable.zip 356 03-12-82 Patch for Model 77

I assume they mean *PS/2* Model 77, despite the strange datestamp (1982
- that would make it much older than almost all the other files).

But if so, then what is the patch for and what exactly does it disable?
I can't find a word about it anywhere...

Since the program is literally only 7 bytes/4 instructions long, doesn't
contain any copyrighted material, and has no commercial value at this
point, I think it's ok to post its complete listing here.

DISABLE.COM says:
(http://greyghost.mooo.com/pccBBS/system_specific/disable.zip)

> in al, 0E2h
> or al, 01000000b
> out 0E2h, al
> retn

As we can see, it just sets bit 6 of the register at I/O addr. E2h. The
Exh range is usually assigned to the memory controller, at least in the
PS/2 world. But unfortunately we don't have the Model 77 Tech. Ref., so
I'm not sure what the bit controls in that system.

In some older PS/2 machines (Model 80 T3, 70 T3&T4...) bit 6 of E2h was
used to enable the -PREEMPT signal:

Model 80 Tech. Ref. page 64 physical says:
(https://ardent-tool.com/docs/pdf/m80_ssi.pdf#page=64)

> Bit 6: This bit controls the preempt support for the system
> microprocessor on the Type 3 system board. When this
> bit is set to 1, preempt is disabled. When this bit is set to
> 0, system logic activates the ‘-preempt’ signal when the
> system microprocessor accesses a memory location not
> satisfied in the cache (cache miss).

The Type 1 Model 90/95 Processor Complex uses the same bit to flush the
L2 cache (and so does the Type 4 complex it seems).

Model 90 Tech. Ref., page 88 physical:
(https://ardent-tool.com/docs/pdf/m90_ssi.pdf#page=88)

> Bit 6: This bit controls the flushing of the level 2 cache.
> When the bit is set to 0, the cache is placed and held in the
> flushed state. When this bit is set to 1, the state of the
> level 2 cache is controlled by bit 5.

I'm not sure if its meaning in Model 77 (Bermuda I assume?) matches
either of the two cases above, but the former would make more sense to
me in this context (if nothing else, the program is called DISABLE.COM
and it sets the bit to 1 - matching the logical states of the -Preempt
Enable bit). But it could be controlling something completely different
in the Model 77...

Thoughts?

We could either test it and see if it makes any visible/measurable
difference, or check the 77 FW for clues (when we are done with the T0-
stuff...).

The COM file itself is from 1994 it seems... which sounds more reasonable.

On 1.8.2021 0:33, Tomas Slavotinek wrote:
> ALLFILES.TXT says:
> (http://greyghost.mooo.com/pccbbs/allfiles.txt)
>
>> disable.zip 356 03-12-82 Patch for Model 77
>
> I assume they mean *PS/2* Model 77, despite the strange datestamp (1982
> - that would make it much older than almost all the other files).
>
> But if so, then what is the patch for and what exactly does it disable?
> I can't find a word about it anywhere...
>
> Since the program is literally only 7 bytes/4 instructions long, doesn't
> contain any copyrighted material, and has no commercial value at this
> point, I think it's ok to post its complete listing here.
>
> DISABLE.COM says:
> (http://greyghost.mooo.com/pccBBS/system_specific/disable.zip)
>
>> in al, 0E2h
>> or al, 01000000b
>> out 0E2h, al
>> retn
>
> As we can see, it just sets bit 6 of the register at I/O addr. E2h. The
> Exh range is usually assigned to the memory controller, at least in the
> PS/2 world. But unfortunately we don't have the Model 77 Tech. Ref., so
> I'm not sure what the bit controls in that system.
>
> In some older PS/2 machines (Model 80 T3, 70 T3&T4...) bit 6 of E2h was
> used to enable the -PREEMPT signal:
>
> Model 80 Tech. Ref. page 64 physical says:
> (https://ardent-tool.com/docs/pdf/m80_ssi.pdf#page=64)
>
>> Bit 6: This bit controls the preempt support for the system
>> microprocessor on the Type 3 system board. When this
>> bit is set to 1, preempt is disabled. When this bit is set to
>> 0, system logic activates the ‘-preempt’ signal when the
>> system microprocessor accesses a memory location not
>> satisfied in the cache (cache miss).
>
> The Type 1 Model 90/95 Processor Complex uses the same bit to flush the
> L2 cache (and so does the Type 4 complex it seems).
>
> Model 90 Tech. Ref., page 88 physical:
> (https://ardent-tool.com/docs/pdf/m90_ssi.pdf#page=88)
>
>> Bit 6: This bit controls the flushing of the level 2 cache.
>> When the bit is set to 0, the cache is placed and held in the
>> flushed state. When this bit is set to 1, the state of the
>> level 2 cache is controlled by bit 5.
>
> I'm not sure if its meaning in Model 77 (Bermuda I assume?) matches
> either of the two cases above, but the former would make more sense to
> me in this context (if nothing else, the program is called DISABLE.COM
> and it sets the bit to 1 - matching the logical states of the -Preempt
> Enable bit). But it could be controlling something completely different
> in the Model 77...
>
> Thoughts?
>
> We could either test it and see if it makes any visible/measurable
> difference, or check the 77 FW for clues (when we are done with the T0-
> stuff...).
>
>
>

Tom, if the file date is 1994, what 77 models were released around that
time?

L2? Lacuna. I'm not thinking that the Bermuda is involved.

On 7/31/2021 17:58, Tomas Slavotinek wrote:
> The COM file itself is from 1994 it seems... which sounds more reasonable.
>
> On 1.8.2021 0:33, Tomas Slavotinek wrote:
>> ALLFILES.TXT says:
>> (http://greyghost.mooo.com/pccbbs/allfiles.txt)
>>
>>> disable.zip 356 03-12-82 Patch for Model 77
>>
>> I assume they mean *PS/2* Model 77, despite the strange datestamp (1982
>> - that would make it much older than almost all the other files).
>>
>> But if so, then what is the patch for and what exactly does it disable?
>> I can't find a word about it anywhere...
>>
>> Since the program is literally only 7 bytes/4 instructions long, doesn't
>> contain any copyrighted material, and has no commercial value at this
>> point, I think it's ok to post its complete listing here.
>>
>> DISABLE.COM says:
>> (http://greyghost.mooo.com/pccBBS/system_specific/disable.zip)
>>
>>> in al, 0E2h
>>> or al, 01000000b
>>> out 0E2h, al
>>> retn
>>
>> As we can see, it just sets bit 6 of the register at I/O addr. E2h. The
>> Exh range is usually assigned to the memory controller, at least in the
>> PS/2 world. But unfortunately we don't have the Model 77 Tech. Ref., so
>> I'm not sure what the bit controls in that system.
>>
>> In some older PS/2 machines (Model 80 T3, 70 T3&T4...) bit 6 of E2h was
>> used to enable the -PREEMPT signal:
>>
>> Model 80 Tech. Ref. page 64 physical says:
>> (https://ardent-tool.com/docs/pdf/m80_ssi.pdf#page=64)
>>
>>> Bit 6: This bit controls the preempt support for the system
>>> microprocessor on the Type 3 system board. When this
>>> bit is set to 1, preempt is disabled. When this bit is set to
>>> 0, system logic activates the ‘-preempt’ signal when the
>>> system microprocessor accesses a memory location not
>>> satisfied in the cache (cache miss).
>>
>> The Type 1 Model 90/95 Processor Complex uses the same bit to flush the
>> L2 cache (and so does the Type 4 complex it seems).
>>
>> Model 90 Tech. Ref., page 88 physical:
>> (https://ardent-tool.com/docs/pdf/m90_ssi.pdf#page=88)
>>
>>> Bit 6: This bit controls the flushing of the level 2 cache.
>>> When the bit is set to 0, the cache is placed and held in the
>>> flushed state. When this bit is set to 1, the state of the
>>> level 2 cache is controlled by bit 5.
>>
>> I'm not sure if its meaning in Model 77 (Bermuda I assume?) matches
>> either of the two cases above, but the former would make more sense to
>> me in this context (if nothing else, the program is called DISABLE.COM
>> and it sets the bit to 1 - matching the logical states of the -Preempt
>> Enable bit). But it could be controlling something completely different
>> in the Model 77...
>>
>> Thoughts?
>>
>> We could either test it and see if it makes any visible/measurable
>> difference, or check the 77 FW for clues (when we are done with the T0-
>> stuff...).
>>
>>
>>
>

https://www-01.ibm.com/common/ssi/ShowDoc.wss?docURL=/common/ssi/rep_ca/6/897/ENUS194-206/index.html&request_locale=en

I wonder if it applied to the L2 COAST module? Remember there were
issues with WT / WB, interposers, and voodoo...

On 7/31/2021 19:06, Louis Ohland wrote:
>
> https://www-01.ibm.com/common/ssi/ShowDoc.wss?docURL=/common/ssi/rep_ca/6/897/ENUS194-206/index.html&request_locale=en
>

Yeah 1994 definitely points more towards the Lacuna systems. I didn't
notice the the file date originally...

The binary is from 24 May 1994 and the (completely worthless) readme
file is dated 22 June 1994, so the date information stored in the ZIP is
probably correct.

Anyway, changing the state of the cache(s) is usually more complex than
setting a single bit. And the BIOS already provides an interface for all
common cache operations - Int 15h function C8h subfuctions 00 - 06h. So
what they are doing here is a little bit strange if it indeed involves
the L2 cache...

On 1.8.2021 2:08, Louis Ohland wrote:
> I wonder if it applied to the L2 COAST module? Remember there were
> issues with WT / WB, interposers, and voodoo...
>
> On 7/31/2021 19:06, Louis Ohland wrote:
>>
>> https://www-01.ibm.com/common/ssi/ShowDoc.wss?docURL=/common/ssi/rep_ca/6/897/ENUS194-206/index.html&request_locale=en
>>
>