On 6/30/2022 6:17 PM, Dennis Bush wrote:
> On Thursday, June 30, 2022 at 7:11:01 PM UTC-4, olcott wrote:
>> On 6/30/2022 6:05 PM, Dennis Bush wrote:
>>> On Thursday, June 30, 2022 at 6:57:12 PM UTC-4, olcott wrote:
>>>> On 6/30/2022 5:26 PM, Dennis Bush wrote:
>>>>> On Thursday, June 30, 2022 at 6:23:56 PM UTC-4, olcott wrote:
>>>>>> On 6/30/2022 5:09 PM, Dennis Bush wrote:
>>>>>>> On Thursday, June 30, 2022 at 5:52:37 PM UTC-4, olcott wrote:
>>>>>>>> On 6/30/2022 3:50 PM, Dennis Bush wrote:
>>>>>>>>> On Thursday, June 30, 2022 at 4:22:57 PM UTC-4, olcott wrote:
>>>>>>>>>> On 6/30/2022 11:55 AM, Dennis Bush wrote:
>>>>>>>>>>> On Thursday, June 30, 2022 at 12:43:17 PM UTC-4, olcott wrote:
>>>>>>>>>>>> On 6/30/2022 11:34 AM, Dennis Bush wrote:
>>>>>>>>>>>>> On Thursday, June 30, 2022 at 12:15:58 PM UTC-4, olcott wrote:
>>>>>>>>>>>>>> On 6/30/2022 10:40 AM, Dennis Bush wrote:
>>>>>>>>>>>>>>> On Thursday, June 30, 2022 at 11:36:43 AM UTC-4, olcott wrote:
>>>>>>>>>>>>>>>> On 6/30/2022 7:12 AM, Dennis Bush wrote:
>>>>>>>>>>>>>>>>> On Thursday, June 30, 2022 at 12:59:38 AM UTC-4, olcott wrote:
>>>>>>>>>>>>>>>>>> On 6/29/2022 11:51 PM, Dennis Bush wrote:
>>>>>>>>>>>>>>>>>>> On Thursday, June 30, 2022 at 12:42:59 AM UTC-4, olcott wrote:
>>>>>>>>>>>>>>>>>>>> On 6/29/2022 9:02 AM, Dennis Bush wrote:
>>>>>>>>>>>>>>>>>>>>> On Wednesday, June 29, 2022 at 9:44:39 AM UTC-4, olcott wrote:
>>>>>>>>>>>>>>>>>>>>>> On 6/28/2022 8:44 PM, Dennis Bush wrote:
>>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>>>>>>> Every simulating halt decider correctly simulates its input until it
>>>>>>>>>>>>>>>>>>>>>> correctly determines that this simulated input would never reach its
>>>>>>>>>>>>>>>>>>>>>> final state.
>>>>>>>>>>>>>>>>>>>>>> I don't know why you keep making the ridiculous assertion that a
>>>>>>>>>>>>>>>>>>>>>> simulating halt decider cannot possibly predict/determine that its
>>>>>>>>>>>>>>>>>>>>>> complete and correct x86 emulation of its input would never reach the
>>>>>>>>>>>>>>>>>>>>>> "ret" instruction of this input.
>>>>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>>>>>> But Ha doesn't *do* a complete and correct emulation of its input as per its fixed algorithm, so to say what the complete and correct emulation of the input to Ha(Pa,Pa) by Ha is, is simply nonsense.
>>>>>>>>>>>>>>>>>>>> To continue to insist that a simulating halt decider cannot correctly
>>>>>>>>>>>>>>>>>>>> predict (in a finite number of steps) that its complete and correct x86
>>>>>>>>>>>>>>>>>>>> emulation of its input
>>>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>>>> Which does not exist because Ha aborts and therefore does not do a complete and correct x86 emulation.
>>>>>>>>>>>>>>>>>> We are taking that what you are saying means that you believe it is
>>>>>>>>>>>>>>>>>> impossible for H to correctly determine that Infinite_Loop() never halts.
>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>> No, you're saying that the correctness criteria for Ha(Pa,Pa) is a complete and correct emulation of the input *by Ha*. And because Ha has a fixed algorithm that aborts, Ha does not do a complete and correct emulation of the input.
>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>> And because Ha does not do a complete and correct emulation of the input, what I'm saying is that your correctness criteria simply doesn't exist.
>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>> That is a Jackass (deceptive head games) thing to say when you already
>>>>>>>>>>>>>>>> know that H merely needs to correctly predict what the complete and
>>>>>>>>>>>>>>>> correct x86 emulation of its input would do and it need not actually to
>>>>>>>>>>>>>>>> a complete emulation to do this. EXAMPLE BELOW
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> *The* complete and correct emulation of the input to Ha(Pa,Pa) is performed by UTM(Pa,Pa) which halts, proving that Ha(Pa,Pa)==0 is wrong.
>>>>>>>>>>>>>> The part that you keep erasing proves that you are a liar.
>>>>>>>>>>>>>> You keep erasing it because you know that it proves you are a liar.
>>>>>>>>>>>>>
>>>>>>>>>>>>> Infinite_Loop was previously shown to be irrelevant.
>>>>>>>>>>>>>
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> Changing the subject to a completely different computation UTM(Pa,Pa)
>>>>>>>>>>>>>> than the actual computation Ha(Pa,Pa) is the strawman deception.
>>>>>>>>>>>>>> straw man
>>>>>>>>>>>>>> An intentionally misrepresented proposition that is set up because it is
>>>>>>>>>>>>>> easier to defeat than an opponent's real argument.
>>>>>>>>>>>>>> https://www.lexico.com/en/definition/straw_man
>>>>>>>>>>>>>
>>>>>>>>>>>>> I'm not changing the subject. I'm just going by what you're saying.
>>>>>>>>>>>>>
>>>>>>>>>>>>>> THIS IS NECESSARILY TRUE THUS IMPOSSIBLY FALSE
>>>>>>>>>>>>>> Every simulating halt decider correctly simulates its input until it
>>>>>>>>>>>>>> correctly determines that this simulated input would never reach its
>>>>>>>>>>>>>> final state.
>>>>>>>>>>>>>
>>>>>>>>>>>>> You keep changing this part. Sometimes you say "the" simulated input, sometimes "its" simulated input, sometimes "this" simulated input.
>>>>>>>>>>>>>
>>>>>>>>>>>>> *The* complete and correct simulation of the input to Ha(Pa,Pa) is by definition performed by UTM(Pa,Pa).
>>>>>>>>>>>> That is a lie and you know it.
>>>>>>>>>>>>
>>>>>>>>>>>> The actual behavior of the actual input to H(P,P) is conclusively proven
>>>>>>>>>>>> to diverge from the actual behavior of the actual input to H1(P,P) on
>>>>>>>>>>>> the basis of the semantics of the x86 language.
>>>>>>>>>>>
>>>>>>>>>>> Then what is the first x86 instruction where the behavior of Ha(Pa,Pa) and UTM(Pa,Pa) differ?
>>>>>>>>>>>
>>>>>>>>>> [0000164a][00212749][0021274d] 83c408 add esp,+08
>>>>>>>>>
>>>>>>>>> FALSE
>>>>>>>>>
>>>>>>>>> The simulation performed by Ha is aborted before that instruction can be reached.
>>>>>>>> Aborted or not the above instruction is the first instruction that
>>>>>>>> differs.
>>>>>>>
>>>>>>> That instruction doesn't differ between the two simulations because Ha stopped before it got there.
>>>>>> Perhaps you are simply not bright enough to understand that aborted or
>>>>>> not the emulated input never reaches its "ret" instruction.
>>>>>
>>>>> Then you believe that Ha3(N,5)==0 is correct because the emulated input never reaches its "ret" instruction, correct?
>>>>>
>>>>> If not, then explain in detail why it is wrong. Failure to do so will be taken as you asserting that this is correct.
>>>> The problem is not that you are not bright enough the problem is that
>>>> you are a liar that continues to try and get away with the strawman
>>>> deception.
>>>
>>> You said "aborted or not the emulated input never reaches its "ret" instruction". There is no "not" since the fixed algorithm of Ha aborts, so you're saying that because Ha aborts that causes the "ret" instruction to not be reached which is your criteria for returning 0.
>> *This is necessarily true thus impossibly false*
>> Every simulating halt decider that correctly simulates its input until
>> it correctly determines that this simulated input would never reach its
>> final state, correctly rejects this input as non-halting.
>
> So now you're back to "this" simulated input, which means aborting and reporting non-halting is necessarily correct.
>
> Which means you've just affirmed that you agree that Ha3(N,5)==0 is correct.

A dog is an animal is correct thus anyone that disagrees is necessarily
incorrect.

*This is necessarily true thus impossibly false*
Every simulating halt decider that correctly simulates its input until
it correctly determines that this simulated input would never reach its
final state, correctly rejects this input as non-halting.

That you disagree with necessarily true statements makes you either
lacking sufficient technical skills or a liar.

--
Copyright 2022 Pete Olcott

"Talent hits a target no one else can hit;
Genius hits a target no one else can see."
Arthur Schopenhauer