On Sat, 27 Aug 2022 16:25:44 -0500
olcott <NoOne@NoWhere.com> wrote:

> On 8/27/2022 3:06 PM, Mr Flibble wrote:
> > On Sat, 27 Aug 2022 14:26:36 -0500
> > olcott <NoOne@NoWhere.com> wrote:
> >
> >> On 8/27/2022 2:05 PM, Mr Flibble wrote:
> >>> On Sat, 27 Aug 2022 13:35:12 -0500
> >>> olcott <NoOne@NoWhere.com> wrote:
> >>>
> >>>> On 8/27/2022 1:12 PM, Mr Flibble wrote:
> >>>>> On Sat, 27 Aug 2022 13:08:42 -0500
> >>>>> olcott <NoOne@NoWhere.com> wrote:
> >>>>>
> >>>>>> On 8/27/2022 12:58 PM, Mr Flibble wrote:
> >>>>>>> On Sat, 27 Aug 2022 12:56:31 -0500
> >>>>>>> olcott <NoOne@NoWhere.com> wrote:
> >>>>>>>
> >>>>>>>> On 8/27/2022 12:42 PM, Mr Flibble wrote:
> >>>>>>>>> On Sat, 27 Aug 2022 12:35:44 -0500
> >>>>>>>>> olcott <NoOne@NoWhere.com> wrote:
> >>>>>>>>>
> >>>>>>>>>> On 8/27/2022 12:29 PM, Richard Damon wrote:
> >>>>>>>>>>> On 8/27/22 1:15 PM, olcott wrote:
> >>>>>>>>>>>> On 8/27/2022 12:12 PM, Mr Flibble wrote:
> >>>>>>>>>>>>> On Sat, 27 Aug 2022 11:58:13 -0500
> >>>>>>>>>>>>> olcott <NoOne@NoWhere.com> wrote:
> >>>>>>>>>>>>>
> >>>>>>>>>>>>>> On 8/27/2022 11:28 AM, Mr Flibble wrote:
> >>>>>>>>>>>>>>> Blocking/ignoring your reviewers means only one thing:
> >>>>>>>>>>>>>>> you do not want an honest review of your work and you
> >>>>>>>>>>>>>>> are yourself dishonest.
> >>>>>>>>>>>>>>>
> >>>>>>>>>>>>>>> /Flibble
> >>>>>>>>>>
> >>>>>>>>>> *No one would build a complete operating system as a mere
> >>>>>>>>>> ruse* *No one would build a complete operating system as a
> >>>>>>>>>> mere ruse* *No one would build a complete operating system
> >>>>>>>>>> as a mere ruse* *No one would build a complete operating
> >>>>>>>>>> system as a mere ruse*
> >>>>>>>>>>
> >>>>>>>>>> This is the complete system:
> >>>>>>>>>> https://www.liarparadox.org/2022_08_16.zip
> >>>>>>>>>>
> >>>>>>>>>> Microsoft Visual Studio Community 2017
> >>>>>>>>>> https://visualstudio.microsoft.com/vs/older-downloads/
> >>>>>>>>>
> >>>>>>>>> Ah so you are claiming to be a member of the Terry A. Davis
> >>>>>>>>> (R.I.P) club? It all makes sense now: you are simply a
> >>>>>>>>> nutter.
> >>>>>>>>>
> >>>>>>>>> /Flibble
> >>>>>>>>>
> >>>>>>>>
> >>>>>>>> void Px(void (*x)())
> >>>>>>>> {
> >>>>>>>> (void) H(x, x);
> >>>>>>>> return;
> >>>>>>>> }
> >>>>>>>>
> >>>>>>>> int main()
> >>>>>>>> {
> >>>>>>>> Output("Input_Halts = ", H(Px, Px));
> >>>>>>>> }
> >>>>>>>>
> >>>>>>>> Flibble does not understand that
> >>>>>>>>
> >>>>>>>> when simulating halt decider H(Px,Px) correctly simulates its
> >>>>>>>> input the "return" instruction of the simulated Px in
> >>>>>>>> unreachable by this simulated Px.
> >>>>>>>
> >>>>>>> Px should always halt you nutter:
> >>>>>>
> >>>>>> It is a matter of easily verified fact the Px never reaches its
> >>>>>> final state. I have fully operational software that proves
> >>>>>> this. All that you have is misconceptions and empty rhetoric.
> >>>>>
> >>>>> Px halts if H is designed correctly
> >>>>
> >>>> INCORRECT
> >>>>
> >>>>> (a valid halt decider always
> >>>>> returns a result to its caller) ergo H is not designed
> >>>>> correctly.
> >>>>
> >>>> CORRECT
> >>>>
> >>>>> Simple undeniable logic, dear.
> >>>>>
> >>>>> /Flibble
> >>>>>
> >>>>
> >>>> You just said that the non-halting input to a simulating halt
> >>>> decider must halt, that is a contradiction.
> >>>
> >>> No, dear, I am saying that your simulating halt decider is not a
> >>> valid halt decider as it doesn't return a result to its caller,
> >>
> >> In other words you believe that a function called in (what is
> >> essentially) infinite recursion must return to its caller even
> >> though it is an axiom to no function called in infinite recursion
> >> ever returns to its caller?
> >>
> >> When any system of axioms has a pair of axioms that contradict each
> >> other at most one of these axioms is correct.
> >>
> >> (a) Deciders must always return to their caller.
> >> (b) No function called in infinite recursion returns to its caller.
> >>
> >> When deciders are called in infinite recursion we have
> >> contradictory axioms.
> >>
> >> *HERE IS WHAT ACTUALLY HAPPENS*
> >> (a) H(P,P) simulates P(P) that calls a simulated H(P,P)
> >> (b) that simulates P(P) that calls a simulated H(P,P)
> >> (c) that simulates P(P) that calls a simulated H(P,P)
> >> (d) that simulates P(P) that calls a simulated H(P,P)...
> >> *Until H aborts its simulation*
> >> (e) then H(P,P) returns to main()
> >>
> >> (a) P(P) invokes H(P,P)
> >> (b) H(P,P) simulates P(P) that calls a simulated H(P,P)
> >> (c) that simulates P(P) that calls a simulated H(P,P)
> >> (d) that simulates P(P) that calls a simulated H(P,P)
> >> (e) that simulates P(P) that calls a simulated H(P,P)...
> >> *Until H aborts its simulation*
> >> (f) then H(P,P) returns to P(P) in main()
> >>
> >> (a) Deciders must always return to their caller.
> >> becomes
> >> (a) Deciders that are not called in infinite recursion must always
> >> return to their caller.
> >
> > Simple enough to refute by counter-example, dear: the Flibble
> > Signaling Halt Decider (TM) is a simulating halt decider that does
> > return to its caller, dear.
>
> It is not doing what the semantics of its inputs specifies that it
> must do.
>
> void Px(void (*x)())
> {
> (void) HH(x, x);
> return;
> }
>
> int main()
> {
> Output("Input_Halts = ", HH(Px, Px));
> }
>
> The correct pure simulation of the input to HH by HH as if HH was
> only a simulator and not a simulating halt decider is this:
>
> (a) H(Px,Px) simulates Px(Px) that calls a simulated H(Px,Px)
> (b) that simulates Px(Px) that calls a simulated H(Px,Px)
> (c) that simulates Px(Px) that calls a simulated H(Px,Px)
> (d) that simulates Px(Px) that calls a simulated H(Px,Px)...
>
> _Px()
> [00001102](01) 55 push ebp
> [00001103](02) 8bec mov ebp,esp
> [00001105](03) 8b4508 mov eax,[ebp+08]
> [00001108](01) 50 push eax // Push Px
> [00001109](03) 8b4d08 mov ecx,[ebp+08]
> [0000110c](01) 51 push ecx // Push Px
> [0000110d](05) e890fbffff call 00000ca2 // call HH
> [00001112](03) 83c408 add esp,+08
> [00001115](01) 5d pop ebp
> [00001116](01) c3 ret
> Size in bytes:(0021) [00001116]
>
> It is not possible for HH to correctly return to a simulated Px.
> Every Px that HH(Px,Px) correctly simulates cannot possibly correctly
> reach past machine address [0000110d].

Nope, your assertion is false. The Flibble Signaling Halt Decider (TM)
is a simulating halt decider that can and does return a value to its
caller, Px.

/Flibble