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computers / comp.ai.philosophy / Re: Halting Problem proof refutation is a tautology thus irrefutable [ strawman ]

Re: Halting Problem proof refutation is a tautology thus irrefutable [ strawman ]

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https://www.novabbs.com/computers/article-flat.php?id=9596&group=comp.ai.philosophy#9596

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Subject: Re: Halting Problem proof refutation is a tautology thus irrefutable
[ strawman ]
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Newsgroups: comp.theory,comp.ai.philosophy,sci.logic,sci.math
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From: Rich...@Damon-Family.org (Richard Damon)
In-Reply-To: <ttOdnbX_X4GyEDL_nZ2dnUU7_83NnZ2d@giganews.com>
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Date: Sun, 19 Jun 2022 17:23:16 -0400
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 by: Richard Damon - Sun, 19 Jun 2022 21:23 UTC

On 6/19/22 4:55 PM, olcott wrote:
> On 6/19/2022 3:50 PM, Richard Damon wrote:
>> On 6/19/22 4:34 PM, olcott wrote:
>>> On 6/19/2022 3:19 PM, Richard Damon wrote:
>>>>
>>>> On 6/19/22 3:17 PM, olcott wrote:
>>>>> On 6/19/2022 1:43 PM, Richard Damon wrote:
>>>>>> On 6/19/22 2:30 PM, olcott wrote:
>>>>>>> On 6/19/2022 1:20 PM, Richard Damon wrote:
>>>>>>>> On 6/19/22 2:08 PM, olcott wrote:
>>>>>>>>> On 6/19/2022 12:40 PM, Mr Flibble wrote:
>>>>>>>>>> On Sun, 19 Jun 2022 12:16:05 -0500
>>>>>>>>>> olcott <NoOne@NoWhere.com> wrote:
>>>>>>>>>>
>>>>>>>>>>> On 6/19/2022 12:01 PM, Mr Flibble wrote:
>>>>>>>>>>>> On Sun, 19 Jun 2022 11:23:24 -0500
>>>>>>>>>>>> olcott <NoOne@NoWhere.com> wrote:
>>>>>>>>>>>>> On 6/19/2022 11:01 AM, Mr Flibble wrote:
>>>>>>>>>>>>>> On Sun, 19 Jun 2022 10:39:34 -0500
>>>>>>>>>>>>>> olcott <NoOne@NoWhere.com> wrote:
>>>>>>>>>>>>>>> On 6/19/2022 10:23 AM, Mr Flibble wrote:
>>>>>>>>>>>>>>>> On Sun, 19 Jun 2022 10:13:00 -0500
>>>>>>>>>>>>>>>> olcott <NoOne@NoWhere.com> wrote:
>>>>>>>>>>>>>>>>> computation that halts … the Turing machine will halt
>>>>>>>>>>>>>>>>> whenever
>>>>>>>>>>>>>>>>> it enters a final state. (Linz:1990:234)
>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>> A halt decider must compute the mapping from its inputs
>>>>>>>>>>>>>>>>> to an
>>>>>>>>>>>>>>>>> accept or reject state on the basis of the actual
>>>>>>>>>>>>>>>>> behavior of
>>>>>>>>>>>>>>>>> these actual inputs.
>>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>>> When a simulating halt decider rejects all inputs as
>>>>>>>>>>>>>>>>> non-halting whenever it correctly detects [in a finite
>>>>>>>>>>>>>>>>> number
>>>>>>>>>>>>>>>>> of steps] that its correct and complete simulation of its
>>>>>>>>>>>>>>>>> input would never reach [a] final state of this input
>>>>>>>>>>>>>>>>> then all
>>>>>>>>>>>>>>>>> [these] inputs (including pathological inputs) are decided
>>>>>>>>>>>>>>>>> correctly.
>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>> void Px(u32 x)
>>>>>>>>>>>>>>>> {
>>>>>>>>>>>>>>>>        H(x, x);
>>>>>>>>>>>>>>>>        return;
>>>>>>>>>>>>>>>> }
>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>> int main()
>>>>>>>>>>>>>>>> {
>>>>>>>>>>>>>>>>        Output("Input_Halts = ", H((u32)Px, (u32)Px));
>>>>>>>>>>>>>>>> }
>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>> ...[000013e8][00102357][00000000] 83c408          add
>>>>>>>>>>>>>>>> esp,+08
>>>>>>>>>>>>>>>> ...[000013eb][00102353][00000000] 50              push eax
>>>>>>>>>>>>>>>> ...[000013ec][0010234f][00000427] 6827040000      push
>>>>>>>>>>>>>>>> 00000427
>>>>>>>>>>>>>>>> ---[000013f1][0010234f][00000427] e880f0ffff      call
>>>>>>>>>>>>>>>> 00000476
>>>>>>>>>>>>>>>> Input_Halts = 0
>>>>>>>>>>>>>>>> ...[000013f6][00102357][00000000] 83c408          add
>>>>>>>>>>>>>>>> esp,+08
>>>>>>>>>>>>>>>> ...[000013f9][00102357][00000000] 33c0            xor
>>>>>>>>>>>>>>>> eax,eax
>>>>>>>>>>>>>>>> ...[000013fb][0010235b][00100000] 5d              pop ebp
>>>>>>>>>>>>>>>> ...[000013fc][0010235f][00000004] c3              ret
>>>>>>>>>>>>>>>> Number of Instructions Executed(16120)
>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>> It gets the answer wrong, i.e. input has not been decided
>>>>>>>>>>>>>>>> correctly. QED.
>>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>>> /Flibble
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> _P()
>>>>>>>>>>>>>>> [000010fa](01)  55              push ebp
>>>>>>>>>>>>>>> [000010fb](02)  8bec            mov ebp,esp
>>>>>>>>>>>>>>> [000010fd](03)  8b4508          mov eax,[ebp+08]
>>>>>>>>>>>>>>> [00001100](01)  50              push eax       // push P
>>>>>>>>>>>>>>> [00001101](03)  8b4d08          mov ecx,[ebp+08]
>>>>>>>>>>>>>>> [00001104](01)  51              push ecx       // push P
>>>>>>>>>>>>>>> [00001105](05)  e800feffff      call 00000f0a  // call H
>>>>>>>>>>>>>>> [0000110a](03)  83c408          add esp,+08
>>>>>>>>>>>>>>> [0000110d](02)  85c0            test eax,eax
>>>>>>>>>>>>>>> [0000110f](02)  7402            jz 00001113
>>>>>>>>>>>>>>> [00001111](02)  ebfe            jmp 00001111
>>>>>>>>>>>>>>> [00001113](01)  5d              pop ebp
>>>>>>>>>>>>>>> [00001114](01)  c3              ret
>>>>>>>>>>>>>>> Size in bytes:(0027) [00001114]
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> Begin Simulation   Execution Trace Stored at:211ee2
>>>>>>>>>>>>>>> ...[000010da][00211ece][00211ed2] 55         push ebp
>>>>>>>>>>>>>>> ...[000010db][00211ece][00211ed2] 8bec       mov ebp,esp
>>>>>>>>>>>>>>> ...[000010dd][00211ece][00211ed2] 8b4508     mov
>>>>>>>>>>>>>>> eax,[ebp+08]
>>>>>>>>>>>>>>> ...[000010e0][00211eca][000010da] 50         push
>>>>>>>>>>>>>>> eax      //
>>>>>>>>>>>>>>> push P ...[000010e1][00211eca][000010da] 8b4d08     mov
>>>>>>>>>>>>>>> ecx,[ebp+08] ...[000010e4][00211ec6][000010da] 51 push
>>>>>>>>>>>>>>> ecx      // push P ...[000010e5][00211ec2][000010ea]
>>>>>>>>>>>>>>> e820feffff
>>>>>>>>>>>>>>> call 00000f0a // call H Infinitely Recursive Simulation
>>>>>>>>>>>>>>> Detected
>>>>>>>>>>>>>>> Simulation Stopped
>>>>>>>>>>>>>>>
>>>>>>>>>>>>>>> *All technically competent software engineers* will see that
>>>>>>>>>>>>>>> when H bases its halt status decision on whether or not its
>>>>>>>>>>>>>>> complete and correct x86 emulation of its input would
>>>>>>>>>>>>>>> ever reach
>>>>>>>>>>>>>>> the "ret" instruction of this input that H is correct to
>>>>>>>>>>>>>>> reject
>>>>>>>>>>>>>>> this input.
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> void Px(u32 x)
>>>>>>>>>>>>>> {
>>>>>>>>>>>>>>       H(x, x);
>>>>>>>>>>>>>>       return;
>>>>>>>>>>>>>> }
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> int main()
>>>>>>>>>>>>>> {
>>>>>>>>>>>>>>       Output("Input_Halts = ", H((u32)Px, (u32)Px));
>>>>>>>>>>>>>> }
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> ...[000013e8][00102357][00000000] 83c408          add esp,+08
>>>>>>>>>>>>>> ...[000013eb][00102353][00000000] 50              push eax
>>>>>>>>>>>>>> ...[000013ec][0010234f][00000427] 6827040000      push
>>>>>>>>>>>>>> 00000427
>>>>>>>>>>>>>> ---[000013f1][0010234f][00000427] e880f0ffff      call
>>>>>>>>>>>>>> 00000476
>>>>>>>>>>>>>> Input_Halts = 0
>>>>>>>>>>>>>> ...[000013f6][00102357][00000000] 83c408          add esp,+08
>>>>>>>>>>>>>> ...[000013f9][00102357][00000000] 33c0            xor eax,eax
>>>>>>>>>>>>>> ...[000013fb][0010235b][00100000] 5d              pop ebp
>>>>>>>>>>>>>> ...[000013fc][0010235f][00000004] c3              ret
>>>>>>>>>>>>>> Number of Instructions Executed(16120)
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> It gets the answer wrong, i.e. input has not been decided
>>>>>>>>>>>>>> correctly. QED.
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> /Flibble
>>>>>>>>>>>>>
>>>>>>>>>>>>> *All technically competent software engineers*
>>>>>>>>>>>> void Px(u32 x)
>>>>>>>>>>>> {
>>>>>>>>>>>>      H(x, x);
>>>>>>>>>>>>      return;
>>>>>>>>>>>> }
>>>>>>>>>>>>
>>>>>>>>>>>> int main()
>>>>>>>>>>>> {
>>>>>>>>>>>>      Output("Input_Halts = ", H((u32)Px, (u32)Px));
>>>>>>>>>>>> }
>>>>>>>>>>>>
>>>>>>>>>>>> ...[000013e8][00102357][00000000] 83c408          add esp,+08
>>>>>>>>>>>> ...[000013eb][00102353][00000000] 50              push eax
>>>>>>>>>>>> ...[000013ec][0010234f][00000427] 6827040000      push 00000427
>>>>>>>>>>>> ---[000013f1][0010234f][00000427] e880f0ffff      call 00000476
>>>>>>>>>>>> Input_Halts = 0
>>>>>>>>>>>> ...[000013f6][00102357][00000000] 83c408          add esp,+08
>>>>>>>>>>>> ...[000013f9][00102357][00000000] 33c0            xor eax,eax
>>>>>>>>>>>> ...[000013fb][0010235b][00100000] 5d              pop ebp
>>>>>>>>>>>> ...[000013fc][0010235f][00000004] c3              ret
>>>>>>>>>>>> Number of Instructions Executed(16120)
>>>>>>>>>>>>
>>>>>>>>>>>> It gets the answer wrong, i.e. input has not been decided
>>>>>>>>>>>> correctly.
>>>>>>>>>>>> QED.
>>>>>>>>>>>>
>>>>>>>>>>>> /Flibble
>>>>>>>>>>>
>>>>>>>>>>> Because it is an easily verified fact that the correct and
>>>>>>>>>>> complete
>>>>>>>>>>> x86 emulation of the input to H(P,P) by H would never reach
>>>>>>>>>>> the "ret"
>>>>>>>>>>> instruction of P and this is the criterion measure for H to
>>>>>>>>>>> reject
>>>>>>>>>>> its input how do you figure that H gets the wrong answer?
>>>>>>>>>>>
>>>>>>>>>>> What I am saying is a logical tautology the same as when we
>>>>>>>>>>> know that
>>>>>>>>>>> X is a black cat then we know that X is a cat.
>>>>>>>>>> We are talking about Px, not P. We are talking about your H not
>>>>>>>>>> analysing what its input actually does and instead assuming
>>>>>>>>>> that an
>>>>>>>>>> input that calls H is always pathological.
>>>>>>>>>>
>>>>>>>>>> void Px(u32 x)
>>>>>>>>>> {
>>>>>>>>>>     H(x, x);
>>>>>>>>>>     return;
>>>>>>>>>> }
>>>>>>>>>>
>>>>>>>>>> int main()
>>>>>>>>>> {
>>>>>>>>>>     Output("Input_Halts = ", H((u32)Px, (u32)Px));
>>>>>>>>>> }
>>>>>>>>>>
>>>>>>>>>> ...[000013e8][00102357][00000000] 83c408          add esp,+08
>>>>>>>>>> ...[000013eb][00102353][00000000] 50              push eax
>>>>>>>>>> ...[000013ec][0010234f][00000427] 6827040000      push 00000427
>>>>>>>>>> ---[000013f1][0010234f][00000427] e880f0ffff      call 00000476
>>>>>>>>>> Input_Halts = 0
>>>>>>>>>> ...[000013f6][00102357][00000000] 83c408          add esp,+08
>>>>>>>>>> ...[000013f9][00102357][00000000] 33c0            xor eax,eax
>>>>>>>>>> ...[000013fb][0010235b][00100000] 5d              pop ebp
>>>>>>>>>> ...[000013fc][0010235f][00000004] c3              ret
>>>>>>>>>> Number of Instructions Executed(16120)
>>>>>>>>>>
>>>>>>>>>> It gets the answer wrong, i.e. input has not been decided
>>>>>>>>>> correctly.
>>>>>>>>>> QED.
>>>>>>>>>>
>>>>>>>>>> /Flibble
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> DO YOU AGREE WITH THIS?
>>>>>>>>> H(Px,Px) does correctly determine that the complete and correct
>>>>>>>>> x86 emulation of its input would never reach the "ret"
>>>>>>>>> instruction of Px.
>>>>>>>>>
>>>>>>>>
>>>>>>>> That is only true if H never returns ANY answer (and thus fails
>>>>>>>> to be a decider).
>>>>>>> Competent software engineers will understand that when the
>>>>>>> behavior of Px matches this pattern that correct and complete x86
>>>>>>> emulation of the input to H(Px,Px) by H would never reach the
>>>>>>> "ret" instruction of Px:
>>>>>>>
>>>>>>> H knows its own machine address and on this basis:
>>>>>>> (a) H recognizes that Px is calling H with the same arguments
>>>>>>> that H was called with.
>>>>>>> (b) There are no instructions in Px that could possibly escape
>>>>>>> this infinitely recursive emulation.
>>>>>>> (c) H aborts its emulation of Px before Px its call to H is invoked.
>>>>>>>
>>>>>>>
>>>>>>
>>>>>> Only if H never aborts. If H does abort, then Px(Px), whose
>>>>>> behavior exactly matches the CORRECT emulation of the input to
>>>>>> H(Px,Px) BY DEFINITION shows this.
>>>>>
>>>>> The question is: Would (future tense) the complete and correct x86
>>>>> emulation of the input to H(Px,Px) by H ever reach the "ret"
>>>>> instruction of Px.
>>>>
>>>> What "Future Tense".
>>> A halt decider must always correctly determine whether or not its
>>> input WOULD halt. If halt deciders reported what the behavior of its
>>> input
>>> DOES then like you said it would never report on non halting inputs.
>>>
>>> All non-simulating halt deciders can only report on what their input
>>> WOULD do and not what their input DOES because non-simulating halt
>>> deciders are static rather than dynamic analyzers.
>>>
>>
>> Would only in the sense of condition of testing, not time.
> Halt deciders must always predict what their non-halting inputs would do
> in the future if they were executed.

Why?

There is no actual requirement to execute the machine, only know what
would happen if at some point we did do that execution either in the
past or the future.

>
> They can never report on the non-halting behavior of what their inputs
> did do in the past.

Why not? Does it change? In fact, doesn't your halt decider work on
emulating its input, and if it sees it halt report that. That halting
happened BEFORE H gave its answer.

>
> You have been confused about this for your last 1000 messages.
>

No, you are.

Which happened first, did 3+4 become equal to 7 before or after 2+5
became equal to 7

Mathematical facts are not temporal, so don't change over time, so
placing when they "happened" in time is non-sense.

Specific events, that depend on others may have "Order", but that isn't
the same as past and future to us.

SubjectRepliesAuthor
o Halting Problem proof refutation is a tautology thus irrefutable

By: olcott on Sun, 19 Jun 2022

76olcott
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