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Simulations are like miniskirts, they show a lot and hide the essentials. -- Hubert Kirrman

computers / comp.arch.fpga

Subject	Replies	Last Message
Old versions of quartus By: Chris Adams on Tue, 8 Feb 2022	6	1 Month 9 Days ago By: Namazi Azhari
All my PDF files suddenly become Chrome HTML Document! Why? By: Tianxiang Weng on Fri, 28 May 2021	20	1 Month 24 Days ago By: gnuarm.del...@gmail.
PCB Layout for BGAs By: gnuarm.del...@gmail. on Sat, 7 Jan 2023	49	1 Month 27 Days ago By: David Brown
What happened to the OpenCores website By: Wojciech Zabolotny on Wed, 18 Jan 2023	3	2 Months ago By: gnuarm.del...@gmail.
Excess 3 Adder: Add 2 three digits numbers in excess 3. By: Virulog_X on Wed, 14 Dec 2022	2	3 Months 10 Days ago By: KJ
Program Counter in Verilog. Case not working. By: SpainHack on Fri, 9 Dec 2022	5	3 Months 13 Days ago By: gnuarm.del...@gmail.
Disabled generate gives compile error in Modelsim By: Stef on Fri, 9 Dec 2022	1	3 Months 16 Days ago By: KJ
Trion bitstream compression test By: John Larkin on Sun, 11 Dec 2022	4	3 Months 16 Days ago By: Dimiter_Popoff
Where can I find solutions to my problems? By: JAMMY Anderson on Fri, 9 Dec 2022	0	3 Months 18 Days ago By: JAMMY Anderson
efinix bit stream question By: John Larkin on Sun, 27 Nov 2022	10	3 Months 22 Days ago By: John Larkin
Developing older Xilinx FPGA and CPLD XC3S500E By: Cy Drollinger on Wed, 30 Nov 2022	2	3 Months 25 Days ago By: Gabor
Re: How to change the font size in text editor of modelsim By: Prince Kumar Gupta on Tue, 15 Nov 2022	0	4 Months 12 Days ago By: Prince Kumar Gupta
Forcing Synopsys to use only DFFs By: Chris Johnson on Thu, 20 Oct 2022	1	5 Months 6 Days ago By: gnuarm.del...@gmail.
Renesas has a 1 kLUT FPGA! By: gnuarm.del...@gmail. on Mon, 10 Oct 2022	2	5 Months 17 Days ago By: gnuarm.del...@gmail.
Renesas GreenPAK Sales/FAE Support By: gnuarm.del...@gmail. on Sun, 9 Oct 2022	0	5 Months 18 Days ago By: gnuarm.del...@gmail.
32-bit Z8000 the Z80,000 and Z80320 Microprocessor By: Nathan Brown on Wed, 5 Oct 2022	0	5 Months 21 Days ago By: Nathan Brown
Intel announces new FPGA families By: Claudio Avi Chami on Thu, 29 Sep 2022	2	5 Months 26 Days ago By: Theo
Hardware based IP protection of FPGA designs By: gnuarm.del...@gmail. on Sat, 24 Sep 2022	10	6 Months ago By: gnuarm.del...@gmail.
Re: (PDF) Solutions Manual Calculus, Single and Multivariable, 6th By: Andrew Cao on Tue, 27 Sep 2022	0	6 Months ago By: Andrew Cao
Research Assistantship at the Graduate School, Dept. of Computer By: jg.lee on Mon, 26 Sep 2022	0	6 Months 1 Day ago By: jg.lee
Magellan VHDL monitor for Basys 3 board By: Claudio Avi Chami on Sat, 24 Sep 2022	0	6 Months 3 Days ago By: Claudio Avi Chami
Last CFP: 22nd International Conference on Hybrid Intelligent Systems By: Anu Bajaj on Fri, 9 Sep 2022	0	6 Months 18 Days ago By: Anu Bajaj
Wide frequency range, arbitrary waveform DDS By: Stef on Tue, 16 Aug 2022	22	7 Months 3 Days ago By: gnuarm.del...@gmail.
Efinix FPGA By: gnuarm.del...@gmail. on Tue, 12 Jul 2022	17	7 Months 10 Days ago By: Clifford Heath
2nd CFP: 18th International Conference on Information Assurance and By: Dr.Aswathy SU on Sun, 7 Aug 2022	0	7 Months 20 Days ago By: Dr.Aswathy SU
VHDL project. Connecting components to one component By: Durko Rurko on Mon, 31 Jan 2022	1	8 Months 5 Days ago By: 嚴子清
Getting Rank of Elements in an Array using VHDL By: Md Multan Biswas on Tue, 21 Jun 2022	1	9 Months 6 Days ago By: Kevin
First CFP: The 12th World Congress on Information and Communication By: Anu Bajaj on Fri, 20 May 2022	0	10 Months 7 Days ago By: Anu Bajaj
First CFP: 13th International Conference on Innovations in By: Anu Bajaj on Mon, 16 May 2022	0	10 Months 11 Days ago By: Anu Bajaj
Why Xilinx Ten Gigabit Ethernet PCS/PMA IP Core 32-bit version use By: Qiu Shui on Sat, 3 Jul 2021	1	10 Months 26 Days ago By: Hariprasad Bhat
First CFP: 14th World Congress on Nature and Biologically Inspired By: Anu Bajaj on Wed, 27 Apr 2022	0	11 Months ago By: Anu Bajaj
First CFP: 18th International Conference on Information Assurance and By: Anu Bajaj on Fri, 15 Apr 2022	0	11 Months 12 Days ago By: Anu Bajaj
First CFP: 22nd International Conference on Intelligent Systems By: Anu Bajaj on Wed, 13 Apr 2022	0	11 Months 14 Days ago By: Anu Bajaj
First CFP: 22nd International Conference on Hybrid Intelligent By: Anu Bajaj on Sat, 9 Apr 2022	0	11 Months 18 Days ago By: Anu Bajaj
Development tools for Xilinx Spartan 3 By: Stef on Thu, 3 Mar 2022	4	1 Year ago By: Gerhard Hoffmann
Calculation of throughput of sub-block in digital design (I) By: Hassan Iqbal on Sun, 20 Feb 2022	0	1 Year 1 Month ago By: Hassan Iqbal
Re: Xilinx microblaze vs. picoblaze By: Alisha Pal on Fri, 18 Feb 2022	1	1 Year 1 Month ago By: Hassan Iqbal
Quartus II Synthesis - System Memory Issues for Large Stratix 10 Desig By: Chris Adams on Fri, 29 Oct 2021	6	1 Year 1 Month ago By: Theo
Is it possible to amplify weak lows and weak highs? By: Kevin Simonson on Sun, 2 Jan 2022	2	1 Year 2 Months ago By: gnuarm.del...@gmail.
BeMicro Cyclone III 64-bit drivers By: Maur Vir on Fri, 21 Jan 2022	2	1 Year 2 Months ago By: Maur Vir
How to Implement a Random Access Memory at the Transistor Level By: Kevin Simonson on Mon, 27 Dec 2021	2	1 Year 2 Months ago By: Doug McIntyre
Xilinx forums have disappeared? By: Wojciech Zabolotny on Sun, 26 Sep 2021	10	1 Year 3 Months ago By: Slawomir Siluk
Re: Cheacksum implementation in VHDL By: Vincent Li on Tue, 9 Nov 2021	7	1 Year 3 Months ago By: gnuarm.del...@gmail.
Verilog HDL Finite State Machine - detecting a decimal number By: Tanishk Singh on Sun, 7 Nov 2021	1	1 Year 4 Months ago By: gnuarm.del...@gmail.
Re: Cheacksum implementation in VHDL By: Vincent Li on Tue, 9 Nov 2021	0	1 Year 4 Months ago By: Vincent Li
Is there any software I can use to transform state machines in VHDL By: Tianxiang Weng on Wed, 8 Sep 2021	7	1 Year 4 Months ago By: Svenn Are Bjerkem
UDP -FPGA point to point By: Manav Nair on Mon, 18 Oct 2021	3	1 Year 5 Months ago By: Richard Damon
Re: Orcad Capture error DSM0006 and DBO3203 By: PROYMAV on Wed, 20 Oct 2021	0	1 Year 5 Months ago By: PROYMAV
Notepad++ is an excellent editor for coding VHDL By: Tianxiang Weng on Wed, 26 May 2021	1	1 Year 5 Months ago By: john
GDB from my university... By: Yousaf tehseen on Sun, 15 Aug 2021	2	1 Year 7 Months ago By: Kevin
PLL dynamic phase shift By: promach on Sun, 1 Aug 2021	0	1 Year 7 Months ago By: promach
A state machine design problem By: Tianxiang Weng on Thu, 8 Jul 2021	1	1 Year 8 Months ago By: Tianxiang Weng
Synthesis : Pan's Algorithm By: promach on Thu, 8 Jul 2021	0	1 Year 8 Months ago By: promach
How long does it take to fill up an array prior to sorting? By: Kevin Simonson on Mon, 21 Jun 2021	4	1 Year 9 Months ago By: gnuarm.del...@gmail.
A loop problem which does not do what is expected By: Tianxiang Weng on Fri, 18 Jun 2021	9	1 Year 9 Months ago By: gnuarm.del...@gmail.
How to increase data of std_logic_vector by 1 in VHDL-2002 By: W TX on Mon, 24 May 2021	8	1 Year 9 Months ago By: Tianxiang Weng
Measuring ps of delays in FPGAs By: partha sarathy on Mon, 21 Jun 2021	0	1 Year 9 Months ago By: partha sarathy
Enterpoint dev board manuals By: Philip Pemberton on Fri, 18 Jun 2021	0	1 Year 9 Months ago By: Philip Pemberton
How to eliminate a troublesome warning from ModelSim By: Tianxiang Weng on Thu, 17 Jun 2021	0	1 Year 9 Months ago By: Tianxiang Weng
How to run ModelSim overnight with display off By: Tianxiang Weng on Fri, 11 Jun 2021	9	1 Year 9 Months ago By: Tianxiang Weng
How to start with FPGA as "coprocessor" By: Thomas Koenig on Sat, 8 May 2021	19	1 Year 9 Months ago By: Nelson Ribeiro
How to turn off cursor note pane when cursor stops at wave pane of Mod By: Tianxiang Weng on Fri, 4 Jun 2021	2	1 Year 9 Months ago By: Tianxiang Weng
Intel ModelSim Starter Edition is available free now! By: W TX on Mon, 24 May 2021	18	1 Year 10 Months ago By: Tianxiang Weng
Using MachXO2 as a SRAM device By: Piotr Wyderski on Tue, 25 May 2021	0	1 Year 10 Months ago By: Piotr Wyderski
VHDL2019 Webinars By: HT-Lab on Fri, 30 Apr 2021	7	1 Year 10 Months ago By: HT-Lab
A bewildering Visio-2019 problem! By: W TX on Sun, 11 Apr 2021	1	1 Year 11 Months ago By: W TX
Research Assistantship (Fall, 2021) at Dept. of Computer Engineering, By: jg.lee on Mon, 5 Apr 2021	0	1 Year 11 Months ago By: jg.lee
Re: XILINX PCIe read of slow device By: Luis Benites on Tue, 9 Mar 2021	2	2 Years ago By: Luis Benites
Hi can anyone please tell me how to rectify this error By: Shanmukharao Muddada on Sun, 14 Mar 2021	1	2 Years ago By: Jon Elson
Achronix? By: John Larkin on Fri, 29 Jan 2021	2	2 Years ago By: gnuarm.del...@gmail.
MachXO2 pin mismatch error By: Piotr Wyderski on Thu, 11 Mar 2021	1	2 Years ago By: HT-Lab
Fully Comitted to LVDS as Comparitors By: gnuarm.del...@gmail. on Tue, 23 Feb 2021	0	2 Years 1 Month ago By: gnuarm.del...@gmail.
Gowin - This Just Got Real By: gnuarm.del...@gmail. on Wed, 9 Dec 2020	5	2 Years 2 Months ago By: gnuarm.del...@gmail.
Division Algorithms By: gnuarm.del...@gmail. on Sat, 16 Jan 2021	2	2 Years 2 Months ago By: gnuarm.del...@gmail.
Re: Achronix Semiconductor in Talks for Merger By: Kevin Neilson on Thu, 7 Jan 2021	28	2 Years 2 Months ago By: Kevin Neilson
Fixed Point Arithmetic By: gnuarm.del...@gmail. on Tue, 29 Dec 2020	9	2 Years 2 Months ago By: gnuarm.del...@gmail.
PHB FPGA question By: jlarkin on Sun, 27 Dec 2020	3	2 Years 2 Months ago By: Kevin Neilson
Temperature Sensor Error By: Mezanur Rahman on Wed, 16 Dec 2020	5	2 Years 3 Months ago By: Mike Perkins
CRC is an FPGA PITA By: gnuarm.del...@gmail. on Sat, 12 Dec 2020	18	2 Years 3 Months ago By: Mike Perkins
Why am I getting different results with two files collapsed into one? By: Kevin Simonson on Sun, 6 Dec 2020	5	2 Years 3 Months ago By: Kevin Simonson
Synthesizable open FPGA cores By: partha sarathy on Sat, 28 Nov 2020	1	2 Years 3 Months ago By: Theo
To Reset or not to Reset, That is the Question! By: gnuarm.del...@gmail. on Tue, 24 Nov 2020	4	2 Years 4 Months ago By: Mike Perkins
Using DSP Units By: gnuarm.del...@gmail. on Sun, 22 Nov 2020	7	2 Years 4 Months ago By: Richard Damon
Programming a Traffic Light Controller In verilog using Quartus Prime By: Dave Wood on Thu, 19 Nov 2020	3	2 Years 4 Months ago By: Theo
ADCs in FPGAs By: Rick C on Mon, 31 Aug 2020	23	2 Years 4 Months ago By: gnuarm.del...@gmail.
Is there a way in Verilog to refer to a slice of an array? By: Kevin Simonson on Thu, 5 Nov 2020	9	2 Years 4 Months ago By: Remigiusz Kaletka
Finally! I figgured it out accidentally. By: Rick C on Fri, 6 Nov 2020	2	2 Years 4 Months ago By: Rick C
Is there a way in Verilog to refer to a slice of an array? By: Kevin Simonson on Thu, 5 Nov 2020	0	2 Years 4 Months ago By: Kevin Simonson
HP "owning" the software for Xilinx-FTDI drivers??? By: Rick C on Tue, 27 Oct 2020	6	2 Years 4 Months ago By: Rick C
ready/valid vs 2-way handshaking vs 4-way handshaking By: Ubaid Abdullah on Wed, 28 Oct 2020	4	2 Years 4 Months ago By: Kevin Neilson
Active-HDL Throws Error By: Rick C on Mon, 19 Oct 2020	14	2 Years 5 Months ago By: HT-Lab
Gowin Synthesis Software By: Rick C on Sun, 18 Oct 2020	0	2 Years 5 Months ago By: Rick C
adding FPGA grounds By: jlarkin on Sun, 11 Oct 2020	21	2 Years 5 Months ago By: Rick C
What is wrong with low level code? By: Kevin Simonson on Mon, 5 Oct 2020	14	2 Years 5 Months ago By: Kevin Neilson
XLNX on the Auction Block? By: Rick C on Mon, 12 Oct 2020	0	2 Years 5 Months ago By: Rick C
Real Time Simulation By: Rick C on Sat, 10 Oct 2020	4	2 Years 5 Months ago By: HT-Lab
FPGA sensitivities By: John Larkin on Fri, 25 Sep 2020	4	2 Years 5 Months ago By: John Larkin
Piplineing logic alot? I have a tool for you By: Julian Kemmerer on Thu, 1 Oct 2020	0	2 Years 5 Months ago By: Julian Kemmerer
Multi-FPGA Interconnection: latest techniques By: partha sarathy on Thu, 24 Sep 2020	9	2 Years 5 Months ago By: Theo
How powerful is Verilog at using parameters to specify designs? By: Kevin Simonson on Mon, 21 Sep 2020	21	2 Years 5 Months ago By: Kevin Simonson
Active HDL Entity Retention By: Rick C on Fri, 25 Sep 2020	4	2 Years 5 Months ago By: Rick C
Is there any way to get a different font for code sections? By: Kevin Simonson on Tue, 22 Sep 2020	1	2 Years 6 Months ago By: Rick C
Exponential Regression by XSG By: Mjzoob I. Ibrahim on Mon, 21 Sep 2020	0	2 Years 6 Months ago By: Mjzoob I. Ibrahim
Gowin FPGA Oddities By: Rick C on Tue, 15 Sep 2020	27	2 Years 6 Months ago By: Rick C
exponential regression in XSG By: Mjzoob I. Ibrahim on Sun, 20 Sep 2020	1	2 Years 6 Months ago By: Kevin Neilson
Is it illegal to use an (enum) as a Verilog function input? By: Kevin Simonson on Thu, 17 Sep 2020	1	2 Years 6 Months ago By: gtwrek
Can anyone explain "cannot currently create a parameter of type" By: Kevin Simonson on Thu, 17 Sep 2020	5	2 Years 6 Months ago By: gtwrek
Non-binary NCO Modulus By: Rick C on Tue, 15 Sep 2020	8	2 Years 6 Months ago By: Rick C
Can a Verilog function take a boolean argument? By: Kevin Simonson on Thu, 17 Sep 2020	1	2 Years 6 Months ago By: Kevin Neilson
DE10 Standard Audio Demos not working By: Nandan Dayal on Mon, 14 Sep 2020	5	2 Years 6 Months ago By: Richard Damon
Trenz FPGA Module By: Rick C on Mon, 14 Sep 2020	5	2 Years 6 Months ago By: Rick C
Active HDL and the Case of the Haunted Cursor By: Rick C on Sat, 12 Sep 2020	1	2 Years 6 Months ago By: HT-Lab
Bit Swizzling By: Rick C. Hodgin on Sat, 5 Sep 2020	7	2 Years 6 Months ago By: R.Wieser
Go To VHDL Resource By: Rick C on Mon, 7 Sep 2020	2	2 Years 6 Months ago By: Mike Perkins
Re: Bit swizzling By: Rick C. Hodgin on Sun, 6 Sep 2020	0	2 Years 6 Months ago By: Rick C. Hodgin
Are Gowin Serious Contenders? By: Rick C on Sat, 29 Aug 2020	7	2 Years 6 Months ago By: Rick C
What is a Processor and Software in Context of Reliability Analysis? By: Rick C on Thu, 3 Sep 2020	2	2 Years 6 Months ago By: Rick C
iCE40 Ultra Family Data Sheet By: Rick C on Tue, 25 Aug 2020	7	2 Years 6 Months ago By: Rick C
Potential New Design By: Rick C on Sat, 22 Aug 2020	11	2 Years 7 Months ago By: Rick C
Re: Is FPGA code called firmware? By: Narada Fernando on Thu, 13 Aug 2020	0	2 Years 7 Months ago By: Narada Fernando
Elastic buffer implementation By: promach on Wed, 12 Aug 2020	0	2 Years 7 Months ago By: promach
Some preliminary help for an FPGA selection By: Dimiter_Popoff on Fri, 7 Aug 2020	4	2 Years 7 Months ago By: Gabor
VLSI SUBSCRIBE By: Chip training design on Sun, 9 Aug 2020	0	2 Years 7 Months ago By: Chip training design
Entity-bound SDC file in Quartus Lite Edition? By: wzab01 on Mon, 3 Aug 2020	1	2 Years 7 Months ago By: Theo
Re: Xilinx Xact Step Software By: edsil694 on Mon, 20 Jul 2020	0	2 Years 8 Months ago By: edsil694
Re: Open source Verilog BCH encoder/decoder By: gab.jimenez93 on Mon, 13 Jul 2020	0	2 Years 8 Months ago By: gab.jimenez93
Re: Need help finding Synario Futurenet 6.10 By: tgroden3 on Sat, 11 Jul 2020	0	2 Years 8 Months ago By: tgroden3
ICCD 2020: Call for Special Sessions and Tutorial Proposals By: Pillement on Mon, 6 Jul 2020	0	2 Years 8 Months ago By: Pillement
CPU Softcore Compendium By: Rick C on Thu, 16 Apr 2020	4	2 Years 8 Months ago By: jim.brakefield
Driving crystal with cheap FPGA ( MAchXO2) directly ? By: Brane 2 on Tue, 16 Jun 2020	29	2 Years 8 Months ago By: Richard Damon
Lattice new 28nm series - any clues about availability ? By: Brane 2 on Mon, 29 Jun 2020	8	2 Years 8 Months ago By: Rick C
<whine mode on> Why is my source buried in the bowels of the project? By: Rick C on Sat, 20 Jun 2020	5	2 Years 9 Months ago By: Rick C
Lattice Diamond/LSE Synthesis - implementing ring oscilator in By: Brane 2 on Sun, 14 Jun 2020	6	2 Years 9 Months ago By: Brane 2
Reverse Engineering the Comtech AHA363 PCIe Gzip Accelerator Board By: Zach Metzinger on Tue, 23 Jun 2020	0	2 Years 9 Months ago By: Zach Metzinger
enum and Vivado By: David Bridgham on Fri, 5 Jun 2020	7	2 Years 9 Months ago By: David Bridgham
Looking for MMI M2018 LCA data sheet By: Zach Metzinger on Fri, 15 May 2020	15	2 Years 10 Months ago By: Gerhard Hoffmann
fixed point modeling tools By: zack sheffield on Wed, 6 May 2020	4	2 Years 10 Months ago By: zack_sheffield
Passing digitized data to design By: Mohammed Billoo on Wed, 6 May 2020	5	2 Years 10 Months ago By: Rick C
Re: Custom CPU Designs By: Theo on Fri, 17 Apr 2020	3	2 Years 11 Months ago By: Rick C
CFP IEEE International Conference on Computer Design (ICCD) 2020 By: Pillement on Fri, 17 Apr 2020	0	2 Years 11 Months ago By: Pillement
No more gate-level simulation. for Cyclone V !!! By: Luis Cupido on Thu, 2 Apr 2020	8	2 Years 11 Months ago By: KJ
Terminated By: Jeff Hickling on Mon, 6 Apr 2020	2	2 Years 11 Months ago By: Zach Metzinger
Use example of Intel University program in Intel Quartus - problem By: Bliad Bors on Tue, 24 Mar 2020	4	3 Years ago By: Bliad Bors
PipelineC - C-like almost hardware description language - AWS F1 Examp By: Julian Kemmerer on Sun, 22 Mar 2020	2	3 Years ago By: Julian Kemmerer
Using EDA tools at home By: henknep4 on Thu, 19 Mar 2020	0	3 Years ago By: henknep4
Re: Is FPGA code called firmware? By: ben.twijnstra on Tue, 18 Feb 2020	1	3 Years 1 Month ago By: thomas.entner99
Code block in icestudio By: Josef Moellers on Thu, 13 Feb 2020	17	3 Years 1 Month ago By: Anssi Saari
How to generate bits info for a record structure? By: Weng Tianxiang on Thu, 13 Feb 2020	9	3 Years 1 Month ago By: Weng Tianxiang
how to suppress assertion warnings in gtkwave? By: the clever Bit on Fri, 7 Feb 2020	3	3 Years 1 Month ago By: the clever Bit
Re: Is FPGA code called firmware? By: ritchiew on Mon, 27 Jan 2020	19	3 Years 1 Month ago By: Rick C
Add Hunter By: Add Hunter on Wed, 22 Jan 2020	0	3 Years 2 Months ago By: Add Hunter
Apple eBook on Educational CPU design using FPGA By: Othman Ahmad on Tue, 14 Jan 2020	0	3 Years 2 Months ago By: Othman Ahmad
Displays - Apple Mac vs. IBM PC By: Rick C on Wed, 8 Jan 2020	10	3 Years 2 Months ago By: pault.eg
Optimizations, How Much and When? By: Rick C on Sat, 4 Jan 2020	11	3 Years 2 Months ago By: Rick C
Can't get image from PCam 5C running on Zybo Z7-20 with petalinux By: Swapnil Patil on Sat, 14 Dec 2019	0	3 Years 3 Months ago By: Swapnil Patil
Efinix and their new Trion FPGAs - By: Brane2 on Fri, 29 Nov 2019	10	3 Years 3 Months ago By: Rick C
Enabler for New FPGA Companies By: Rick C on Thu, 5 Dec 2019	2	3 Years 3 Months ago By: Adrian Byszuk
Anybody used Amazon AWS for HW sims? By: Kevin Neilson on Thu, 5 Dec 2019	4	3 Years 3 Months ago By: Kevin Neilson
New coding method for a state machine in groups in HDL By: Weng Tianxiang on Mon, 25 Nov 2019	33	3 Years 3 Months ago By: KJ
Issue regarding boot qspi flash in zynq By: richa2854 on Tue, 3 Dec 2019	0	3 Years 3 Months ago By: richa2854
Lattice's ECP5 - half of the program went MIA - WTF ? By: Brane2 on Fri, 29 Nov 2019	6	3 Years 3 Months ago By: Rick C
SOS ! Raspberry PI - HDMI - TMDS Hamsterwork HDMI INPUT = not work By: abirov on Fri, 29 Nov 2019	3	3 Years 3 Months ago By: abirov
tell me what you think! By: consten2013 on Fri, 29 Nov 2019	1	3 Years 3 Months ago By: consten2013
Efinix and their Trion FPGAs By: Brane2 on Fri, 29 Nov 2019	2	3 Years 3 Months ago By: Rick C
AGM vs. Gowin By: Rick C on Sun, 17 Nov 2019	3	3 Years 4 Months ago By: Rick C
Lattice MachXO2/XO3/XO3D vs ECP5 By: Brane2 on Thu, 7 Nov 2019	3	3 Years 4 Months ago By: Rick C
AGM AG6K SoC By: Rick C on Fri, 15 Nov 2019	2	3 Years 4 Months ago By: Rick C
Gowin Semiconductor, Real or Fake? By: Rick C on Wed, 13 Nov 2019	6	3 Years 4 Months ago By: Brane2
Lattice XO3D New By: Rick C on Fri, 12 Jul 2019	7	3 Years 4 Months ago By: Michael Kellett
FPGA config sizes By: John Larkin on Fri, 8 Nov 2019	14	3 Years 4 Months ago By: David Brown
Re: Tiny CPUs for Slow Logic By: oldben on Wed, 9 Oct 2019	9	3 Years 5 Months ago By: Rick C
Student seeking for Internship in Digital Design By: Joshua Roy on Sun, 29 Sep 2019	0	3 Years 5 Months ago By: Joshua Roy
Here is new definition for keyword "if_2", version 2. By: Weng Tianxiang on Fri, 27 Sep 2019	12	3 Years 5 Months ago By: Weng Tianxiang
How to write a correct code to do 2 writes to an array on same cycle? By: Weng Tianxiang on Tue, 24 Sep 2019	12	3 Years 6 Months ago By: KJ
New keyword "if_2" for HDL is suggested for dealing with 2-write port By: Weng Tianxiang on Wed, 25 Sep 2019	5	3 Years 6 Months ago By: KJ
[Fully Funded Scholarship] Research Assistantship (Spring, 2020) at By: jg.lee on Mon, 23 Sep 2019	0	3 Years 6 Months ago By: jg.lee
PipelineC (again), dct example, looking for help/interest By: Julian Kemmerer on Sat, 7 Sep 2019	0	3 Years 6 Months ago By: Julian Kemmerer
PipelineC (again), dct example, looking for help/interest By: Julian Kemmerer on Sat, 7 Sep 2019	0	3 Years 6 Months ago By: Julian Kemmerer
Re: Philips LA PM3585 disassembler software wanted By: smed on Wed, 28 Aug 2019	1	3 Years 6 Months ago By: frankcovending
VHDL TIME support in Vivado By: Rob Gaddi on Fri, 9 Aug 2019	12	3 Years 7 Months ago By: Rick C
Bayer Pattern to RGB VHDL CODE By: abirov on Sun, 11 Aug 2019	1	3 Years 7 Months ago By: abirov
Why differences between Merly-type and Moore-type clock-gated state By: Weng Tianxiang on Fri, 9 Aug 2019	3	3 Years 7 Months ago By: KJ
New uses of FPGAs By: camil.matiska on Mon, 8 Jul 2019	10	3 Years 7 Months ago By: Doug McIntyre
Re: Field update By: Per on Mon, 15 Jul 2019	0	3 Years 8 Months ago By: Per
Us congress hearing of maan alsaan Money laundry ق By: lolo sami on Mon, 8 Jul 2019	0	3 Years 8 Months ago By: lolo sami
Re: Field update By: camil.matiska on Mon, 8 Jul 2019	1	3 Years 8 Months ago By: Jon Elson
Unique uses for the DSP48 By: Kevin Neilson on Fri, 28 Jun 2019	8	3 Years 8 Months ago By: Kevin Neilson
How do big compagnies use Verilog/VHDL for processor designs? By: Benjamin Couillard on Tue, 2 Jul 2019	2	3 Years 8 Months ago By: Tim
HOW TO READ A 64 BIT REGISTER IN 2 CLOCK CYCLES IN VERILOG By: Anonymous on Fri, 28 Jun 2019	1	3 Years 8 Months ago By: gtwrek
bare-metal ZYNQ By: John Larkin on Wed, 12 Jun 2019	25	3 Years 9 Months ago By: Tom Gardner
Microchip UNI/O controller core for FPGA By: wzab01 on Thu, 13 Jun 2019	0	3 Years 9 Months ago By: wzab01
Nallatech BenBlue-II software By: terafemto on Tue, 28 May 2019	0	3 Years 9 Months ago By: terafemto

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Simulations are like miniskirts, they show a lot and hide the essentials. -- Hubert Kirrman

computers / comp.arch.fpga

There are currently 419 users online Total messages: 3,332,604

There are currently 419 users online
Total messages: 3,332,604