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computers / comp.arch.fpga

1
SubjectRepliesLast Message
o First CFP: The 12th World Congress on Information and Communication

By: Anu Bajaj on Fri, 20 May 2022

0

4 Days 7 Hours ago

By: Anu Bajaj

o First CFP: 13th International Conference on Innovations in

By: Anu Bajaj on Mon, 16 May 2022

0

8 Days 14 Hours ago

By: Anu Bajaj

o Why Xilinx Ten Gigabit Ethernet PCS/PMA IP Core 32-bit version use

By: Qiu Shui on Sat, 3 Jul 2021

1

23 Days 18 Hours ago

By: Hariprasad Bhat

o First CFP: 14th World Congress on Nature and Biologically Inspired

By: Anu Bajaj on Wed, 27 Apr 2022

0

27 Days 16 Hours ago

By: Anu Bajaj

o First CFP: 18th International Conference on Information Assurance and

By: Anu Bajaj on Fri, 15 Apr 2022

0

1 Month 9 Days ago

By: Anu Bajaj

o First CFP: 22nd International Conference on Intelligent Systems

By: Anu Bajaj on Wed, 13 Apr 2022

0

1 Month 11 Days ago

By: Anu Bajaj

o First CFP: 22nd International Conference on Hybrid Intelligent

By: Anu Bajaj on Sat, 9 Apr 2022

0

1 Month 15 Days ago

By: Anu Bajaj

o Development tools for Xilinx Spartan 3

By: Stef on Thu, 3 Mar 2022

4

2 Months 20 Days ago

By: Gerhard Hoffmann

o Calculation of throughput of sub-block in digital design (I)

By: Hassan Iqbal on Sun, 20 Feb 2022

0

3 Months 4 Days ago

By: Hassan Iqbal

o Re: Xilinx microblaze vs. picoblaze

By: Alisha Pal on Fri, 18 Feb 2022

1

3 Months 4 Days ago

By: Hassan Iqbal

o Old versions of quartus

By: Chris Adams on Tue, 8 Feb 2022

5

3 Months 15 Days ago

By: dalai lamah

o All my PDF files suddenly become Chrome HTML Document! Why?

By: Tianxiang Weng on Fri, 28 May 2021

13

3 Months 18 Days ago

By: lars kirk

o VHDL project. Connecting components to one component

By: Durko Rurko on Mon, 31 Jan 2022

0

3 Months 23 Days ago

By: Durko Rurko

o Quartus II Synthesis - System Memory Issues for Large Stratix 10 Desig

By: Chris Adams on Fri, 29 Oct 2021

6

3 Months 26 Days ago

By: Theo

o Is it possible to amplify weak lows and weak highs?

By: Kevin Simonson on Sun, 2 Jan 2022

2

3 Months 28 Days ago

By: gnuarm.del...@gmail.

o BeMicro Cyclone III 64-bit drivers

By: Maur Vir on Fri, 21 Jan 2022

2

4 Months 2 Days ago

By: Maur Vir

o How to Implement a Random Access Memory at the Transistor Level

By: Kevin Simonson on Mon, 27 Dec 2021

2

4 Months 26 Days ago

By: Doug McIntyre

o Xilinx forums have disappeared?

By: Wojciech Zabolotny on Sun, 26 Sep 2021

10

5 Months 8 Days ago

By: Slawomir Siluk

o Re: Cheacksum implementation in VHDL

By: Vincent Li on Tue, 9 Nov 2021

7

5 Months 9 Days ago

By: gnuarm.del...@gmail.

o Verilog HDL Finite State Machine - detecting a decimal number

By: Tanishk Singh on Sun, 7 Nov 2021

1

6 Months 4 Days ago

By: gnuarm.del...@gmail.

o Re: Cheacksum implementation in VHDL

By: Vincent Li on Tue, 9 Nov 2021

0

6 Months 15 Days ago

By: Vincent Li

o Is there any software I can use to transform state machines in VHDL

By: Tianxiang Weng on Wed, 8 Sep 2021

7

6 Months 19 Days ago

By: Svenn Are Bjerkem

o UDP -FPGA point to point

By: Manav Nair on Mon, 18 Oct 2021

3

7 Months 4 Days ago

By: Richard Damon

o Re: Orcad Capture error DSM0006 and DBO3203

By: PROYMAV on Wed, 20 Oct 2021

0

7 Months 4 Days ago

By: PROYMAV

o Notepad++ is an excellent editor for coding VHDL

By: Tianxiang Weng on Wed, 26 May 2021

1

7 Months 24 Days ago

By: john

o GDB from my university...

By: Yousaf tehseen on Sun, 15 Aug 2021

2

8 Months 27 Days ago

By: Kevin

o PLL dynamic phase shift

By: promach on Sun, 1 Aug 2021

0

9 Months 23 Days ago

By: promach

o A state machine design problem

By: Tianxiang Weng on Thu, 8 Jul 2021

1

10 Months 14 Days ago

By: Tianxiang Weng

o Synthesis : Pan's Algorithm

By: promach on Thu, 8 Jul 2021

0

10 Months 16 Days ago

By: promach

o How long does it take to fill up an array prior to sorting?

By: Kevin Simonson on Mon, 21 Jun 2021

4

10 Months 27 Days ago

By: gnuarm.del...@gmail.

o A loop problem which does not do what is expected

By: Tianxiang Weng on Fri, 18 Jun 2021

9

10 Months 28 Days ago

By: gnuarm.del...@gmail.

o How to increase data of std_logic_vector by 1 in VHDL-2002

By: W TX on Mon, 24 May 2021

8

11 Months ago

By: Tianxiang Weng

o Measuring ps of delays in FPGAs

By: partha sarathy on Mon, 21 Jun 2021

0

11 Months 3 Days ago

By: partha sarathy

o Enterpoint dev board manuals

By: Philip Pemberton on Fri, 18 Jun 2021

0

11 Months 6 Days ago

By: Philip Pemberton

o How to eliminate a troublesome warning from ModelSim

By: Tianxiang Weng on Thu, 17 Jun 2021

0

11 Months 7 Days ago

By: Tianxiang Weng

o How to run ModelSim overnight with display off

By: Tianxiang Weng on Fri, 11 Jun 2021

9

11 Months 10 Days ago

By: Tianxiang Weng

o How to start with FPGA as "coprocessor"

By: Thomas Koenig on Sat, 8 May 2021

19

11 Months 16 Days ago

By: Nelson Ribeiro

o How to turn off cursor note pane when cursor stops at wave pane of Mod

By: Tianxiang Weng on Fri, 4 Jun 2021

2

11 Months 20 Days ago

By: Tianxiang Weng

o Intel ModelSim Starter Edition is available free now!

By: W TX on Mon, 24 May 2021

18

11 Months 27 Days ago

By: Tianxiang Weng

o Using MachXO2 as a SRAM device

By: Piotr Wyderski on Tue, 25 May 2021

0

11 Months 29 Days ago

By: Piotr Wyderski

o VHDL2019 Webinars

By: HT-Lab on Fri, 30 Apr 2021

7

1 Year ago

By: HT-Lab

o A bewildering Visio-2019 problem!

By: W TX on Sun, 11 Apr 2021

1

1 Year 1 Month ago

By: W TX

o Research Assistantship (Fall, 2021) at Dept. of Computer Engineering,

By: jg.lee on Mon, 5 Apr 2021

0

1 Year 1 Month ago

By: jg.lee

o Re: XILINX PCIe read of slow device

By: Luis Benites on Tue, 9 Mar 2021

2

1 Year 2 Months ago

By: Luis Benites

o Hi can anyone please tell me how to rectify this error

By: Shanmukharao Muddada on Sun, 14 Mar 2021

1

1 Year 2 Months ago

By: Jon Elson

o Achronix?

By: John Larkin on Fri, 29 Jan 2021

2

1 Year 2 Months ago

By: gnuarm.del...@gmail.

o MachXO2 pin mismatch error

By: Piotr Wyderski on Thu, 11 Mar 2021

1

1 Year 2 Months ago

By: HT-Lab

o Fully Comitted to LVDS as Comparitors

By: gnuarm.del...@gmail. on Tue, 23 Feb 2021

0

1 Year 3 Months ago

By: gnuarm.del...@gmail.

o Gowin - This Just Got Real

By: gnuarm.del...@gmail. on Wed, 9 Dec 2020

5

1 Year 4 Months ago

By: gnuarm.del...@gmail.

o Division Algorithms

By: gnuarm.del...@gmail. on Sat, 16 Jan 2021

2

1 Year 4 Months ago

By: gnuarm.del...@gmail.

o Re: Achronix Semiconductor in Talks for Merger

By: Kevin Neilson on Thu, 7 Jan 2021

28

1 Year 4 Months ago

By: Kevin Neilson

o Fixed Point Arithmetic

By: gnuarm.del...@gmail. on Tue, 29 Dec 2020

9

1 Year 4 Months ago

By: gnuarm.del...@gmail.

o PHB FPGA question

By: jlarkin on Sun, 27 Dec 2020

3

1 Year 4 Months ago

By: Kevin Neilson

o Temperature Sensor Error

By: Mezanur Rahman on Wed, 16 Dec 2020

5

1 Year 5 Months ago

By: Mike Perkins

o CRC is an FPGA PITA

By: gnuarm.del...@gmail. on Sat, 12 Dec 2020

18

1 Year 5 Months ago

By: Mike Perkins

o Why am I getting different results with two files collapsed into one?

By: Kevin Simonson on Sun, 6 Dec 2020

5

1 Year 5 Months ago

By: Kevin Simonson

o Synthesizable open FPGA cores

By: partha sarathy on Sat, 28 Nov 2020

1

1 Year 5 Months ago

By: Theo

o To Reset or not to Reset, That is the Question!

By: gnuarm.del...@gmail. on Tue, 24 Nov 2020

4

1 Year 5 Months ago

By: Mike Perkins

o Using DSP Units

By: gnuarm.del...@gmail. on Sun, 22 Nov 2020

7

1 Year 6 Months ago

By: Richard Damon

o Programming a Traffic Light Controller In verilog using Quartus Prime

By: Dave Wood on Thu, 19 Nov 2020

3

1 Year 6 Months ago

By: Theo

o ADCs in FPGAs

By: Rick C on Mon, 31 Aug 2020

23

1 Year 6 Months ago

By: gnuarm.del...@gmail.

o Is there a way in Verilog to refer to a slice of an array?

By: Kevin Simonson on Thu, 5 Nov 2020

9

1 Year 6 Months ago

By: Remigiusz Kaletka

o Finally! I figgured it out accidentally.

By: Rick C on Fri, 6 Nov 2020

2

1 Year 6 Months ago

By: Rick C

o Is there a way in Verilog to refer to a slice of an array?

By: Kevin Simonson on Thu, 5 Nov 2020

0

1 Year 6 Months ago

By: Kevin Simonson

o HP "owning" the software for Xilinx-FTDI drivers???

By: Rick C on Tue, 27 Oct 2020

6

1 Year 6 Months ago

By: Rick C

o ready/valid vs 2-way handshaking vs 4-way handshaking

By: Ubaid Abdullah on Wed, 28 Oct 2020

4

1 Year 6 Months ago

By: Kevin Neilson

o Active-HDL Throws Error

By: Rick C on Mon, 19 Oct 2020

14

1 Year 7 Months ago

By: HT-Lab

o Gowin Synthesis Software

By: Rick C on Sun, 18 Oct 2020

0

1 Year 7 Months ago

By: Rick C

o adding FPGA grounds

By: jlarkin on Sun, 11 Oct 2020

21

1 Year 7 Months ago

By: Rick C

o What is wrong with low level code?

By: Kevin Simonson on Mon, 5 Oct 2020

14

1 Year 7 Months ago

By: Kevin Neilson

o XLNX on the Auction Block?

By: Rick C on Mon, 12 Oct 2020

0

1 Year 7 Months ago

By: Rick C

o Real Time Simulation

By: Rick C on Sat, 10 Oct 2020

4

1 Year 7 Months ago

By: HT-Lab

o FPGA sensitivities

By: John Larkin on Fri, 25 Sep 2020

4

1 Year 7 Months ago

By: John Larkin

o Piplineing logic alot? I have a tool for you

By: Julian Kemmerer on Thu, 1 Oct 2020

0

1 Year 7 Months ago

By: Julian Kemmerer

o Multi-FPGA Interconnection: latest techniques

By: partha sarathy on Thu, 24 Sep 2020

9

1 Year 7 Months ago

By: Theo

o How powerful is Verilog at using parameters to specify designs?

By: Kevin Simonson on Mon, 21 Sep 2020

21

1 Year 7 Months ago

By: Kevin Simonson

o Active HDL Entity Retention

By: Rick C on Fri, 25 Sep 2020

4

1 Year 7 Months ago

By: Rick C

o Is there any way to get a different font for code sections?

By: Kevin Simonson on Tue, 22 Sep 2020

1

1 Year 8 Months ago

By: Rick C

o Exponential Regression by XSG

By: Mjzoob I. Ibrahim on Mon, 21 Sep 2020

0

1 Year 8 Months ago

By: Mjzoob I. Ibrahim

o Gowin FPGA Oddities

By: Rick C on Tue, 15 Sep 2020

27

1 Year 8 Months ago

By: Rick C

o exponential regression in XSG

By: Mjzoob I. Ibrahim on Sun, 20 Sep 2020

1

1 Year 8 Months ago

By: Kevin Neilson

o Is it illegal to use an (enum) as a Verilog function input?

By: Kevin Simonson on Thu, 17 Sep 2020

1

1 Year 8 Months ago

By: gtwrek

o Can anyone explain "cannot currently create a parameter of type"

By: Kevin Simonson on Thu, 17 Sep 2020

5

1 Year 8 Months ago

By: gtwrek

o Non-binary NCO Modulus

By: Rick C on Tue, 15 Sep 2020

8

1 Year 8 Months ago

By: Rick C

o Can a Verilog function take a boolean argument?

By: Kevin Simonson on Thu, 17 Sep 2020

1

1 Year 8 Months ago

By: Kevin Neilson

o DE10 Standard Audio Demos not working

By: Nandan Dayal on Mon, 14 Sep 2020

5

1 Year 8 Months ago

By: Richard Damon

o Trenz FPGA Module

By: Rick C on Mon, 14 Sep 2020

5

1 Year 8 Months ago

By: Rick C

o Active HDL and the Case of the Haunted Cursor

By: Rick C on Sat, 12 Sep 2020

1

1 Year 8 Months ago

By: HT-Lab

o Bit Swizzling

By: Rick C. Hodgin on Sat, 5 Sep 2020

7

1 Year 8 Months ago

By: R.Wieser

o Go To VHDL Resource

By: Rick C on Mon, 7 Sep 2020

2

1 Year 8 Months ago

By: Mike Perkins

o Re: Bit swizzling

By: Rick C. Hodgin on Sun, 6 Sep 2020

0

1 Year 8 Months ago

By: Rick C. Hodgin

o Are Gowin Serious Contenders?

By: Rick C on Sat, 29 Aug 2020

7

1 Year 8 Months ago

By: Rick C

o What is a Processor and Software in Context of Reliability Analysis?

By: Rick C on Thu, 3 Sep 2020

2

1 Year 8 Months ago

By: Rick C

o iCE40 Ultra Family Data Sheet

By: Rick C on Tue, 25 Aug 2020

7

1 Year 8 Months ago

By: Rick C

o Potential New Design

By: Rick C on Sat, 22 Aug 2020

11

1 Year 9 Months ago

By: Rick C

o Re: Is FPGA code called firmware?

By: Narada Fernando on Thu, 13 Aug 2020

0

1 Year 9 Months ago

By: Narada Fernando

o Elastic buffer implementation

By: promach on Wed, 12 Aug 2020

0

1 Year 9 Months ago

By: promach

o Some preliminary help for an FPGA selection

By: Dimiter_Popoff on Fri, 7 Aug 2020

4

1 Year 9 Months ago

By: Gabor

o VLSI SUBSCRIBE

By: Chip training design on Sun, 9 Aug 2020

0

1 Year 9 Months ago

By: Chip training design

o Entity-bound SDC file in Quartus Lite Edition?

By: wzab01 on Mon, 3 Aug 2020

1

1 Year 9 Months ago

By: Theo

o Re: Xilinx Xact Step Software

By: edsil694 on Mon, 20 Jul 2020

0

1 Year 10 Months ago

By: edsil694

o Re: Open source Verilog BCH encoder/decoder

By: gab.jimenez93 on Mon, 13 Jul 2020

0

1 Year 10 Months ago

By: gab.jimenez93

o Re: Need help finding Synario Futurenet 6.10

By: tgroden3 on Sat, 11 Jul 2020

0

1 Year 10 Months ago

By: tgroden3

o ICCD 2020: Call for Special Sessions and Tutorial Proposals

By: Pillement on Mon, 6 Jul 2020

0

1 Year 10 Months ago

By: Pillement

o CPU Softcore Compendium

By: Rick C on Thu, 16 Apr 2020

4

1 Year 10 Months ago

By: jim.brakefield

o Driving crystal with cheap FPGA ( MAchXO2) directly ?

By: Brane 2 on Tue, 16 Jun 2020

29

1 Year 10 Months ago

By: Richard Damon

o Lattice new 28nm series - any clues about availability ?

By: Brane 2 on Mon, 29 Jun 2020

8

1 Year 10 Months ago

By: Rick C

o <whine mode on> Why is my source buried in the bowels of the project?

By: Rick C on Sat, 20 Jun 2020

5

1 Year 10 Months ago

By: Rick C

o Lattice Diamond/LSE Synthesis - implementing ring oscilator in

By: Brane 2 on Sun, 14 Jun 2020

6

1 Year 11 Months ago

By: Brane 2

o Reverse Engineering the Comtech AHA363 PCIe Gzip Accelerator Board

By: Zach Metzinger on Tue, 23 Jun 2020

0

1 Year 11 Months ago

By: Zach Metzinger

o enum and Vivado

By: David Bridgham on Fri, 5 Jun 2020

7

1 Year 11 Months ago

By: David Bridgham

o Looking for MMI M2018 LCA data sheet

By: Zach Metzinger on Fri, 15 May 2020

15

2 Years ago

By: Gerhard Hoffmann

o fixed point modeling tools

By: zack sheffield on Wed, 6 May 2020

4

2 Years ago

By: zack_sheffield

o Passing digitized data to design

By: Mohammed Billoo on Wed, 6 May 2020

5

2 Years ago

By: Rick C

o Re: Custom CPU Designs

By: Theo on Fri, 17 Apr 2020

3

2 Years 1 Month ago

By: Rick C

o CFP IEEE International Conference on Computer Design (ICCD) 2020

By: Pillement on Fri, 17 Apr 2020

0

2 Years 1 Month ago

By: Pillement

o No more gate-level simulation. for Cyclone V !!!

By: Luis Cupido on Thu, 2 Apr 2020

8

2 Years 1 Month ago

By: KJ

o Terminated

By: Jeff Hickling on Mon, 6 Apr 2020

2

2 Years 1 Month ago

By: Zach Metzinger

o Use example of Intel University program in Intel Quartus - problem

By: Bliad Bors on Tue, 24 Mar 2020

4

2 Years 1 Month ago

By: Bliad Bors

o PipelineC - C-like almost hardware description language - AWS F1 Examp

By: Julian Kemmerer on Sun, 22 Mar 2020

2

2 Years 2 Months ago

By: Julian Kemmerer

o Using EDA tools at home

By: henknep4 on Thu, 19 Mar 2020

0

2 Years 2 Months ago

By: henknep4

o Re: Is FPGA code called firmware?

By: ben.twijnstra on Tue, 18 Feb 2020

1

2 Years 3 Months ago

By: thomas.entner99

o Code block in icestudio

By: Josef Moellers on Thu, 13 Feb 2020

17

2 Years 3 Months ago

By: Anssi Saari

o How to generate bits info for a record structure?

By: Weng Tianxiang on Thu, 13 Feb 2020

9

2 Years 3 Months ago

By: Weng Tianxiang

o how to suppress assertion warnings in gtkwave?

By: the clever Bit on Fri, 7 Feb 2020

3

2 Years 3 Months ago

By: the clever Bit

o Re: Is FPGA code called firmware?

By: ritchiew on Mon, 27 Jan 2020

19

2 Years 3 Months ago

By: Rick C

o Add Hunter

By: Add Hunter on Wed, 22 Jan 2020

0

2 Years 4 Months ago

By: Add Hunter

o Apple eBook on Educational CPU design using FPGA

By: Othman Ahmad on Tue, 14 Jan 2020

0

2 Years 4 Months ago

By: Othman Ahmad

o Displays - Apple Mac vs. IBM PC

By: Rick C on Wed, 8 Jan 2020

10

2 Years 4 Months ago

By: pault.eg

o Optimizations, How Much and When?

By: Rick C on Sat, 4 Jan 2020

11

2 Years 4 Months ago

By: Rick C

o Can't get image from PCam 5C running on Zybo Z7-20 with petalinux

By: Swapnil Patil on Sat, 14 Dec 2019

0

2 Years 5 Months ago

By: Swapnil Patil

o Efinix and their new Trion FPGAs -

By: Brane2 on Fri, 29 Nov 2019

10

2 Years 5 Months ago

By: Rick C

o Enabler for New FPGA Companies

By: Rick C on Thu, 5 Dec 2019

2

2 Years 5 Months ago

By: Adrian Byszuk

o Anybody used Amazon AWS for HW sims?

By: Kevin Neilson on Thu, 5 Dec 2019

4

2 Years 5 Months ago

By: Kevin Neilson

o New coding method for a state machine in groups in HDL

By: Weng Tianxiang on Mon, 25 Nov 2019

33

2 Years 5 Months ago

By: KJ

o Issue regarding boot qspi flash in zynq

By: richa2854 on Tue, 3 Dec 2019

0

2 Years 5 Months ago

By: richa2854

o Lattice's ECP5 - half of the program went MIA - WTF ?

By: Brane2 on Fri, 29 Nov 2019

6

2 Years 5 Months ago

By: Rick C

o SOS ! Raspberry PI - HDMI - TMDS Hamsterwork HDMI INPUT = not work

By: abirov on Fri, 29 Nov 2019

3

2 Years 5 Months ago

By: abirov

o tell me what you think!

By: consten2013 on Fri, 29 Nov 2019

1

2 Years 5 Months ago

By: consten2013

o Efinix and their Trion FPGAs

By: Brane2 on Fri, 29 Nov 2019

2

2 Years 5 Months ago

By: Rick C

o AGM vs. Gowin

By: Rick C on Sun, 17 Nov 2019

3

2 Years 5 Months ago

By: Rick C

o Lattice MachXO2/XO3/XO3D vs ECP5

By: Brane2 on Thu, 7 Nov 2019

3

2 Years 6 Months ago

By: Rick C

o AGM AG6K SoC

By: Rick C on Fri, 15 Nov 2019

2

2 Years 6 Months ago

By: Rick C

o Gowin Semiconductor, Real or Fake?

By: Rick C on Wed, 13 Nov 2019

6

2 Years 6 Months ago

By: Brane2

o Lattice XO3D New

By: Rick C on Fri, 12 Jul 2019

7

2 Years 6 Months ago

By: Michael Kellett

o FPGA config sizes

By: John Larkin on Fri, 8 Nov 2019

14

2 Years 6 Months ago

By: David Brown

o Re: Tiny CPUs for Slow Logic

By: oldben on Wed, 9 Oct 2019

9

2 Years 6 Months ago

By: Rick C

o Student seeking for Internship in Digital Design

By: Joshua Roy on Sun, 29 Sep 2019

0

2 Years 7 Months ago

By: Joshua Roy

o Here is new definition for keyword "if_2", version 2.

By: Weng Tianxiang on Fri, 27 Sep 2019

12

2 Years 7 Months ago

By: Weng Tianxiang

o How to write a correct code to do 2 writes to an array on same cycle?

By: Weng Tianxiang on Tue, 24 Sep 2019

12

2 Years 7 Months ago

By: KJ

o New keyword "if_2" for HDL is suggested for dealing with 2-write port

By: Weng Tianxiang on Wed, 25 Sep 2019

5

2 Years 7 Months ago

By: KJ

o [Fully Funded Scholarship] Research Assistantship (Spring, 2020) at

By: jg.lee on Mon, 23 Sep 2019

0

2 Years 8 Months ago

By: jg.lee

o PipelineC (again), dct example, looking for help/interest

By: Julian Kemmerer on Sat, 7 Sep 2019

0

2 Years 8 Months ago

By: Julian Kemmerer

o PipelineC (again), dct example, looking for help/interest

By: Julian Kemmerer on Sat, 7 Sep 2019

0

2 Years 8 Months ago

By: Julian Kemmerer

o Re: Philips LA PM3585 disassembler software wanted

By: smed on Wed, 28 Aug 2019

1

2 Years 8 Months ago

By: frankcovending

o VHDL TIME support in Vivado

By: Rob Gaddi on Fri, 9 Aug 2019

12

2 Years 9 Months ago

By: Rick C

o Bayer Pattern to RGB VHDL CODE

By: abirov on Sun, 11 Aug 2019

1

2 Years 9 Months ago

By: abirov

o Why differences between Merly-type and Moore-type clock-gated state

By: Weng Tianxiang on Fri, 9 Aug 2019

3

2 Years 9 Months ago

By: KJ

o New uses of FPGAs

By: camil.matiska on Mon, 8 Jul 2019

10

2 Years 9 Months ago

By: Doug McIntyre

o Re: Field update

By: Per on Mon, 15 Jul 2019

0

2 Years 10 Months ago

By: Per

o Us congress hearing of maan alsaan Money laundry ق

By: lolo sami on Mon, 8 Jul 2019

0

2 Years 10 Months ago

By: lolo sami

o Re: Field update

By: camil.matiska on Mon, 8 Jul 2019

1

2 Years 10 Months ago

By: Jon Elson

o Unique uses for the DSP48

By: Kevin Neilson on Fri, 28 Jun 2019

8

2 Years 10 Months ago

By: Kevin Neilson

o How do big compagnies use Verilog/VHDL for processor designs?

By: Benjamin Couillard on Tue, 2 Jul 2019

2

2 Years 10 Months ago

By: Tim

o HOW TO READ A 64 BIT REGISTER IN 2 CLOCK CYCLES IN VERILOG

By: Anonymous on Fri, 28 Jun 2019

1

2 Years 10 Months ago

By: gtwrek

o bare-metal ZYNQ

By: John Larkin on Wed, 12 Jun 2019

25

2 Years 11 Months ago

By: Tom Gardner

o Microchip UNI/O controller core for FPGA

By: wzab01 on Thu, 13 Jun 2019

0

2 Years 11 Months ago

By: wzab01

o Nallatech BenBlue-II software

By: terafemto on Tue, 28 May 2019

0

2 Years 11 Months ago

By: terafemto

1

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