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devel / comp.arch.fpga / How to increase data of std_logic_vector by 1 in VHDL-2002

SubjectAuthor
* How to increase data of std_logic_vector by 1 in VHDL-2002W TX
+- Re: How to increase data of std_logic_vector by 1 in VHDL-2002andrew_b
`* Re: How to increase data of std_logic_vector by 1 in VHDL-2002andrew_b
 `* Re: How to increase data of std_logic_vector by 1 in VHDL-2002W TX
  `* Re: How to increase data of std_logic_vector by 1 in VHDL-2002Tianxiang Weng
   +* Re: How to increase data of std_logic_vector by 1 in VHDL-2002Tianxiang Weng
   |`- Re: How to increase data of std_logic_vector by 1 in VHDL-2002Tianxiang Weng
   `* Re: How to increase data of std_logic_vector by 1 in VHDL-2002Anssi Saari
    `- Re: How to increase data of std_logic_vector by 1 in VHDL-2002Tianxiang Weng

1
How to increase data of std_logic_vector by 1 in VHDL-2002

<b149cee3-39a9-4f1d-bf08-8428eaf2776fn@googlegroups.com>

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Subject: How to increase data of std_logic_vector by 1 in VHDL-2002
From: wtx...@gmail.com (W TX)
Injection-Date: Mon, 24 May 2021 04:26:33 +0000
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 by: W TX - Mon, 24 May 2021 04:26 UTC

Hi,
It is a long time headache for me to increase a data of std_logic_vector by 1.

Here are examples:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;

constant ONE : std_logic_vector(7 downto 0);
signal Series_Number : std_logic_vector(7 downto 0);
....
All followings generate errors in VHDL-2002:
Series_Number <= Series_Number +1;
Series_Number <= Series_Number +'1';
Series_Number <= Series_Number+std_logic_vector(unsigned(Series_Number)+1);
Series_Number <= Series_Number+ONE;

Thank you.

Weng

Re: How to increase data of std_logic_vector by 1 in VHDL-2002

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Subject: Re: How to increase data of std_logic_vector by 1 in VHDL-2002
From: andrew.b...@gmail.com (andrew_b)
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 by: andrew_b - Mon, 24 May 2021 05:20 UTC

> Series_Number <= Series_Number+std_logic_vector(unsigned(Series_Number)+1);
> Series_Number <= std_logic_vector (unsigned (Series_Number) + 1);

Re: How to increase data of std_logic_vector by 1 in VHDL-2002

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Subject: Re: How to increase data of std_logic_vector by 1 in VHDL-2002
From: andrew.b...@gmail.com (andrew_b)
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 by: andrew_b - Mon, 24 May 2021 05:22 UTC

Series_Number <= std_logic_vector (unsigned (Series_Number) + 1);

Re: How to increase data of std_logic_vector by 1 in VHDL-2002

<5b38dfa4-5c40-4fef-bed1-798e34f1b832n@googlegroups.com>

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Subject: Re: How to increase data of std_logic_vector by 1 in VHDL-2002
From: wtx...@gmail.com (W TX)
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 by: W TX - Mon, 24 May 2021 10:00 UTC

On Sunday, May 23, 2021 at 10:22:23 PM UTC-7, andrew_b wrote:
> Series_Number <= std_logic_vector (unsigned (Series_Number) + 1);

andrew_b, thank you!!!

Weng

Re: How to increase data of std_logic_vector by 1 in VHDL-2002

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Subject: Re: How to increase data of std_logic_vector by 1 in VHDL-2002
From: wtx...@gmail.com (Tianxiang Weng)
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 by: Tianxiang Weng - Tue, 22 Jun 2021 10:18 UTC

On Monday, May 24, 2021 at 3:00:28 AM UTC-7, Tianxiang Weng wrote:
> On Sunday, May 23, 2021 at 10:22:23 PM UTC-7, andrew_b wrote:
> > Series_Number <= std_logic_vector (unsigned (Series_Number) + 1);
> andrew_b, thank you!!!
>
> Weng

Hi,
I now ha another similar problem: how to change an integer to a std_logic_vector.

Here is a code snippet:
signal X :integer range 0 to 15;
signal Y :

Re: How to increase data of std_logic_vector by 1 in VHDL-2002

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Subject: Re: How to increase data of std_logic_vector by 1 in VHDL-2002
From: wtx...@gmail.com (Tianxiang Weng)
Injection-Date: Tue, 22 Jun 2021 10:27:37 +0000
Content-Type: text/plain; charset="UTF-8"
 by: Tianxiang Weng - Tue, 22 Jun 2021 10:27 UTC

On Tuesday, June 22, 2021 at 3:18:18 AM UTC-7, Tianxiang Weng wrote:
> On Monday, May 24, 2021 at 3:00:28 AM UTC-7, Tianxiang Weng wrote:
> > On Sunday, May 23, 2021 at 10:22:23 PM UTC-7, andrew_b wrote:
> > > Series_Number <= std_logic_vector (unsigned (Series_Number) + 1);
> > andrew_b, thank you!!!
> >
> > Weng
Hi,
I now have another similar problem: how to change an integer to a std_logic_vector.in VHDL-2002.

Here is a code snippet:

signal X :integer range 0 to 15; -- X is used as an index to an array.
signal Y :std_logic_vector(3 downto 0); -- Y is a device input interface so Y data type cannot change, but X may be.

Y <= std_logic_vector(X); -- error!

Thank you.

Weng

Re: How to increase data of std_logic_vector by 1 in VHDL-2002

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Subject: Re: How to increase data of std_logic_vector by 1 in VHDL-2002
From: wtx...@gmail.com (Tianxiang Weng)
Injection-Date: Tue, 22 Jun 2021 11:19:11 +0000
Content-Type: text/plain; charset="UTF-8"
 by: Tianxiang Weng - Tue, 22 Jun 2021 11:19 UTC

On Tuesday, June 22, 2021 at 3:27:40 AM UTC-7, Tianxiang Weng wrote:
> On Tuesday, June 22, 2021 at 3:18:18 AM UTC-7, Tianxiang Weng wrote:
> > On Monday, May 24, 2021 at 3:00:28 AM UTC-7, Tianxiang Weng wrote:
> > > On Sunday, May 23, 2021 at 10:22:23 PM UTC-7, andrew_b wrote:
> > > > Series_Number <= std_logic_vector (unsigned (Series_Number) + 1);
> > > andrew_b, thank you!!!
> > >
> > > Weng
> Hi,
> I now have another similar problem: how to change an integer to a std_logic_vector.in VHDL-2002.
> Here is a code snippet:
> signal X :integer range 0 to 15; -- X is used as an index to an array.
> signal Y :std_logic_vector(3 downto 0); -- Y is a device input interface so Y data type cannot change, but X may be.
>
> Y <= std_logic_vector(X); -- error!
>
> Thank you.
>
> Weng

Hi,
In https://groups.google.com/g/comp.arch.fpga/c/vkeCNxzCvdc/m/wOk5AZVR0ksJ, I learned the solution:
Y <= std_logic_vector(to_unsigned(X, WIDTH));

Thank you.

Weng

Re: How to increase data of std_logic_vector by 1 in VHDL-2002

<sm01r8thszn.fsf@lakka.kapsi.fi>

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Subject: Re: How to increase data of std_logic_vector by 1 in VHDL-2002
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 by: Anssi Saari - Wed, 23 Jun 2021 08:42 UTC

Tianxiang Weng <wtxwtx@gmail.com> writes:

> I now ha another similar problem: how to change an integer to a std_logic_vector.
>
> Here is a code snippet:
> signal X :integer range 0 to 15;
> signal Y :

Maybe save a copy of this:

https://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

It has pretty good coverage on type conversions in VHDL.

Re: How to increase data of std_logic_vector by 1 in VHDL-2002

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Subject: Re: How to increase data of std_logic_vector by 1 in VHDL-2002
From: wtx...@gmail.com (Tianxiang Weng)
Injection-Date: Thu, 24 Jun 2021 13:54:18 +0000
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 by: Tianxiang Weng - Thu, 24 Jun 2021 13:54 UTC

On Wednesday, June 23, 2021 at 1:42:41 AM UTC-7, Anssi Saari wrote:
> Tianxiang Weng <wtx...@gmail.com> writes:
>
> > I now ha another similar problem: how to change an integer to a std_logic_vector.
> >
> > Here is a code snippet:
> > signal X :integer range 0 to 15;
> > signal Y :
> Maybe save a copy of this:
>
> https://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf
>
> It has pretty good coverage on type conversions in VHDL.

Hi,
Thank you.
When I opened the *.pdf file and planned to save it, a surprising thing happened: my computer has already had a copy of it. After downloading it, I never read it. Its name is "DRAFT Standard for Floating-Point Arithmetic P754-Draft 129", I thought it is for Floating-Point Arithmetic only, and I never use Floating-Point Arithmetic in VHDL. After your post, I changed the pdf file name to "VHDL-Type conversion".

This time I will read it carefully.

Weng


devel / comp.arch.fpga / How to increase data of std_logic_vector by 1 in VHDL-2002

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