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devel / comp.arch.fpga / Measuring ps of delays in FPGAs

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o Measuring ps of delays in FPGAspartha sarathy

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Measuring ps of delays in FPGAs

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Subject: Measuring ps of delays in FPGAs
From: gpar...@gmail.com (partha sarathy)
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 by: partha sarathy - Mon, 21 Jun 2021 13:49 UTC

Hi FPGA Experts,

How can we measure ps of delays in FPGA with minimum area and good accuracy ?
Today's TDC (Time to Digital Converter) architectures suffer lot of drawbacks
like high gate utilization, High number of delay cells required for high resolution, Longer dead time, dependant on PVT conditions etc.

Regards
Parth


devel / comp.arch.fpga / Measuring ps of delays in FPGAs

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