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devel / comp.arch.fpga / Verilog HDL Finite State Machine - detecting a decimal number

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* Verilog HDL Finite State Machine - detecting a decimal numberTanishk Singh
`- Re: Verilog HDL Finite State Machine - detecting a decimal numbergnuarm.del...@gmail.com

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Verilog HDL Finite State Machine - detecting a decimal number

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Subject: Verilog HDL Finite State Machine - detecting a decimal number
From: tanwarta...@gmail.com (Tanishk Singh)
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 by: Tanishk Singh - Sun, 7 Nov 2021 04:58 UTC

Hi all,

I am trying to build a sequence detector to detect a decimal number like 1092 when a stream of numbers from 0-9 is given as input. Do you think just changing the width of input i.e parallel inputs instead of series would result in pattern detection? I am lost in this, please help. If you have any resources around this do share them.

Re: Verilog HDL Finite State Machine - detecting a decimal number

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Subject: Re: Verilog HDL Finite State Machine - detecting a decimal number
From: gnuarm.d...@gmail.com (gnuarm.del...@gmail.com)
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 by: gnuarm.del...@gmail. - Sat, 20 Nov 2021 14:14 UTC

On Sunday, November 7, 2021 at 12:58:16 AM UTC-4, tanwart...@gmail.com wrote:
> Hi all,
>
> I am trying to build a sequence detector to detect a decimal number like 1092 when a stream of numbers from 0-9 is given as input. Do you think just changing the width of input i.e parallel inputs instead of series would result in pattern detection? I am lost in this, please help. If you have any resources around this do share them.

You can detect in parallel or sequentially as you choose. In parallel is simple, but uses more resources. If the data is arriving sequentially you will do better constructing a state machine. The states are:

IDLE - waiting for an input

NUMERIC - the last character was numeric

Logic is needed to tell if the current incoming character is a decimal digit or not. Based on that signal the transitions are -

IDLE
Decimal = 0 then remain in IDLE and perform no action.
Decimal = 1 then transition to NUMERIC state and perform no action.

NUMERIC
Decimal = 0 then transition to IDLE state and flag a number has been completed.
Decimal = 1 then remain in NUMERIC state and perform no action.

If you need to accumulate the value of the decimal number the character must be converted to a binary value and an accumulator must multiply the previous value by decimal 10 (simply add the present value to itself shifted by two and shift two more bits) and add the new binary value of the digit. Of course the accumulator value is not included on the first digit (when the present value of the state machine is "IDLE". When the flag says the last digit was received the value in the accumulator can be used.

Is that clear? I think I got all the details.

--

Rick C.

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devel / comp.arch.fpga / Verilog HDL Finite State Machine - detecting a decimal number

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