Rocksolid Light

Welcome to novaBBS (click a section below)

mail  files  register  newsreader  groups  login

Message-ID:  

Brain off-line, please wait.


devel / comp.arch.fpga / Calculation of throughput of sub-block in digital design (I)

SubjectAuthor
o Calculation of throughput of sub-block in digital design (I)Hassan Iqbal

1
Calculation of throughput of sub-block in digital design (I)

<eaa7bf0f-a92d-4ea4-9809-0d259650b080n@googlegroups.com>

  copy mid

https://www.novabbs.com/devel/article-flat.php?id=270&group=comp.arch.fpga#270

  copy link   Newsgroups: comp.arch.fpga
X-Received: by 2002:a05:600c:4602:b0:37c:d11a:e892 with SMTP id m2-20020a05600c460200b0037cd11ae892mr14817291wmo.69.1645395500306;
Sun, 20 Feb 2022 14:18:20 -0800 (PST)
X-Received: by 2002:a05:620a:56b:b0:62c:eff4:fe8d with SMTP id
p11-20020a05620a056b00b0062ceff4fe8dmr6438119qkp.459.1645395499590; Sun, 20
Feb 2022 14:18:19 -0800 (PST)
Path: i2pn2.org!i2pn.org!paganini.bofh.team!pasdenom.info!usenet-fr.net!fdn.fr!proxad.net!feeder1-2.proxad.net!209.85.128.87.MISMATCH!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail
Newsgroups: comp.arch.fpga
Date: Sun, 20 Feb 2022 14:18:19 -0800 (PST)
Injection-Info: google-groups.googlegroups.com; posting-host=84.65.5.84; posting-account=EZTXhQoAAABd8gcnPd92-pZGLzXhe3xe
NNTP-Posting-Host: 84.65.5.84
User-Agent: G2/1.0
MIME-Version: 1.0
Message-ID: <eaa7bf0f-a92d-4ea4-9809-0d259650b080n@googlegroups.com>
Subject: Calculation of throughput of sub-block in digital design (I)
From: matrixof...@googlemail.com (Hassan Iqbal)
Injection-Date: Sun, 20 Feb 2022 22:18:20 +0000
Content-Type: text/plain; charset="UTF-8"
 by: Hassan Iqbal - Sun, 20 Feb 2022 22:18 UTC

I am trying to understand the correct way to calculate throughput of a digital hardware design block that forms part of a bigger system.

Here are the few scenarios:
1. DUT takes 10 clock cycles to generate 20 bit output, then another 10 clock cycles to generate the next 20 bit output.
-> The maximum throughput is 20 bits per 10 clock cycles = 2 bits/cycle

2. DUT takes 10 clock cycles to generate the first 20 bit output, then (being pipelined) it generates a new 20 bit output ever cycle
-> The maximum throughput is 20 bits per 1 clock cycles = 20 bits/cycle

Is this correct or do I have to involve clock frequency to calculate the throughput as well?


devel / comp.arch.fpga / Calculation of throughput of sub-block in digital design (I)

1
server_pubkey.txt

rocksolid light 0.9.81
clearnet tor