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devel / comp.arch.fpga / Re: VHDL project. Connecting components to one component

SubjectAuthor
* VHDL project. Connecting components to one componentDurko Rurko
`- Re: VHDL project. Connecting components to one component嚴子清

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VHDL project. Connecting components to one component

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Subject: VHDL project. Connecting components to one component
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 by: Durko Rurko - Mon, 31 Jan 2022 16:35 UTC

Hello guys, I am student at high school interested in VHDL programming and post quantum algorithms. I have a code where algorithm is divided to three parts. Each part is a component. I would like to create another component, which will put input to one of those three components, this component will create output, this will be input to the third component and this one will create final output. Could you please help me with it ? If so, contact me please. I will provide you with all the code I have and we can discuss the solution. Thank you very much.

Re: VHDL project. Connecting components to one component

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Subject: Re: VHDL project. Connecting components to one component
From: ryc1...@gmail.com (嚴子清)
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 by: 嚴子清 - Fri, 22 Jul 2022 11:58 UTC

durk...@gmail.com 在 2022年2月1日 星期二凌晨12:35:02 [UTC+8] 的信中寫道:
> Hello guys, I am student at high school interested in VHDL programming and post quantum algorithms. I have a code where algorithm is divided to three parts. Each part is a component. I would like to create another component, which will put input to one of those three components, this component will create output, this will be input to the third component and this one will create final output. Could you please help me with it ? If so, contact me please. I will provide you with all the code I have and we can discuss the solution. Thank you very much.

HI ,
In order to connect components together, two things must be done.
First, component declaration
Second, useing PortMap syntax to connect the components

Example:Below is a Frequency divider circuit which can divide frequency from 10MHz to 1Hz by using seven components(div_10)
....
ARCHITECTURE A OF FREQUENCY_DIVIDER IS
--component declaration
COMPONENT DIV_10
PORT(
CLK_IN : IN STD_LOGIC;
CLK_OUT : OUT STD_LOGIC
);
END COMPONENT;

SIGNAL CP : STD_LOGIC_VECTOR(7 DOWNTO 0) ;
BEGIN
--connect components togather using "PORT MAP"
U0: div_10 PORT MAP (CLK_10MHz, CP(1)); --1MHz
U1: div_10 PORT MAP (CP(1), CP(2)); --100KHz
U2: div_10 PORT MAP (CP(2), CP(3)); --10KHz
U3: div_10 PORT MAP (CP(3), CP(4)); --1KHz
U4: div_10 PORT MAP (CP(4), CP(5)); --100Hz
U5: div_10 PORT MAP (CP(5), CP(6)); --10Hz
U6: div_10 PORT MAP (CP(6), CP(7)); --1Hz


devel / comp.arch.fpga / Re: VHDL project. Connecting components to one component

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