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devel / comp.arch.fpga / Magellan VHDL monitor for Basys 3 board

SubjectAuthor
o Magellan VHDL monitor for Basys 3 boardClaudio Avi Chami

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Magellan VHDL monitor for Basys 3 board

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Subject: Magellan VHDL monitor for Basys 3 board
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 by: Claudio Avi Chami - Sat, 24 Sep 2022 08:36 UTC

Magellan HW monitor for Basys 3 board - Access register banks for reading/writing via JTAG to AXI adapter. Can also monitor register values via the board seven-segment display (register address is selected through SW0-3)

https://fpgaer.tech/?p=465


devel / comp.arch.fpga / Magellan VHDL monitor for Basys 3 board

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server_pubkey.txt

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