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#define SIGILL 6 /* blech */ -- Larry Wall in perl.c from the perl source code


devel / comp.lang.vhdl

1
SubjectRepliesLast Message
o A Simple VHDL Abstraction of an Efficient Clock Prescaler Using Cascading Shift

By: Fereydoun Memarzanja on Thu, 22 Feb 2024

0

3 Months 3 Days ago

By: Fereydoun Memarzanja

o e

By: Integral West on Thu, 28 Dec 2023

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4 Months 26 Days ago

By: Integral West

o VHDL Blocks Seen As Useful

By: littlewing on Sun, 1 Oct 2023

0

7 Months 23 Days ago

By: littlewing

o Mod 6 counter using Mod 8 counter

By: NAVIN PRASATH.M ECE on Thu, 21 Sep 2023

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8 Months 4 Days ago

By: NAVIN PRASATH.M ECE

o Facing some error while running a project in vsim with intel library files.

By: Sreekanth Billupati on Sun, 10 Sep 2023

0

8 Months 15 Days ago

By: Sreekanth Billupati

o Split array assignment in and out of process?

By: littlewing on Sat, 2 Sep 2023

2

8 Months 21 Days ago

By: littlewing

o Design and Simulation of Seven Segment Decoder

By: Zohaib Ul Hassan on Wed, 16 Aug 2023

1

9 Months 9 Days ago

By: Stef

o Download WooCommerce Follow-Up Emails

By: Lazaros Gekas on Sun, 9 Jul 2023

0

10 Months 15 Days ago

By: Lazaros Gekas

o Concurrent assignment to a non-net q is not permitted

By: Indrayudh Nandy on Fri, 9 Jun 2023

2

11 Months 15 Days ago

By: gnuarm.del...@gmail.

o FPGA + ASIC PQC Security IP / hardware root of trust by Xiphera

By: Alon Refaeli on Thu, 20 Apr 2023

0

1 Year 1 Month ago

By: Alon Refaeli

o 8-bit full adder issue

By: Marco De Luca on Mon, 17 Apr 2023

2

1 Year 1 Month ago

By: Marc Guardiani

o How does a HEAD pointer end up pointing to the first node in a linked list?

By: A “Ashvin” on Tue, 24 Jan 2023

11

1 Year 3 Months ago

By: gnuarm.del...@gmail.

o Best approach using GHDL to wrap clocked VHDL

By: Damien Towning on Wed, 18 Jan 2023

1

1 Year 4 Months ago

By: KJ

o VHDL biggest shit

By: Marvin Klabacher on Tue, 18 Oct 2022

0

1 Year 7 Months ago

By: Marvin Klabacher

o VHDL Looking for clock dropout on clocks of different speeds.

By: Steve Auch-Schwelk on Thu, 29 Sep 2022

1

1 Year 7 Months ago

By: Richard Damon

o Re: Conditional compilation in VHDL?

By: jeevan DJ on Thu, 18 Aug 2022

0

1 Year 9 Months ago

By: jeevan DJ

o Re: GALs and VHDL

By: Diego Moimas on Sun, 24 Jul 2022

0

1 Year 10 Months ago

By: Diego Moimas

o Getting Rank of Elements in an Array using VHDL

By: Md Multan Biswas on Tue, 21 Jun 2022

2

1 Year 10 Months ago

By: Anssi Saari

o How entity name is resolved in architecture body

By: Tomas Whitlock on Mon, 30 May 2022

9

1 Year 11 Months ago

By: Tomas Whitlock

o `transaction `event

By: A on Wed, 1 Jun 2022

0

1 Year 11 Months ago

By: A

o Components in if-else statement

By: tushar sharma on Tue, 10 May 2022

1

2 Years ago

By: Nicolas Matringe

o Array Initialization in VHDL-2008

By: Digital Guy on Thu, 17 Feb 2022

0

2 Years 3 Months ago

By: Digital Guy

o VHDL2019 conditional compilation

By: ht lab on Mon, 14 Feb 2022

0

2 Years 3 Months ago

By: ht lab

o How to Report/Display a File Name in VHDL?

By: A on Thu, 10 Feb 2022

4

2 Years 3 Months ago

By: Nicolas Matringe

o Matlab

By: 4AI18EC074 Pranavi K on Mon, 24 Jan 2022

2

2 Years 4 Months ago

By: Stef

o ces_util_lib, yet another VHDL Utility Library?

By: Andrea Campera on Tue, 18 Jan 2022

0

2 Years 4 Months ago

By: Andrea Campera

o Process sensitivity list - why doesn't the process enter when signals

By: A on Wed, 15 Dec 2021

6

2 Years 5 Months ago

By: A

o Re: VHDL compiler and simulator for student

By: Md Rezaul Karim on Thu, 14 Oct 2021

0

2 Years 7 Months ago

By: Md Rezaul Karim

o Re: VHDL compiler and simulator for student

By: Md Rezaul Karim on Thu, 14 Oct 2021

0

2 Years 7 Months ago

By: Md Rezaul Karim

o Re: VHDL compiler and simulator for student

By: SIDDHARTH SINGH UPAD on Fri, 8 Oct 2021

0

2 Years 7 Months ago

By: SIDDHARTH SINGH UPAD

o Understanding Verilog Code

By: Rupinder Goyal on Tue, 28 Sep 2021

1

2 Years 7 Months ago

By: Motaz

o Re: printf() function like C in VHDL ?

By: Ömer Ziya AYDIN on Fri, 10 Sep 2021

1

2 Years 8 Months ago

By: Nikolaos Kavvadias

o How to manage multiple testcases in a testbench

By: Benjamin Couillard on Mon, 19 Jul 2021

2

2 Years 9 Months ago

By: KJ

o flipflop testbenech

By: Dương Dương on Wed, 12 May 2021

1

3 Years ago

By: Michael Kellett

o accumulator

By: Dương Dương on Wed, 12 May 2021

0

3 Years ago

By: Dương Dương

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