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The unfacts, did we have them, are too imprecisely few to warrant our certitude.


devel / comp.lang.forth / Re: 6 GHz stack machine

SubjectAuthor
* 6 GHz stack machineStephen Pelc
+* Re: 6 GHz stack machineBrian Fox
|+* Re: 6 GHz stack machineStephen Pelc
||`* Re: 6 GHz stack machineClive Arthur
|| `* Re: 6 GHz stack machinenone
||  `- Re: 6 GHz stack machinePaul Rubin
|`- Re: 6 GHz stack machineBrad Eckert
+- Re: 6 GHz stack machineMarcel Hendrix
+- Re: 6 GHz stack machineFourthy Forth
+* Re: 6 GHz stack machineIlya Tarasov
|+* Re: 6 GHz stack machineJurgen Pitaske
||`* Re: 6 GHz stack machineIlya Tarasov
|| `* Re: 6 GHz stack machineJurgen Pitaske
||  +- Re: 6 GHz stack machineIlya Tarasov
||  `* Re: 6 GHz stack machineHugh Aguilar
||   +- Re: 6 GHz stack machineJurgen Pitaske
||   `* Re: 6 GHz stack machineIlya Tarasov
||    +- Re: 6 GHz stack machineFourthy Forth
||    `- Re: 6 GHz stack machineHugh Aguilar
|+* Re: 6 GHz stack machinePaul Rubin
||`* Re: 6 GHz stack machineIlya Tarasov
|| +* Re: 6 GHz stack machinePaul Rubin
|| |`* Re: 6 GHz stack machineIlya Tarasov
|| | `* Re: 6 GHz stack machinePaul Rubin
|| |  +- Re: 6 GHz stack machineRick C
|| |  `* Re: 6 GHz stack machineIlya Tarasov
|| |   `* Re: 6 GHz stack machinePaul Rubin
|| |    +- Re: 6 GHz stack machineJurgen Pitaske
|| |    `- Re: 6 GHz stack machineIlya Tarasov
|| `* Re: 6 GHz stack machineJurgen Pitaske
||  `* Re: 6 GHz stack machineIlya Tarasov
||   `- Re: 6 GHz stack machineJurgen Pitaske
|`* Re: 6 GHz stack machineStephen Pelc
| +* Re: 6 GHz stack machineFourthy Forth
| |`* Re: 6 GHz stack machineStephen Pelc
| | `- Re: 6 GHz stack machineFourthy Forth
| `* Re: 6 GHz stack machineBrad Eckert
|  +- Re: 6 GHz stack machineJurgen Pitaske
|  +- Re: 6 GHz stack machinedxforth
|  +* Re: 6 GHz stack machineStephen Pelc
|  |`* Re: 6 GHz stack machineJurgen Pitaske
|  | `* Re: 6 GHz stack machineStephen Pelc
|  |  `* Re: 6 GHz stack machineJurgen Pitaske
|  |   `* Re: 6 GHz stack machineStephen Pelc
|  |    `- Re: 6 GHz stack machineRick C
|  `* Re: 6 GHz stack machineRick C
|   `* Re: 6 GHz stack machineBrad Eckert
|    +* Re: 6 GHz stack machinePaul Rubin
|    |`* Re: 6 GHz stack machineBrad Eckert
|    | `* Re: 6 GHz stack machinePaul Rubin
|    |  +* Re: 6 GHz stack machineBrad Eckert
|    |  |+- Re: 6 GHz stack machinePaul Rubin
|    |  |`- Re: 6 GHz stack machineS Jack
|    |  `* Re: 6 GHz stack machineAnton Ertl
|    |   `* Re: 6 GHz stack machineJurgen Pitaske
|    |    +- Re: 6 GHz stack machineJurgen Pitaske
|    |    `* Re: 6 GHz stack machineAnton Ertl
|    |     +* Re: 6 GHz stack machineJurgen Pitaske
|    |     |`* Re: 6 GHz stack machineJurgen Pitaske
|    |     | `- Re: 6 GHz stack machineAnton Ertl
|    |     `- Re: 6 GHz stack machinePaul Rubin
|    `* Re: 6 GHz stack machineRick C
|     +- Re: 6 GHz stack machineFourthy Forth
|     `* Re: 6 GHz stack machineJurgen Pitaske
|      `* Re: 6 GHz stack machineRick C
|       `* Re: 6 GHz stack machineFourthy Forth
|        `* Re: 6 GHz stack machineRick C
|         +- Re: 6 GHz stack machineJurgen Pitaske
|         `* Re: 6 GHz stack machineRick C
|          `- Re: 6 GHz stack machineHugh Aguilar
+* Re: 6 GHz stack machineRick C
|`* Re: 6 GHz stack machineWayne morellini
| +- Re: 6 GHz stack machineRick C
| +* Re: 6 GHz stack machinePaul Rubin
| |`* Re: 6 GHz stack machineWayne morellini
| | `* Re: 6 GHz stack machinePaul Rubin
| |  `* Re: 6 GHz stack machineRick C
| |   +* Re: 6 GHz stack machineWayne morellini
| |   |`* Re: 6 GHz stack machineRick C
| |   | `* Re: 6 GHz stack machineWayne morellini
| |   |  `* Re: 6 GHz stack machineRick C
| |   |   `* Re: 6 GHz stack machineWayne morellini
| |   |    `* Re: 6 GHz stack machineRick C
| |   |     +* Re: 6 GHz stack machinePaul Rubin
| |   |     |`- Re: 6 GHz stack machineRick C
| |   |     `* Re: 6 GHz stack machineWayne morellini
| |   |      `* Re: 6 GHz stack machineRick C
| |   |       `* Re: 6 GHz stack machineWayne morellini
| |   |        `* Re: 6 GHz stack machineRick C
| |   |         `* Re: 6 GHz stack machineWayne morellini
| |   |          `* Re: 6 GHz stack machineRick C
| |   |           +* Re: 6 GHz stack machineWayne morellini
| |   |           |`* Re: 6 GHz stack machinedxforth
| |   |           | +* Re: 6 GHz stack machineJurgen Pitaske
| |   |           | |`- Re: 6 GHz stack machineRick C
| |   |           | +- Re: 6 GHz stack machineWayne morellini
| |   |           | +- Re: 6 GHz stack machineWayne morellini
| |   |           | `- Re: 6 GHz stack machineWayne morellini
| |   |           +* Re: 6 GHz stack machineRick C
| |   |           |`* Re: 6 GHz stack machinePaul Rubin
| |   |           | +* Re: 6 GHz stack machineNickolay Kolchin
| |   |           | +- Re: 6 GHz stack machineRick C
| |   |           | +* Re: 6 GHz stack machineRick C
| |   |           | +* Re: 6 GHz stack machineNickolay Kolchin
| |   |           | +- Re: 6 GHz stack machineHugh Aguilar
| |   |           | +- Re: 6 GHz stack machineWayne morellini
| |   |           | +- Re: 6 GHz stack machineRick C
| |   |           | +- Re: 6 GHz stack machineNickolay Kolchin
| |   |           | +- Re: 6 GHz stack machineRick C
| |   |           | +- Re: 6 GHz stack machineNickolay Kolchin
| |   |           | +* Re: 6 GHz stack machineAnton Ertl
| |   |           | +- Re: 6 GHz stack machineRick C
| |   |           | +- Re: 6 GHz stack machineNickolay Kolchin
| |   |           | +- Re: 6 GHz stack machineHugh Aguilar
| |   |           | +- Re: 6 GHz stack machineRick C
| |   |           | +- Re: 6 GHz stack machineRick C
| |   |           | +* Re: 6 GHz stack machineHowerd Oakford
| |   |           | +- Re: 6 GHz stack machineWayne morellini
| |   |           | +- Re: 6 GHz stack machineJurgen Pitaske
| |   |           | +- Re: 6 GHz stack machineHugh Aguilar
| |   |           | +- Re: 6 GHz stack machineJurgen Pitaske
| |   |           | +- Re: 6 GHz stack machineminf...@arcor.de
| |   |           | +- Re: 6 GHz stack machineWayne morellini
| |   |           | +- Re: 6 GHz stack machineWayne morellini
| |   |           | +- Re: 6 GHz stack machineRick C
| |   |           | +- Re: 6 GHz stack machineWayne morellini
| |   |           | +- Re: 6 GHz stack machineJames Brakefield
| |   |           | +- Re: 6 GHz stack machineRick C
| |   |           | +* Re: 6 GHz stack machineWayne morellini
| |   |           | `- Re: 6 GHz stack machineWayne morellini
| |   |           `* Re: 6 GHz stack machineWayne morellini
| |   +* Re: 6 GHz stack machinePaul Rubin
| |   `* Re: 6 GHz stack machineBrian Fox
| `* Re: 6 GHz stack machineAndy Valencia
+* Re: 6 GHz stack machineWayne morellini
`* Re: 6 GHz stack machine

Pages:123456789
6 GHz stack machine

<sbmuh0$l0m$1@dont-email.me>

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https://www.novabbs.com/devel/article-flat.php?id=13798&group=comp.lang.forth#13798

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From: step...@vfxforth.com (Stephen Pelc)
Newsgroups: comp.lang.forth
Subject: 6 GHz stack machine
Date: Fri, 2 Jul 2021 11:49:52 -0000 (UTC)
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 by: Stephen Pelc - Fri, 2 Jul 2021 11:49 UTC

An MPE client is currently designing a new dual-stack machine. The
predicted performance is 6 GHz (instructions per second). 40 CPUs
occupy less than 1 sqare mm.

It's for real, and they have a paying client for it.

Depending on life, there may be more information at EuroForth 21 in
Rome in September. I have my EU Covid passport already.

Stephen
--
Stephen Pelc, stephen@vfxforth.com
MicroProcessor Engineering Ltd - More Real, Less Time
133 Hill Lane, Southampton SO15 5AF, England
tel: +44 (0)23 8063 1441, +44 (0)78 0390 3612, +34 649 662 974
http://www.mpeforth.com - free VFX Forth downloads

Re: 6 GHz stack machine

<60DF15E4.1070701@rogers.com>

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From: brian....@rogers.com (Brian Fox)
Newsgroups: comp.lang.forth
Subject: Re: 6 GHz stack machine
Date: Fri, 02 Jul 2021 09:34:28 -0400
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 by: Brian Fox - Fri, 2 Jul 2021 13:34 UTC

On 2021-07-02 7:49 AM, Stephen Pelc wrote:
> An MPE client is currently designing a new dual-stack machine. The
> predicted performance is 6 GHz (instructions per second). 40 CPUs
> occupy less than 1 sqare mm.
>
> It's for real, and they have a paying client for it.
>
> Depending on life, there may be more information at EuroForth 21 in
> Rome in September. I have my EU Covid passport already.
>
> Stephen
>

That's really exciting Stephen.

I have always found it tragic that Chuck's CPU ideas didn't find a home
in the bigger world.

If it's allowed can you tell us anything about the architecture.
- Which family it leans towards. shBoom perhaps?
- Maybe it's a clean room design.
- Is there are target application area?
- Are they going to make if C friendly with a few extra registers?

And with my business hat on, once it's developed is there a solid
go to market strategy? Without that it is an academic curiosity.
(again)

Re: 6 GHz stack machine

<sbn8h4$rp0$1@dont-email.me>

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From: step...@vfxforth.com (Stephen Pelc)
Newsgroups: comp.lang.forth
Subject: Re: 6 GHz stack machine
Date: Fri, 2 Jul 2021 14:40:36 -0000 (UTC)
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 by: Stephen Pelc - Fri, 2 Jul 2021 14:40 UTC

On 2 Jul 2021 at 15:34:28 CEST, "Brian Fox" <brian.fox@rogers.com> wrote:

> On 2021-07-02 7:49 AM, Stephen Pelc wrote:
>> An MPE client is currently designing a new dual-stack machine. The
>> predicted performance is 6 GHz (instructions per second). 40 CPUs
>> occupy less than 1 sqare mm.
>>
>> It's for real, and they have a paying client for it.
>>
>> Depending on life, there may be more information at EuroForth 21 in
>> Rome in September. I have my EU Covid passport already.
>>
>> Stephen
>>
>
> That's really exciting Stephen.
>
> I have always found it tragic that Chuck's CPU ideas didn't find a home
> in the bigger world.

One of the interesting parts of this design is that it is done in Verilog
using
industry standard tool chains and is prototyped in FPGAs.

The designers are getting paid for the chips. How much will be open is
yet to be seen/decided. The initial application is pretty specialised.

> If it's allowed can you tell us anything about the architecture.

It's all their own work. I can't tell you more yet.

> And with my business hat on, once it's developed is there a solid
> go to market strategy? Without that it is an academic curiosity.
> (again)

I'm working for the techies, not the capital people. It's for a practical
application that attracts capital people.

Stephen

Re: 6 GHz stack machine

<sbna7h$8r8$1@dont-email.me>

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From: cli...@nowaytoday.co.uk (Clive Arthur)
Newsgroups: comp.lang.forth
Subject: Re: 6 GHz stack machine
Date: Fri, 2 Jul 2021 16:09:35 +0100
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 by: Clive Arthur - Fri, 2 Jul 2021 15:09 UTC

On 02/07/2021 15:40, Stephen Pelc wrote:
> On 2 Jul 2021 at 15:34:28 CEST, "Brian Fox" <brian.fox@rogers.com> wrote:
>
>> On 2021-07-02 7:49 AM, Stephen Pelc wrote:
>>> An MPE client is currently designing a new dual-stack machine. The
>>> predicted performance is 6 GHz (instructions per second). 40 CPUs
>>> occupy less than 1 sqare mm.
>>>
>>> It's for real, and they have a paying client for it.
>>>
>>> Depending on life, there may be more information at EuroForth 21 in
>>> Rome in September. I have my EU Covid passport already.
>>>
>>> Stephen
>>>
>>
>> That's really exciting Stephen.
>>
>> I have always found it tragic that Chuck's CPU ideas didn't find a home
>> in the bigger world.
>
> One of the interesting parts of this design is that it is done in Verilog
> using
> industry standard tool chains and is prototyped in FPGAs.
>
> The designers are getting paid for the chips. How much will be open is
> yet to be seen/decided. The initial application is pretty specialised.
>
>> If it's allowed can you tell us anything about the architecture.
>
> It's all their own work. I can't tell you more yet.
>
>> And with my business hat on, once it's developed is there a solid
>> go to market strategy? Without that it is an academic curiosity.
>> (again)
>
> I'm working for the techies, not the capital people. It's for a practical
> application that attracts capital people.
>
> Stephen
>
I hope they've read the PSC1000 manual. Fetch and store to the return
stack and the ability to drop multiple items from it is dead handy for
locals.

eg
3r@ - copy 3rd R to TOS
5r! - TOS to 5th R
6 rdrop - drop top 6 items from R
and of course r> and >r

--
Cheers
Clive

Re: 6 GHz stack machine

<e17cc9d2-11d7-4bb8-ab79-c18ad1403f61n@googlegroups.com>

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Subject: Re: 6 GHz stack machine
From: mhx...@iae.nl (Marcel Hendrix)
Injection-Date: Fri, 02 Jul 2021 15:45:07 +0000
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 by: Marcel Hendrix - Fri, 2 Jul 2021 15:45 UTC

On Friday, July 2, 2021 at 1:49:54 PM UTC+2, Stephen Pelc wrote:
> An MPE client is currently designing a new dual-stack machine. The
> predicted performance is 6 GHz (instructions per second). 40 CPUs
> occupy less than 1 sqare mm.
>
> It's for real, and they have a paying client for it.
>
> Depending on life, there may be more information at EuroForth 21 in
> Rome in September. I have my EU Covid passport already.

Integer / floating-point? 'C' or Forth-like?
How much memory can it address (and how)?
OS?

-marcel

Re: 6 GHz stack machine

<nnd$29b950e5$4a95c345@94e42f12e9e57a1f>

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Newsgroups: comp.lang.forth
Subject: Re: 6 GHz stack machine
References: <sbmuh0$l0m$1@dont-email.me> <60DF15E4.1070701@rogers.com> <sbn8h4$rp0$1@dont-email.me> <sbna7h$8r8$1@dont-email.me>
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Date: Sat, 03 Jul 2021 12:58:25 +0200
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 by: none - Sat, 3 Jul 2021 10:58 UTC

In article <sbna7h$8r8$1@dont-email.me>,
Clive Arthur <clive@nowaytoday.co.uk> wrote:
>On 02/07/2021 15:40, Stephen Pelc wrote:
>> On 2 Jul 2021 at 15:34:28 CEST, "Brian Fox" <brian.fox@rogers.com> wrote:
>>
>>> On 2021-07-02 7:49 AM, Stephen Pelc wrote:
>>>> An MPE client is currently designing a new dual-stack machine. The
>>>> predicted performance is 6 GHz (instructions per second). 40 CPUs
>>>> occupy less than 1 sqare mm.
>>>>
>>>> It's for real, and they have a paying client for it.
>>>>
>>>> Depending on life, there may be more information at EuroForth 21 in
>>>> Rome in September. I have my EU Covid passport already.
>>>>
>>>> Stephen
>>>>
>>>
>>> That's really exciting Stephen.
>>>
>>> I have always found it tragic that Chuck's CPU ideas didn't find a home
>>> in the bigger world.
>>
>> One of the interesting parts of this design is that it is done in Verilog
>> using
>> industry standard tool chains and is prototyped in FPGAs.
>>
>> The designers are getting paid for the chips. How much will be open is
>> yet to be seen/decided. The initial application is pretty specialised.
>>
>>> If it's allowed can you tell us anything about the architecture.
>>
>> It's all their own work. I can't tell you more yet.
>>
>>> And with my business hat on, once it's developed is there a solid
>>> go to market strategy? Without that it is an academic curiosity.
>>> (again)
>>
>> I'm working for the techies, not the capital people. It's for a practical
>> application that attracts capital people.
>>
>> Stephen
>>
>I hope they've read the PSC1000 manual. Fetch and store to the return
>stack and the ability to drop multiple items from it is dead handy for
>locals.
>
>eg
>3r@ - copy 3rd R to TOS
>5r! - TOS to 5th R
>6 rdrop - drop top 6 items from R
>and of course r> and >r

That feature was present in the FIETS project in the 80's in FIG chapter
Holland. Chuck Moore with the NOVIX beat us to it,
so we never went far with it. We made an emulator though.
Glad to hear that this feature is useful. With us it never
got battle-tested.
http://www.keesmoerman.nl/e_forth.html
Choose Forth Processors
Note the 1984 award on that page!
>
>--
>Cheers
>Clive
>

Groetjes Albertwww.keesmoerman.nl/e_forth.html
--
"in our communism country Viet Nam, people are forced to be
alive and in the western country like US, people are free to
die from Covid 19 lol" duc ha
albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst

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 by: Paul Rubin - Sat, 3 Jul 2021 16:21 UTC

albert@cherry.(none) (albert) writes:
>>3r@ - copy 3rd R to TOS
>>5r! - TOS to 5th R
>>6 rdrop - drop top 6 items from R
>>and of course r> and >r
>
> That feature was present in the FIETS project in the 80's in FIG
> chapter Holland. Chuck Moore with the NOVIX beat us to it,

The Novix was able to reach into the interior of the R stack like that?
Of course then R is more like a register file.

> http://www.keesmoerman.nl/e_forth.html

This page looks interesting even though I can't read it. I'll try
google translate on it when I get a chance.

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Subject: Re: 6 GHz stack machine
From: fourthyf...@gmail.com (Fourthy Forth)
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 by: Fourthy Forth - Sun, 4 Jul 2021 05:17 UTC

On Friday, 2 July 2021 at 9:49:54 pm UTC+10, Stephen Pelc wrote:
> An MPE client is currently designing a new dual-stack machine. The
> predicted performance is 6 GHz (instructions per second). 40 CPUs
> occupy less than 1 sqare mm.
>
> It's for real, and they have a paying client for it.
>
> Depending on life, there may be more information at EuroForth 21 in
> Rome in September. I have my EU Covid passport already.
>
> Stephen
> --
> Stephen Pelc, ste...@vfxforth.com
> MicroProcessor Engineering Ltd - More Real, Less Time
> 133 Hill Lane, Southampton SO15 5AF, England
> tel: +44 (0)23 8063 1441, +44 (0)78 0390 3612, +34 649 662 974
> http://www.mpeforth.com - free VFX Forth downloads

Stephen, thank you. Good new. Pity Ga not do after all years. Ga so difficult!

Re: 6 GHz stack machine

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Subject: Re: 6 GHz stack machine
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 by: Ilya Tarasov - Sun, 4 Jul 2021 15:00 UTC

пятница, 2 июля 2021 г. в 14:49:54 UTC+3, Stephen Pelc:
> An MPE client is currently designing a new dual-stack machine. The
> predicted performance is 6 GHz (instructions per second). 40 CPUs
> occupy less than 1 sqare mm.

So clickbaiting. 6 GHz meaning 40*150MHz? This is IPS parameter (Instruction
per second), not clock speed. If instruction needs more than 1 cycle in average,
CPI (cycle per instruction) is needed as well.

Intel CPU with 6 cores, 2 threads per core, and 4 GHz clock speed...
6*2*4 = 48 GHz, hmm?
> It's for real, and they have a paying client for it.

I wonder to see a silicon chip designed without a real goal. Of course, toys or
results of author's ambitions may be done just to show it may exist.

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Subject: Re: 6 GHz stack machine
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 by: Jurgen Pitaske - Sun, 4 Jul 2021 17:38 UTC

On Sunday, 4 July 2021 at 16:00:52 UTC+1, Ilya Tarasov wrote:
> пятница, 2 июля 2021 г. в 14:49:54 UTC+3, Stephen Pelc:
> > An MPE client is currently designing a new dual-stack machine. The
> > predicted performance is 6 GHz (instructions per second). 40 CPUs
> > occupy less than 1 sqare mm.
> So clickbaiting. 6 GHz meaning 40*150MHz? This is IPS parameter (Instruction
> per second), not clock speed. If instruction needs more than 1 cycle in average,
> CPI (cycle per instruction) is needed as well.
>
> Intel CPU with 6 cores, 2 threads per core, and 4 GHz clock speed...
> 6*2*4 = 48 GHz, hmm?
> > It's for real, and they have a paying client for it.
> I wonder to see a silicon chip designed without a real goal. Of course, toys or
> results of author's ambitions may be done just to show it may exist.

Clickbaiting on CLF - who is there to clickbait?
It might just attract the Peter Forths and Hugh Aguilars.
And they have been stumm until now.

I am quite surprised about your negativity.

If a customer wants to have a chip as you describe it - fine, they pay for it.
They must have a reason to do it. An ASIC will not be cheap.

Non-disclosure Agreements are there for a REASON.
If people here like it or not is actually irrelevant.
This is normal business practice.

I do appreciate the data that Stephen is allowed to disclose.
Something is happening with a chip design and Forth - should be great news for all of us here.
We should all be positive about it.
Nothing to do with clockbaiting.

Assuming they know what they do,
they might have heard about Intel or others,
and there are multi-processor ARM chips out there now,
and they could possibly have seen
that these chips do not achieve what is required in their application.
https://arstechnica.com/information-technology/2020/03/amperes-altra-is-80-arm-cores-of-cloud-native-power-efficient-cpu/

A RISC-V can easily do 5GHz clock frequency
https://www.techpowerup.com/275463/risc-v-processor-achieves-5-ghz-frequency-at-just-1-watt-of-power
and an FPGA RISC-V running mecrisp will be faster than the 150 MHZ you want..
And you could run as many cores as fit into the relevant FPGA.
Then unfortunately without a multiprocessor Forth.
As FPGA NOW. Free of Charge for the cores...

But the designers there might have had some spare gates
to add the pre-divivers to achieve the reduced clock speed you want.

So, I assume they must have a reason and an application that pays for the project cost.

I am actually more interested to hear about 2 things:

What is the target application? Probably AI or crypto mining
How are these CPUs coupled / how do they communicate?

Will it be available for the general market or is this just an internal project and custom design.

I hope it is for the general market, otherwise sales for MPE would be limited to project work unfortunately.
And we want to see commercial Forth Software grow - at least I want to see it.
The best proof of what Forth can achieve.

Or it will there be a multiprocessor VFX - so a Greenarrays++++
For a chip we can all buy a couple of design kits for ...
This fact is hopefully not covered by NDA and Stephen can reveal it.

Fingers crossed for MPE ( and the chip ).

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Ilya Tarasov <ilya74.tarasov@gmail.com> writes:

> пятница, 2 июля 2021 г. в 14:49:54 UTC+3, Stephen Pelc:
>> An MPE client is currently designing a new dual-stack machine. The
>> predicted performance is 6 GHz (instructions per second). 40 CPUs
>> occupy less than 1 sqare mm.
>
> So clickbaiting. 6 GHz meaning 40*150MHz?

I took it to mean 40*6ghz = 240gips total. We also don't know the die
size, or what else is on the die. It could be some kind of array
processor for machine vision, or any number of other things.

Re: 6 GHz stack machine

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 by: Ilya Tarasov - Sun, 4 Jul 2021 18:30 UTC

воскресенье, 4 июля 2021 г. в 21:19:54 UTC+3, Paul Rubin:
> Ilya Tarasov <ilya74....@gmail.com> writes:
>
> > пятница, 2 июля 2021 г. в 14:49:54 UTC+3, Stephen Pelc:
> >> An MPE client is currently designing a new dual-stack machine. The
> >> predicted performance is 6 GHz (instructions per second). 40 CPUs
> >> occupy less than 1 sqare mm.
> >
> > So clickbaiting. 6 GHz meaning 40*150MHz?
> I took it to mean 40*6ghz = 240gips total. We also don't know the die
> size, or what else is on the die. It could be some kind of array
> processor for machine vision, or any number of other things.

Well, I'm really wonder to see people who can estimate 6 GHz as a clock speed.
We must not be disoriented by news and journalists reviews. In reality, clock
speed above 1 GHz is not easy to achieve, regardless of technology node.
Reasons are fine physical effects, non-ideal parameters, variations, non-ideal
routing etc etc etc. If someone draws a schematic and receive about 160 ps
(1/6 Ghz) as a summary gate delay - ok, I can fix he is entering chip making
world at a first time.

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 by: Paul Rubin - Sun, 4 Jul 2021 19:47 UTC

Ilya Tarasov <ilya74.tarasov@gmail.com> writes:
> Well, I'm really wonder to see people who can estimate 6 GHz as a
> clock speed.

Chip designers, it sounds like.

> In reality, clock speed above 1 GHz is not easy to achieve, regardless
> of technology node.

Well, chip designers manage to do it.

> If someone draws a schematic and receive about 160 ps (1/6 Ghz) as a
> summary gate delay

Do EDA tools not mostly automate that? I.e. the designer writes HDL
rather than drawing a schematic. The tools handle all the layout etc.

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 by: Ilya Tarasov - Sun, 4 Jul 2021 19:49 UTC

> Clickbaiting on CLF - who is there to clickbait?
> It might just attract the Peter Forths and Hugh Aguilars.
> And they have been stumm until now.

People are free in general and I have no goal to attract someone.
You are talking about a kind of cult with certain hierarchy and
'allowed' phrases about key points.
> I am quite surprised about your negativity.

Not every mention of Forth should generate a positive reaction

> If a customer wants to have a chip as you describe it - fine, they pay for it.
> They must have a reason to do it. An ASIC will not be cheap.

I see no list of chip features. There is only mention 'Forth has another success
but we will not tell you details'.

> I do appreciate the data that Stephen is allowed to disclose.
> Something is happening with a chip design and Forth - should be great news for all of us here.
> We should all be positive about it.

I was quite positive (in general) 10+ years ago when TechnoForth TF16 CPU was implemented
in 0.35 um silicon. After this, TechnoForth (claimed theyselves as only true Forth team in Russia)
goes to bankrupt. Slowly, step by step, but inevitable. Silicon implementation was a kind of last
chance for them to keep impressions with no real base. Indeed, their code was poor and overall
architecture inconsistent to application domain and technology. Their position, however, was
'it is Forth, and we are professional forthers, so you have no chance to understand our wisdom'.
Until bankruption.

> Nothing to do with clockbaiting.

6 GHz is clickbaiting.
> A RISC-V can easily do 5GHz clock frequency
> https://www.techpowerup.com/275463/risc-v-processor-achieves-5-ghz-frequency-at-just-1-watt-of-power

Chuck Norris can easily do many things. Do you can the same? Don't tell me about chip topology unless
you have chips routed by you personally. This is a true art with a huge list of potential problems.

> and an FPGA RISC-V running mecrisp will be faster than the 150 MHZ you want.
> And you could run as many cores as fit into the relevant FPGA.
> Then unfortunately without a multiprocessor Forth.
> As FPGA NOW. Free of Charge for the cores...

JFF design (real Forth CPUs, though).
http://fforum.winglion.ru/viewtopic.php?f=3&t=3309&p=48880#p48880

It seems you will never turn to real activity...
Keep collecting rumors about possible Forth applications ;)
> Will it be available for the general market or is this just an internal project and custom design.
>
> I hope it is for the general market, otherwise sales for MPE would be limited to project work unfortunately.

Exactly then same as for TF16 or SeaForth. Another round of empty dreams?

> Fingers crossed for MPE ( and the chip ).

Crossed fingers will certainly prevent you from doing something :)))

Re: 6 GHz stack machine

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Subject: Re: 6 GHz stack machine
From: jpita...@gmail.com (Jurgen Pitaske)
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 by: Jurgen Pitaske - Sun, 4 Jul 2021 19:50 UTC

On Sunday, 4 July 2021 at 19:30:06 UTC+1, Ilya Tarasov wrote:
> воскресенье, 4 июля 2021 г. в 21:19:54 UTC+3, Paul Rubin:
> > Ilya Tarasov <ilya74....@gmail.com> writes:
> >
> > > пятница, 2 июля 2021 г. в 14:49:54 UTC+3, Stephen Pelc:
> > >> An MPE client is currently designing a new dual-stack machine. The
> > >> predicted performance is 6 GHz (instructions per second). 40 CPUs
> > >> occupy less than 1 sqare mm.
> > >
> > > So clickbaiting. 6 GHz meaning 40*150MHz?
> > I took it to mean 40*6ghz = 240gips total. We also don't know the die
> > size, or what else is on the die. It could be some kind of array
> > processor for machine vision, or any number of other things.
> Well, I'm really wonder to see people who can estimate 6 GHz as a clock speed.
> We must not be disoriented by news and journalists reviews. In reality, clock
> speed above 1 GHz is not easy to achieve, regardless of technology node.
> Reasons are fine physical effects, non-ideal parameters, variations, non-ideal
> routing etc etc etc. If someone draws a schematic and receive about 160 ps
> (1/6 Ghz) as a summary gate delay - ok, I can fix he is entering chip making
> world at a first time.

Ilya,
we can only take what Stephen is allowed to mention.
Let us be happy that something happens on the Forth front.

How much these clock speeds or Instruction execution times vary in either direction is unclear
and will only be known when the design has been signed off at the silicon manufacturer
- or after testing when the chip exists, as you know,
and is not really important for now.
Let's hope the world has access to these chips and creates clickbaits for Forth anywhere..

Re: 6 GHz stack machine

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Subject: Re: 6 GHz stack machine
From: ilya74.t...@gmail.com (Ilya Tarasov)
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 by: Ilya Tarasov - Sun, 4 Jul 2021 19:57 UTC

> > If someone draws a schematic and receive about 160 ps (1/6 Ghz) as a
> > summary gate delay
> Do EDA tools not mostly automate that? I.e. the designer writes HDL
> rather than drawing a schematic. The tools handle all the layout etc.

OMG, you are completely missing this. EDA tools for silicon are not
masterpiece generators, it looks like MS Paint with basic set of features,
and you need to create something really smart. Automatization is very limited
because there are many factorial-based complexity in place&route algorithms.
Even for FPGA, full automatization of optimal designing is impossible. Consider
you have now not predefined layout with only routing required (predefined also
and needed to connect by special points), but a clear piece of silicon with many
layers and many modifications of every logic gate. If an idea is 'Intel can do it,
so we can do it too, especially because we are touched by the Forth spirit', you
will definitely fail.

Re: 6 GHz stack machine

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Subject: Re: 6 GHz stack machine
From: jpita...@gmail.com (Jurgen Pitaske)
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 by: Jurgen Pitaske - Sun, 4 Jul 2021 20:00 UTC

On Sunday, 4 July 2021 at 20:49:06 UTC+1, Ilya Tarasov wrote:
> > Clickbaiting on CLF - who is there to clickbait?
> > It might just attract the Peter Forths and Hugh Aguilars.
> > And they have been stumm until now.
> People are free in general and I have no goal to attract someone.
> You are talking about a kind of cult with certain hierarchy and
> 'allowed' phrases about key points.
> > I am quite surprised about your negativity.
> Not every mention of Forth should generate a positive reaction
> > If a customer wants to have a chip as you describe it - fine, they pay for it.
> > They must have a reason to do it. An ASIC will not be cheap.
> I see no list of chip features. There is only mention 'Forth has another success
> but we will not tell you details'.
> > I do appreciate the data that Stephen is allowed to disclose.
> > Something is happening with a chip design and Forth - should be great news for all of us here.
> > We should all be positive about it.
> I was quite positive (in general) 10+ years ago when TechnoForth TF16 CPU was implemented
> in 0.35 um silicon. After this, TechnoForth (claimed theyselves as only true Forth team in Russia)
> goes to bankrupt. Slowly, step by step, but inevitable. Silicon implementation was a kind of last
> chance for them to keep impressions with no real base. Indeed, their code was poor and overall
> architecture inconsistent to application domain and technology. Their position, however, was
> 'it is Forth, and we are professional forthers, so you have no chance to understand our wisdom'.
> Until bankruption.
> > Nothing to do with clockbaiting.
> 6 GHz is clickbaiting.
> > A RISC-V can easily do 5GHz clock frequency
> > https://www.techpowerup.com/275463/risc-v-processor-achieves-5-ghz-frequency-at-just-1-watt-of-power
> Chuck Norris can easily do many things. Do you can the same? Don't tell me about chip topology unless
> you have chips routed by you personally. This is a true art with a huge list of potential problems.
> > and an FPGA RISC-V running mecrisp will be faster than the 150 MHZ you want.
> > And you could run as many cores as fit into the relevant FPGA.
> > Then unfortunately without a multiprocessor Forth.
> > As FPGA NOW. Free of Charge for the cores...
> JFF design (real Forth CPUs, though).
> http://fforum.winglion.ru/viewtopic.php?f=3&t=3309&p=48880#p48880
>
> It seems you will never turn to real activity...
> Keep collecting rumors about possible Forth applications ;)
> > Will it be available for the general market or is this just an internal project and custom design.
> >
> > I hope it is for the general market, otherwise sales for MPE would be limited to project work unfortunately.
> Exactly then same as for TF16 or SeaForth. Another round of empty dreams?
> > Fingers crossed for MPE ( and the chip ).
> Crossed fingers will certainly prevent you from doing something :)))

99% of the people here with fingers crossed - including YOU - can only make it better,
as none of us
are involved in this design
or the VFX software adaptations.

So, let us just be supportive.
And positive.
The future will tell - or do you have anything more positive to offer?

Re: 6 GHz stack machine

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Subject: Re: 6 GHz stack machine
From: ilya74.t...@gmail.com (Ilya Tarasov)
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 by: Ilya Tarasov - Sun, 4 Jul 2021 20:02 UTC

> Ilya,
> we can only take what Stephen is allowed to mention.
> Let us be happy that something happens on the Forth front.

I will be happy if many Forth projects will be active, with many
approaches and a rich base of practical applications. Shrinking
Forth to a limited set of 'blessed' leaders and a fan club will lead
to fail of false leaders and disappointment of fans.

Re: 6 GHz stack machine

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Subject: Re: 6 GHz stack machine
From: jpita...@gmail.com (Jurgen Pitaske)
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 by: Jurgen Pitaske - Sun, 4 Jul 2021 20:13 UTC

On Sunday, 4 July 2021 at 21:02:11 UTC+1, Ilya Tarasov wrote:
> > Ilya,
> > we can only take what Stephen is allowed to mention.
> > Let us be happy that something happens on the Forth front.
> I will be happy if many Forth projects will be active, with many
> approaches and a rich base of practical applications. Shrinking
> Forth to a limited set of 'blessed' leaders and a fan club will lead
> to fail of false leaders and disappointment of fans.

A language is a tool for applications
- the old hammer and nail example comes to mind.

If a language - Forth included -
is not used in real applications
the world will not bother
but just use other tools which work better - or they like more.

People who like Forth, or hobbyists
will continue to use the 100+ Forth variants they now play with for the next 50 years or longer.

Re: 6 GHz stack machine

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From: step...@vfxforth.com (Stephen Pelc)
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Subject: Re: 6 GHz stack machine
Date: Sun, 4 Jul 2021 20:24:29 -0000 (UTC)
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 by: Stephen Pelc - Sun, 4 Jul 2021 20:24 UTC

On 4 Jul 2021 at 17:00:50 CEST, "Ilya Tarasov" <ilya74.tarasov@gmail.com>
wrote:

> пятница, 2 июля 2021 г. в 14:49:54 UTC+3, Stephen Pelc:
>> An MPE client is currently designing a new dual-stack machine. The
>> predicted performance is 6 GHz (instructions per second). 40 CPUs
>> occupy less than 1 sqare mm.
>
> So clickbaiting. 6 GHz meaning 40*150MHz? This is IPS parameter (Instruction
> per second), not clock speed. If instruction needs more than 1 cycle in
> average,
> CPI (cycle per instruction) is needed as well.

What I can say is limited by what I know and what I am allowed to say. MPE is
doing some tool-making for them. They have completed a fair number of chips.

No click baiting. Let's assume that 6Hz is a target figure for some unknown
process
- i.e. I don't know what it is. From what I do know, I would expect a figure
in excess
of 2GHz. That's per CPU. And I know very little about chip and FPGA design.

150MHz per CPU would happen on an FPGA.

>> It's for real, and they have a paying client for it.
>
> I wonder to see a silicon chip designed without a real goal. Of course, toys or
> results of author's ambitions may be done just to show it may exist.

Yes, there's a goal but it's not published yet. For Marcel's benefit,
it's a 32 bit integer CPU with floating point and custom instructions. The
custom instructions help with the goal.

Stephen

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Subject: Re: 6 GHz stack machine
From: ilya74.t...@gmail.com (Ilya Tarasov)
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 by: Ilya Tarasov - Sun, 4 Jul 2021 21:47 UTC

> So, let us just be supportive.
> And positive.
> The future will tell - or do you have anything more positive to offer?

Following things are just an illusion of support:
- likes
- subscriptions
- automatic acceptance of every news about Forth

Following things are closer to support:
- experimental/modeling verifications
- technical questions
- discussions
- clarifying counterexamples to avoid negative effects
- comparisons and methodology summarizing

Re: 6 GHz stack machine

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Subject: Re: 6 GHz stack machine
From: hughagui...@gmail.com (Hugh Aguilar)
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 by: Hugh Aguilar - Mon, 5 Jul 2021 00:40 UTC

On Sunday, July 4, 2021 at 1:00:53 PM UTC-7, jpit...@gmail.com wrote:
> On Sunday, 4 July 2021 at 20:49:06 UTC+1, Ilya Tarasov wrote:
> > 6 GHz is clickbaiting.
> > > A RISC-V can easily do 5GHz clock frequency
> > > https://www.techpowerup.com/275463/risc-v-processor-achieves-5-ghz-frequency-at-just-1-watt-of-power
> > Chuck Norris can easily do many things. Do you can the same? Don't tell me about chip topology unless
> > you have chips routed by you personally. This is a true art with a huge list of potential problems.

Good analogy, Ilya!
I have found, when trying to discuss MFX and the out-of-ordering of the instructions,
that people will say this is easy, and they read a magazine article about it, etc..
Maybe easily done by Chuck Norris! lol In practice, not done by anybody other than me.

> > > Fingers crossed for MPE ( and the chip ).
> > Crossed fingers will certainly prevent you from doing something :)))

Another good analogy, Ilya!
It is certainly difficult to get any work done with the fingers crossed. lol

> 99% of the people here with fingers crossed - including YOU - can only make it better,
> as none of us
> are involved in this design
> or the VFX software adaptations.
>
> So, let us just be supportive.
> And positive.

Juergen Pintaske disgusts me.
He wants the Forth community to cross their fingers for Stephen Pelc. lol
Shall we also bring Stephen coffee, shine his shoes, and sharpen his pencils?
How about a free blow-job? The Forth community is queuing up for the privilege!

> The future will tell - or do you have anything more positive to offer?

I wrote MFX back in 1994. That seemed to me like something positive to offer.
MFX was certainly a lot of work --- I had to use my brain to figure out how to do it!
Tom Hart now refuses to admit that I wrote MFX --- must be mad because
I never brought him coffee, shined his shoes or sharpened his pencils.
If he was hoping for a blow-job he should have hired John Passaniti instead of me.

Re: 6 GHz stack machine

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From: no.em...@nospam.invalid (Paul Rubin)
Newsgroups: comp.lang.forth
Subject: Re: 6 GHz stack machine
Date: Sun, 04 Jul 2021 22:12:15 -0700
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 by: Paul Rubin - Mon, 5 Jul 2021 05:12 UTC

Ilya Tarasov <ilya74.tarasov@gmail.com> writes:
> OMG, you are completely missing this. EDA tools for silicon are not
> masterpiece generators, it looks like MS Paint with basic set of features,
> and you need to create something really smart.

Ok, that's interesting to hear, I was under the impression that you
write some HDL and the EDA and the fab house take care of (most of the rest).

> Automatization is very limited because there are many factorial-based
> complexity in place&route algorithms.

I think this specific issue is not too bad and some tools use SAT
solvers for routing. The worst case instances are very hard to solve,
but they don't come up that often in practice. I've heard solving SAT
compared with freezing water: if it's below temperature X, it's solid
ice and that's easy to understand. If it's above X, it's liquid water
and that's also easy to understand. It's only difficult if the
temperature is almost exactly X, so you get a complicated phase change
phenomenon that is very hard to analyze. Similarly, the "hard" SAT
instances seem to all have a certain critical density of clauses.

Here is a good tutorial on SAT and SMT solvers:

https://yurichev.com/writings/SAT_SMT_by_example.pdf

> If an idea is 'Intel can do it, so we can do it too, especially
> because we are touched by the Forth spirit', you will definitely fail.

I think the OKAD approach mirrors other stuff written in the 1980's
after Mead & Conway's book "Introduction to VLSI Design" shook things up
a lot. You'd lay out rectangles on a screen and iirc, if a red wire
crossed a green wire, the intersection was a transitor. People did
design chips using those methods, including the GA144, but it was a lot
of work and probably becomes unmanageable for much more complex chips.

I took one of those classes so I have a little bit of familiarity with
that old stuff, but today's stuff is much fancier and I don't know much
about it, beyond having looked at some HDL code here and there.

Re: 6 GHz stack machine

<e60d1d2b-bb31-49ad-b1dd-286d64492916n@googlegroups.com>

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Subject: Re: 6 GHz stack machine
From: jpita...@gmail.com (Jurgen Pitaske)
Injection-Date: Mon, 05 Jul 2021 07:03:40 +0000
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 by: Jurgen Pitaske - Mon, 5 Jul 2021 07:03 UTC

On Monday, 5 July 2021 at 01:40:42 UTC+1, Hugh Aguilar wrote:
> On Sunday, July 4, 2021 at 1:00:53 PM UTC-7, jpit...@gmail.com wrote:
> > On Sunday, 4 July 2021 at 20:49:06 UTC+1, Ilya Tarasov wrote:
> > > 6 GHz is clickbaiting.
> > > > A RISC-V can easily do 5GHz clock frequency
> > > > https://www.techpowerup.com/275463/risc-v-processor-achieves-5-ghz-frequency-at-just-1-watt-of-power
> > > Chuck Norris can easily do many things. Do you can the same? Don't tell me about chip topology unless
> > > you have chips routed by you personally. This is a true art with a huge list of potential problems.
> Good analogy, Ilya!
> I have found, when trying to discuss MFX and the out-of-ordering of the instructions,
> that people will say this is easy, and they read a magazine article about it, etc..
> Maybe easily done by Chuck Norris! lol In practice, not done by anybody other than me.
> > > > Fingers crossed for MPE ( and the chip ).
> > > Crossed fingers will certainly prevent you from doing something :)))
> Another good analogy, Ilya!
> It is certainly difficult to get any work done with the fingers crossed. lol
> > 99% of the people here with fingers crossed - including YOU - can only make it better,
> > as none of us
> > are involved in this design
> > or the VFX software adaptations.
> >
> > So, let us just be supportive.
> > And positive.
> Juergen Pintaske disgusts me.
> He wants the Forth community to cross their fingers for Stephen Pelc. lol
> Shall we also bring Stephen coffee, shine his shoes, and sharpen his pencils?
> How about a free blow-job? The Forth community is queuing up for the privilege!
> > The future will tell - or do you have anything more positive to offer?
> I wrote MFX back in 1994. That seemed to me like something positive to offer.
> MFX was certainly a lot of work --- I had to use my brain to figure out how to do it!
> Tom Hart now refuses to admit that I wrote MFX --- must be mad because
> I never brought him coffee, shined his shoes or sharpened his pencils.
> If he was hoping for a blow-job he should have hired John Passaniti instead of me.

It was clear you would raise your ugly head as I had said in the first lines.

But that you would post more disgusting stuff than usual was a surprise -
and as usual not related to the theme of the post.

Re: 6 GHz stack machine

<fe006ce1-7b63-4d63-8464-9b86ccfa883dn@googlegroups.com>

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Subject: Re: 6 GHz stack machine
From: gnuarm.d...@gmail.com (Rick C)
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 by: Rick C - Mon, 5 Jul 2021 13:51 UTC

On Monday, July 5, 2021 at 1:12:18 AM UTC-4, Paul Rubin wrote:
> Ilya Tarasov <ilya74....@gmail.com> writes:
> > OMG, you are completely missing this. EDA tools for silicon are not
> > masterpiece generators, it looks like MS Paint with basic set of features,
> > and you need to create something really smart.
> Ok, that's interesting to hear, I was under the impression that you
> write some HDL and the EDA and the fab house take care of (most of the rest).

You can do that, but with devices that are not full custom. There are degrees of customization in ASICs. Well, there used to be gate arrays which are like metal layer programmed FPGAs. But I seem to recall they have largely been squeezed out by FPGAs getting bigger and faster. They should still be around since the full custom parts continue to get more expensive as the feature size gets smaller. Gate arrays are the traditional way of lowering the cost of FPGAs once you have been in production and are confident in the design. I know Xilinx started a program where they use the same die as their production parts, but only test to your design requirements lowering the test time, defect rate and so cost.

> > If an idea is 'Intel can do it, so we can do it too, especially
> > because we are touched by the Forth spirit', you will definitely fail.
> I think the OKAD approach mirrors other stuff written in the 1980's
> after Mead & Conway's book "Introduction to VLSI Design" shook things up
> a lot. You'd lay out rectangles on a screen and iirc, if a red wire
> crossed a green wire, the intersection was a transitor. People did
> design chips using those methods, including the GA144, but it was a lot
> of work and probably becomes unmanageable for much more complex chips.
>
> I took one of those classes so I have a little bit of familiarity with
> that old stuff, but today's stuff is much fancier and I don't know much
> about it, beyond having looked at some HDL code here and there.

I seem to recall some of the Forth community who were involved in the GA144 would denigrate Spice because they tried to model the transistors used in the part and got a poor result. But Spice is just a tool, not a model and the garbage in - garbage out rule definitely applies. It was a bit strange they held up this example as some sort of proof that traditional tools don't work in spite of the reality of working chips with any number of transistors you can imagine.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

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