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devel / comp.lang.forth / Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does it exist?

SubjectAuthor
* GreenArrays Softsim, ga4 version, does it exist?HALx Kieler
+- Re: GreenArrays Softsim, ga4 version, does it exist?Dennis Ruffer
+* Re: GreenArrays Softsim, ga4 version, does it exist?Jurgen Pitaske
|+* Re: GreenArrays Softsim, ga4 version, does it exist?HALx Kieler
||`- Re: GreenArrays Softsim, ga4 version, does it exist?Dennis Ruffer
|+* Re: GreenArrays Softsim, ga4 version, does it exist?Dennis Ruffer
||`- Re: GreenArrays Softsim, ga4 version, does it exist?Rick C
|`* Re: GreenArrays Softsim, ga4 version, does it exist?Rick C
| `* Asynchronous Logic , was GreenArrays Softsim, ga4 version, does itJan Coombs
|  +- Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does it exist?Rick C
|  +* Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does it exist?Paul Rubin
|  |+* Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, doesJan Coombs
|  ||`* Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does it exist?Rick C
|  || `* Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, doesJurgen Pitaske
|  ||  `- Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, doesRick C
|  |`* Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does it exist?Rick C
|  | `* Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does it exist?Paul Rubin
|  |  `- Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, doesRick C
|  `* Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, doesBernd Linsel
|   +- Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, doesHALx Kieler
|   `- Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, doesJan Coombs
`- Re: GreenArrays Softsim, ga4 version, does it exist?Jan Coombs

1
GreenArrays Softsim, ga4 version, does it exist?

<52a132f9-f53e-4389-a36a-2789f4481d59n@googlegroups.com>

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Subject: GreenArrays Softsim, ga4 version, does it exist?
From: halxkie...@gmail.com (HALx Kieler)
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 by: HALx Kieler - Wed, 14 Jul 2021 03:02 UTC

http://www.greenarraychips.com/home/documents/greg/cf-softsim.htm

So this document mentions a version of ColorForth's simulator that only has 4 F18 computers rather than the slightly overwhelming 144.
But for the life of me I can't figure out how to activate that mode, or if it even exists, because seemingly no other mentions of it exist on the internet.
Anyone have any leads?

Slightly unrelated, but the game TIS-100 got me back on this wild goose chase, I'm 100% convinced its directly inspired by the green arrays chip.

Thanks

Re: GreenArrays Softsim, ga4 version, does it exist?

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Subject: Re: GreenArrays Softsim, ga4 version, does it exist?
From: daruf...@gmail.com (Dennis Ruffer)
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 by: Dennis Ruffer - Thu, 15 Jul 2021 02:59 UTC

On Tuesday, July 13, 2021 at 8:02:06 PM UTC-7, HALx Kieler wrote:
> http://www.greenarraychips.com/home/documents/greg/cf-softsim.htm
>
> So this document mentions a version of ColorForth's simulator that only has 4 F18 computers rather than the slightly overwhelming 144.
> But for the life of me I can't figure out how to activate that mode, or if it even exists, because seemingly no other mentions of it exist on the internet.
> Anyone have any leads?
>
> Slightly unrelated, but the game TIS-100 got me back on this wild goose chase, I'm 100% convinced its directly inspired by the green arrays chip.
>
> Thanks

As far as I know, they were never able to successfully reproduce the chip using traditional methods. So, you have to use Okad to produce them and the design files have never been released. You have to convince GreenArrays to make whatever you want and pay for the factory run.

DaR

Re: GreenArrays Softsim, ga4 version, does it exist?

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Subject: Re: GreenArrays Softsim, ga4 version, does it exist?
From: jpita...@gmail.com (Jurgen Pitaske)
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 by: Jurgen Pitaske - Thu, 15 Jul 2021 13:37 UTC

On Wednesday, 14 July 2021 at 04:02:06 UTC+1, HALx Kieler wrote:
> http://www.greenarraychips.com/home/documents/greg/cf-softsim.htm
>
> So this document mentions a version of ColorForth's simulator that only has 4 F18 computers rather than the slightly overwhelming 144.
> But for the life of me I can't figure out how to activate that mode, or if it even exists, because seemingly no other mentions of it exist on the internet.
> Anyone have any leads?
>
> Slightly unrelated, but the game TIS-100 got me back on this wild goose chase, I'm 100% convinced its directly inspired by the green arrays chip.
>
> Thanks

I just wonder if a solution in FPGA might be an option.

Has anybody here tried this one?
http://mindworks.shoutwiki.com/wiki/Forth_Computing_on_FPGA

Re: GreenArrays Softsim, ga4 version, does it exist?

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Subject: Re: GreenArrays Softsim, ga4 version, does it exist?
From: halxkie...@gmail.com (HALx Kieler)
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 by: HALx Kieler - Thu, 15 Jul 2021 16:50 UTC

No I'm not looking for an actual chip, I'm trying to find the softsim mode that only simulated 4 of the F18's, because the default softsim inside of ColorForth is the 144 version, and I think I'd have an easier time exploring the functionality with the 4 mode which supposedly has more details about each of the chips on the screen.

Re: GreenArrays Softsim, ga4 version, does it exist?

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Subject: Re: GreenArrays Softsim, ga4 version, does it exist?
From: daruf...@gmail.com (Dennis Ruffer)
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 by: Dennis Ruffer - Fri, 16 Jul 2021 00:35 UTC

On Thursday, July 15, 2021 at 6:37:53 AM UTC-7, jpit...@gmail.com wrote:
> On Wednesday, 14 July 2021 at 04:02:06 UTC+1, HALx Kieler wrote:
> > http://www.greenarraychips.com/home/documents/greg/cf-softsim.htm
> >
> > So this document mentions a version of ColorForth's simulator that only has 4 F18 computers rather than the slightly overwhelming 144.
> > But for the life of me I can't figure out how to activate that mode, or if it even exists, because seemingly no other mentions of it exist on the internet.
> > Anyone have any leads?
> >
> > Slightly unrelated, but the game TIS-100 got me back on this wild goose chase, I'm 100% convinced its directly inspired by the green arrays chip.
> >
> > Thanks
> I just wonder if a solution in FPGA might be an option.
>
> Has anybody here tried this one?
> http://mindworks.shoutwiki.com/wiki/Forth_Computing_on_FPGA

We started working on the F18 in a FPGA model, but it was extremely slow and error prone.

DaR

Re: GreenArrays Softsim, ga4 version, does it exist?

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Subject: Re: GreenArrays Softsim, ga4 version, does it exist?
From: daruf...@gmail.com (Dennis Ruffer)
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 by: Dennis Ruffer - Fri, 16 Jul 2021 00:38 UTC

On Thursday, July 15, 2021 at 9:50:30 AM UTC-7, HALx Kieler wrote:
> No I'm not looking for an actual chip, I'm trying to find the softsim mode that only simulated 4 of the F18's, because the default softsim inside of ColorForth is the 144 version, and I think I'd have an easier time exploring the functionality with the 4 mode which supposedly has more details about each of the chips on the screen.

You really cannot work on a 4 node model on a 144 node chip. All the nodes have unique features, especially, the edge nodes. So, there is no "mode" that could adjust the features on nodes. They are hardwired to do what they do.

DaR

Re: GreenArrays Softsim, ga4 version, does it exist?

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Subject: Re: GreenArrays Softsim, ga4 version, does it exist?
From: gnuarm.d...@gmail.com (Rick C)
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 by: Rick C - Fri, 16 Jul 2021 06:29 UTC

On Thursday, July 15, 2021 at 9:37:53 AM UTC-4, jpit...@gmail.com wrote:
> On Wednesday, 14 July 2021 at 04:02:06 UTC+1, HALx Kieler wrote:
> > http://www.greenarraychips.com/home/documents/greg/cf-softsim.htm
> >
> > So this document mentions a version of ColorForth's simulator that only has 4 F18 computers rather than the slightly overwhelming 144.
> > But for the life of me I can't figure out how to activate that mode, or if it even exists, because seemingly no other mentions of it exist on the internet.
> > Anyone have any leads?
> >
> > Slightly unrelated, but the game TIS-100 got me back on this wild goose chase, I'm 100% convinced its directly inspired by the green arrays chip.
> >
> > Thanks
> I just wonder if a solution in FPGA might be an option.
>
> Has anybody here tried this one?
> http://mindworks.shoutwiki.com/wiki/Forth_Computing_on_FPGA

The Green Arrays F18A CPUs are designed at the gate level with mechanisms that are probably not supported in FPGAs. I've never seen any indication of how the asynchronous logic works at the gate level. FPGAs do not actually use logic gates. They use transmission gates controlled by configuration RAM, essentially multiplexer logic. As a result you can't do certain asynchronous logic design in FPGAs.

An F18A can be emulated using clocked logic, but it may or may not be useful depending on how accurately you wish to model the device. If you just want a functional emulation an FPGA would do the job just fine.

I asked someone at GA once if they had any objection to my doing this. The response was that they can't stop me from building such an FPGA design... but that they would not allow me to use their tools to program it. I had no interest in creating any drama, so I never bothered to follow through. It's not a hard processor to reproduce. Even the timing is much more simple than many CPUs and that may be the most complex part of the device with the many different timings depending on the various details of the instruction stream. Still simpler than emulating the timing of a processor with cache I expect.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

Re: GreenArrays Softsim, ga4 version, does it exist?

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Subject: Re: GreenArrays Softsim, ga4 version, does it exist?
From: gnuarm.d...@gmail.com (Rick C)
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 by: Rick C - Fri, 16 Jul 2021 06:34 UTC

On Thursday, July 15, 2021 at 8:35:17 PM UTC-4, daru...@gmail.com wrote:
> On Thursday, July 15, 2021 at 6:37:53 AM UTC-7, jpit...@gmail.com wrote:
> > On Wednesday, 14 July 2021 at 04:02:06 UTC+1, HALx Kieler wrote:
> > > http://www.greenarraychips.com/home/documents/greg/cf-softsim.htm
> > >
> > > So this document mentions a version of ColorForth's simulator that only has 4 F18 computers rather than the slightly overwhelming 144.
> > > But for the life of me I can't figure out how to activate that mode, or if it even exists, because seemingly no other mentions of it exist on the internet.
> > > Anyone have any leads?
> > >
> > > Slightly unrelated, but the game TIS-100 got me back on this wild goose chase, I'm 100% convinced its directly inspired by the green arrays chip..
> > >
> > > Thanks
> > I just wonder if a solution in FPGA might be an option.
> >
> > Has anybody here tried this one?
> > http://mindworks.shoutwiki.com/wiki/Forth_Computing_on_FPGA
> We started working on the F18 in a FPGA model, but it was extremely slow and error prone.

Error prone??? Why would it be error prone? If you aren't trying to emulate detailed timing, it would be a very simple design indeed. I've forgotten much of what I know about the F18A, but it is far from a complex processor. I could write HDL code for it in a few days. Most of the work in coding HDL is writing the test bench. I suppose the variations for the many different IO nodes might make it another few days.
Slow, yes. FPGAs are seldom as fast as custom chip designs.

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209

Re: GreenArrays Softsim, ga4 version, does it exist?

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From: jan4comp...@murray-microft.co.uk (Jan Coombs)
Newsgroups: comp.lang.forth
Subject: Re: GreenArrays Softsim, ga4 version, does it exist?
Date: Fri, 16 Jul 2021 11:23:37 +0100
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 by: Jan Coombs - Fri, 16 Jul 2021 10:23 UTC

On Tue, 13 Jul 2021 20:02:05 -0700 (PDT)
HALx Kieler <halxkieler@gmail.com> wrote:

> http://www.greenarraychips.com/home/documents/greg/cf-softsim.htm
>
> So this document mentions a version of ColorForth's simulator that only has 4 F18 computers rather than the slightly overwhelming 144.
> But for the life of me I can't figure out how to activate that mode, or if it even exists, because seemingly no other mentions of it exist on the internet.

> Anyone have any leads?

Search for "softsim" in this page:

https://bitlog.it/20141224_getting_started_with_the_ga144_and_arrayforth.html

More instructions here:

http://www.greenarraychips.com/home/documents/greg/cf-intro.htm

http://www.greenarraychips.com/home/documents/greg/cf-releases.htm

You might be better off putting four b16s[1] on a $16 FPGA board:-)

Jan Coombs
--

https://duckduckgo.com/?q=arrayForth+softsim&t=ffnt&atb=v102-1&ia=web

[1] b16 Processor
https://bernd-paysan.de/b16.html

Asynchronous Logic , was GreenArrays Softsim, ga4 version, does it exist?

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From: jenfhaom...@murmic.plus.com (Jan Coombs)
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Subject: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does it
exist?
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 by: Jan Coombs - Fri, 16 Jul 2021 11:26 UTC

On Thu, 15 Jul 2021 23:29:35 -0700 (PDT)
Rick C <gnuarm.deletethisbit@gmail.com> wrote:

> The Green Arrays F18A CPUs are designed at the gate level with mechanisms that are probably not supported in FPGAs. I've never seen any indication of how the asynchronous logic works at the gate level.

We accept that synchronous logic is synchronous at boundaries formed
by latches. If an FPGA design requires more than one lookup table
between latches then timing at the intermediate nodes is bounded, but
not synchronous.

Similarly an asynchronous design is asynchronous at it's boundary,
it could be asynchronous down to gate level, or could use other
techniques, such as regular logic, with signals validate by a local
thermally linked delay.

That the GreenArrays F18A processor is asynchronous at it's boundary can
be seen in that it can suspends clock generation while waiting for data
to arrive (asynchronously) on a link port.

Internally the F18A logic is not (all?) asynchronous. The processor
manual[1] states that it is necessary "to insert a nop between an
instruction that alters S, T or P9 and an add or multiply step instruction."
If the ALU logic was fully asynchronous then this extra clock cycle delay
would be unnecessary.

It is now more than 30 years since the first fully asynchronous processor
was built[2], and there are now quite a few. I am curious as to what
proportion of these are not fully asynchronous?

Jan Coombs
--

[1] See "2.4.2 Prefetch considerations" in the F18A Technology Reference
http://www.greenarraychips.com/home/documents/greg/DB001-171107-F18A.pdf

[2] "Twenty-five years ago, in December 1988, my research group at Caltech
submitted the world’s first asynchronous (“clockless”) microprocessor
design for fabrication to MOSIS."
http://authors.library.caltech.edu/43698/1/25YearsAgo.pdf

Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does it exist?

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Subject: Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does it exist?
From: gnuarm.d...@gmail.com (Rick C)
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 by: Rick C - Fri, 16 Jul 2021 12:26 UTC

On Friday, July 16, 2021 at 7:26:18 AM UTC-4, Jan Coombs wrote:
> On Thu, 15 Jul 2021 23:29:35 -0700 (PDT)
> Rick C <gnuarm.del...@gmail.com> wrote:
>
> > The Green Arrays F18A CPUs are designed at the gate level with mechanisms that are probably not supported in FPGAs. I've never seen any indication of how the asynchronous logic works at the gate level.
> We accept that synchronous logic is synchronous at boundaries formed
> by latches. If an FPGA design requires more than one lookup table
> between latches then timing at the intermediate nodes is bounded, but
> not synchronous.

Sorry, not sure what your point is? The term synchronous in logic design has nothing to do with the logic between registers.

> Similarly an asynchronous design is asynchronous at it's boundary,
> it could be asynchronous down to gate level, or could use other
> techniques, such as regular logic, with signals validate by a local
> thermally linked delay.
>
> That the GreenArrays F18A processor is asynchronous at it's boundary can
> be seen in that it can suspends clock generation while waiting for data
> to arrive (asynchronously) on a link port.
>
> Internally the F18A logic is not (all?) asynchronous. The processor
> manual[1] states that it is necessary "to insert a nop between an
> instruction that alters S, T or P9 and an add or multiply step instruction."
> If the ALU logic was fully asynchronous then this extra clock cycle delay
> would be unnecessary.

That is not a valid argument. The fact that some logic paths are not included in the asynchronous timing controls doesn't mean it's not asynchronous. It just means the designer did not want to slow the execution of the given instruction for every use rather than allow the coder the choice of running slowly for full functionality or quickly for cases where the adder output is stable. Really, this was most likely about reducing the logic used. It doesn't mean it's not asynchronous, it just means some timing is handled by the programmer.

> It is now more than 30 years since the first fully asynchronous processor
> was built[2], and there are now quite a few. I am curious as to what
> proportion of these are not fully asynchronous?
>
> Jan Coombs
> --
>
> [1] See "2.4.2 Prefetch considerations" in the F18A Technology Reference
> http://www.greenarraychips.com/home/documents/greg/DB001-171107-F18A.pdf
>
> [2] "Twenty-five years ago, in December 1988, my research group at Caltech
> submitted the world’s first asynchronous (“clockless”) microprocessor
> design for fabrication to MOSIS."
> http://authors.library.caltech.edu/43698/1/25YearsAgo.pdf

If not asynchronous, what are they? Normally the choices are synchronous or asynchronous. I'm not clear on what distinctions you are trying to make.

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does it exist?

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Newsgroups: comp.lang.forth
Subject: Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does it exist?
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 by: Paul Rubin - Fri, 16 Jul 2021 12:51 UTC

Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> writes:
> Internally the F18A logic is not (all?) asynchronous.

I thought the F18A is a normal synchronous processor, and that the GA144
is asynchronous in the sense that the separate F18A's on it are
indepdendently clocked.

Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does it exist?

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From: bl1-remo...@gmx.com (Bernd Linsel)
Newsgroups: comp.lang.forth
Subject: Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does
it exist?
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 by: Bernd Linsel - Fri, 16 Jul 2021 13:51 UTC

On 16.07.2021 13:26, Jan Coombs wrote:
>
> Internally the F18A logic is not (all?) asynchronous. The processor
> manual[1] states that it is necessary "to insert a nop between an
> instruction that alters S, T or P9 and an add or multiply step instruction."
> If the ALU logic was fully asynchronous then this extra clock cycle delay
> would be unnecessary.

The need to insert nop instructions before "+" and "+*" arises from the
fact that the F18A's ALU always generates all possible results from S
and T in parallel (altering CF dependent on P9) whenever the previous
instruction is finished, as Chuck Moore described on his colorforth.com
blog (there is a backup at https://colorforth.github.io/ ).

The individual ALU opcodes just select their result between the various
available results after awaiting ~1400 picoseconds (depending on V_DD
and T_junc), replace T and, if necessary, nip S [see "G144A12 Data
Book",
http://www.greenarraychips.com/home/documents/greg/DB002-110705-G144A12.pdf
Sect. 5.3 "Typical Instruction Timings"].

As Mr Moore implemented the adder within the ALU simply as a chain of
full adders with carry rippling from LSB to MSB instead of a more
sophisticated carry look-ahead logic, the standard ALU timing is just
sufficient for 9 bits ripple carry (so it is e.g. possible to add
0x1feff + 0x101 without a preceding nop).
A preceding "." (nop) ensures that the ALU inputs (T, S, CF, P9) remain
constant for another 1400ps, so there's enough time left to complete the
carry chain. P9 just decides if carry out of T17 is stored in CF.

From all the widespread available F18 descriptions, one can conclude
that synchronization in F18A is achieved using a kind of "delay lines"
driving the processors states instead of clocked latch chains. As the
whole processor seems to be made up in this manner, it's perfectly
legitimate to speak of a "fully asynchronous" design.

--
Bernd Linsel

Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does it exist?

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Subject: Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does
it exist?
From: halxkie...@gmail.com (HALx Kieler)
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 by: HALx Kieler - Fri, 16 Jul 2021 16:08 UTC

Jan, thanks for comprehending what I was looking for, your third link had the download for the other version of arrayForth who's simulator is the 4 version I was looking for. Thank you.

Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does it exist?

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Subject: Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does
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 by: Jan Coombs - Fri, 16 Jul 2021 18:17 UTC

On Fri, 16 Jul 2021 15:51:35 +0200
Bernd Linsel <bl1-removethis@gmx.com> wrote:

> On 16.07.2021 13:26, Jan Coombs wrote:
> >
> > Internally the F18A logic is not (all?) asynchronous. The processor
> > manual[1] states that it is necessary "to insert a nop between an
> > instruction that alters S, T or P9 and an add or multiply step instruction."
> > If the ALU logic was fully asynchronous then this extra clock cycle delay
> > would be unnecessary.
>
> The need to insert nop instructions before "+" and "+*" arises from the
> fact that the F18A's ALU always generates all possible results from S
> and T in parallel (altering CF dependent on P9) whenever the previous
> instruction is finished, as Chuck Moore described on his colorforth.com
> blog (there is a backup at https://colorforth.github.io/ ).
>
> The individual ALU opcodes just select their result between the various
> available results after awaiting ~1400 picoseconds (depending on V_DD
> and T_junc), replace T and, if necessary, nip S [see "G144A12 Data
> Book",
> http://www.greenarraychips.com/home/documents/greg/DB002-110705-G144A12.pdf
> Sect. 5.3 "Typical Instruction Timings"].
>
> As Mr Moore implemented the adder within the ALU simply as a chain of
> full adders with carry rippling from LSB to MSB instead of a more
> sophisticated carry look-ahead logic, the standard ALU timing is just
> sufficient for 9 bits ripple carry (so it is e.g. possible to add
> 0x1feff + 0x101 without a preceding nop).
> A preceding "." (nop) ensures that the ALU inputs (T, S, CF, P9) remain
> constant for another 1400ps, so there's enough time left to complete the
> carry chain. P9 just decides if carry out of T17 is stored in CF.
>
> From all the widespread available F18 descriptions, one can conclude
> that synchronization in F18A is achieved using a kind of "delay lines"
> driving the processors states instead of clocked latch chains. As the
> whole processor seems to be made up in this manner, it's perfectly
> legitimate to speak of a "fully asynchronous" design.
>
> --
> Bernd Linsel

Perhaps I was expecting too much, or being too picky? Economic
memory devices would need "delay line" timing, but I expected
that the ALU and it's output mux would use self-timed logic
gates to qualify as fully asynchronous.

Still plenty more to learn, thanks.

Jan Coombs
--

Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does it exist?

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From: jan4comp...@murray-microft.co.uk (Jan Coombs)
Newsgroups: comp.lang.forth
Subject: Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does
it exist?
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 by: Jan Coombs - Fri, 16 Jul 2021 18:26 UTC

On Fri, 16 Jul 2021 05:51:57 -0700
Paul Rubin <no.email@nospam.invalid> wrote:

> Jan Coombs <jan4comp.lang.forth@murray-microft.co.uk> writes:
> > Internally the F18A logic is not (all?) asynchronous.
>
> I thought the F18A is a normal synchronous processor, and that the GA144
> is asynchronous in the sense that the separate F18A's on it are
> indepdendently clocked.

Agreed, so did I but Bernd Linsel has now filled in much more of
the details. I was replying to Rick, who (I think) stated:

"The Green Arrays F18A CPUs are designed at the gate level with
mechanisms that are probably not supported in FPGAs. I've never
seen any indication of how the asynchronous logic works at the
gate level."

and I assumed that the two statements were linked.?:(

Jan Coombs
--

@Paul: email me?

Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does it exist?

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Subject: Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does it exist?
From: gnuarm.d...@gmail.com (Rick C)
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 by: Rick C - Sun, 18 Jul 2021 01:27 UTC

On Friday, July 16, 2021 at 8:51:59 AM UTC-4, Paul Rubin wrote:
> Jan Coombs <jenfhaom...@murmic.plus.com> writes:
> > Internally the F18A logic is not (all?) asynchronous.
> I thought the F18A is a normal synchronous processor, and that the GA144
> is asynchronous in the sense that the separate F18A's on it are
> indepdendently clocked.

No clock is supplied at all to an F18A.

What exactly is the difference between asynchronous logic and synchronous logic? I think I had this discussion with someone here who brought up many very odd styles of logic that are used for asynchronous design that I had never heard of. If you want to say that is the only asynchronous logic, fine, but I don't agree.

The F18A processors use a timing path of some sort in parallel with the logic path. The timing path determines when the result is captured in the output register. Both paths are impacted by the same effects in the manufacturing process, the die temperature and the voltage, so the timing always works at the fastest speed possible.

In synchronous logic designs the worst case timing must be identified and the supplied clock must not be faster than the worst case of the three primary conditions that impact logic delays.

Asynchronous vs. Synchronous logic has nothing to do with clocking different portions of the chip separately. That would be an asynchronous system.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does it exist?

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Subject: Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does it exist?
From: gnuarm.d...@gmail.com (Rick C)
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 by: Rick C - Sun, 18 Jul 2021 01:39 UTC

On Friday, July 16, 2021 at 2:26:09 PM UTC-4, Jan Coombs wrote:
> On Fri, 16 Jul 2021 05:51:57 -0700
> Paul Rubin <no.e...@nospam.invalid> wrote:
> > Jan Coombs <jan4comp....@murray-microft.co.uk> writes:
> > > Internally the F18A logic is not (all?) asynchronous.
> >
> > I thought the F18A is a normal synchronous processor, and that the GA144
> > is asynchronous in the sense that the separate F18A's on it are
> > indepdendently clocked.
> Agreed, so did I but Bernd Linsel has now filled in much more of
> the details. I was replying to Rick, who (I think) stated:
> "The Green Arrays F18A CPUs are designed at the gate level with
> mechanisms that are probably not supported in FPGAs. I've never
> seen any indication of how the asynchronous logic works at the
> gate level."
> and I assumed that the two statements were linked.?:(

Please don't read into my statement anything about how the F18A is designed.. I don't really know other than that it has variable timing depending on the data path used and the various factors that impact an asynchronous circuit (process, voltage and temperature).

I was simply trying to say that there is nothing in an FPGA that is intended to be used for asynchronous sequential logic design. That's something I know a bit about although one company touted an asynchronous logic FPGA, Achronix, but I don't think they are actually producing that.

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209

Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does it exist?

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Subject: Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does
it exist?
From: jpita...@gmail.com (Jurgen Pitaske)
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 by: Jurgen Pitaske - Sun, 18 Jul 2021 09:44 UTC

On Sunday, 18 July 2021 at 02:39:41 UTC+1, gnuarm.del...@gmail.com wrote:
> On Friday, July 16, 2021 at 2:26:09 PM UTC-4, Jan Coombs wrote:
> > On Fri, 16 Jul 2021 05:51:57 -0700
> > Paul Rubin <no.e...@nospam.invalid> wrote:
> > > Jan Coombs <jan4comp....@murray-microft.co.uk> writes:
> > > > Internally the F18A logic is not (all?) asynchronous.
> > >
> > > I thought the F18A is a normal synchronous processor, and that the GA144
> > > is asynchronous in the sense that the separate F18A's on it are
> > > indepdendently clocked.
> > Agreed, so did I but Bernd Linsel has now filled in much more of
> > the details. I was replying to Rick, who (I think) stated:
> > "The Green Arrays F18A CPUs are designed at the gate level with
> > mechanisms that are probably not supported in FPGAs. I've never
> > seen any indication of how the asynchronous logic works at the
> > gate level."
> > and I assumed that the two statements were linked.?:(
> Please don't read into my statement anything about how the F18A is designed. I don't really know other than that it has variable timing depending on the data path used and the various factors that impact an asynchronous circuit (process, voltage and temperature).
>
> I was simply trying to say that there is nothing in an FPGA that is intended to be used for asynchronous sequential logic design. That's something I know a bit about although one company touted an asynchronous logic FPGA, Achronix, but I don't think they are actually producing that.
>
> --
>
> Rick C.
>
> +- Get 1,000 miles of free Supercharging
> +- Tesla referral code - https://ts.la/richard11209

For some clarification, this article of Steve Furber might help.
https://apt.cs.manchester.ac.uk/ftp/pub/apt/www/async/async_desc.html

NCL is one implementation of asynchronous logic , possible to implement on any FPGA.
Faster than clocked? Probably the usual answer - depends.

Or at a more basic level, I fell over this article from the past ...
https://www.design-reuse.com/articles/5552/asynchronous-logic-large-cmos-devices-without-a-clock-tree.html

Most chips contain some aspects of asynchronous logic locally, very few are completely asynchronous.
Globally Synchronous Locally Asynchronous.
I do not know the internals of the F18, but as Chuck used his own design tools, he could do what fitted best.

It seems nobody has been interested yet to open one of these chips and check the logic,
as has been done for many older and interesting chips like the 1802
http://www.visual6502.org/images/pages/RCA_1802_die_shots.html

Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does it exist?

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Subject: Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does
it exist?
From: gnuarm.d...@gmail.com (Rick C)
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 by: Rick C - Sun, 18 Jul 2021 12:13 UTC

On Sunday, July 18, 2021 at 5:44:02 AM UTC-4, jpit...@gmail.com wrote:
> On Sunday, 18 July 2021 at 02:39:41 UTC+1, gnuarm.del...@gmail.com wrote:
> > On Friday, July 16, 2021 at 2:26:09 PM UTC-4, Jan Coombs wrote:
> > > On Fri, 16 Jul 2021 05:51:57 -0700
> > > Paul Rubin <no.e...@nospam.invalid> wrote:
> > > > Jan Coombs <jan4comp....@murray-microft.co.uk> writes:
> > > > > Internally the F18A logic is not (all?) asynchronous.
> > > >
> > > > I thought the F18A is a normal synchronous processor, and that the GA144
> > > > is asynchronous in the sense that the separate F18A's on it are
> > > > indepdendently clocked.
> > > Agreed, so did I but Bernd Linsel has now filled in much more of
> > > the details. I was replying to Rick, who (I think) stated:
> > > "The Green Arrays F18A CPUs are designed at the gate level with
> > > mechanisms that are probably not supported in FPGAs. I've never
> > > seen any indication of how the asynchronous logic works at the
> > > gate level."
> > > and I assumed that the two statements were linked.?:(
> > Please don't read into my statement anything about how the F18A is designed. I don't really know other than that it has variable timing depending on the data path used and the various factors that impact an asynchronous circuit (process, voltage and temperature).
> >
> > I was simply trying to say that there is nothing in an FPGA that is intended to be used for asynchronous sequential logic design. That's something I know a bit about although one company touted an asynchronous logic FPGA, Achronix, but I don't think they are actually producing that.
> >
> > --
> >
> > Rick C.
> >
> > +- Get 1,000 miles of free Supercharging
> > +- Tesla referral code - https://ts.la/richard11209
> For some clarification, this article of Steve Furber might help.
> https://apt.cs.manchester.ac.uk/ftp/pub/apt/www/async/async_desc.html
>
> NCL is one implementation of asynchronous logic , possible to implement on any FPGA.
> Faster than clocked? Probably the usual answer - depends.
>
> Or at a more basic level, I fell over this article from the past ...
> https://www.design-reuse.com/articles/5552/asynchronous-logic-large-cmos-devices-without-a-clock-tree.html
>
> Most chips contain some aspects of asynchronous logic locally, very few are completely asynchronous.
> Globally Synchronous Locally Asynchronous.
> I do not know the internals of the F18, but as Chuck used his own design tools, he could do what fitted best.
>
> It seems nobody has been interested yet to open one of these chips and check the logic,
> as has been done for many older and interesting chips like the 1802
> http://www.visual6502.org/images/pages/RCA_1802_die_shots.html

One of the reasons why I'm not so interested in asynchronous logic is because there are few applications where the speed advantage can be utilized. While the chips are asynchronous at the logic level, there are few applications that are asynchronous in nature. The end result is the logic in an asynchronous logic chip simply spends more time waiting for the synchronization signal.

While an asynchronous logic CPU can run faster because it doesn't need to spend time for the worse case logic settling time, at the system level it still has to account for the same worse case logic settling time due to PVT (process, voltage, temperature). So in the end you can only use the same number of instructions to assure your CPU does not run too slowly.

In a similar discussion someone pointed out a networking application where this is not a limitation. It seems that processing incoming IP packets is often done in software and when the load becomes heavy it is common for packets to be dropped. An asynchronous logic processor can take advantage of any excess performance available when the load is heavy and process a few more packets than an otherwise equivalent synchronous logic processor. I don't know of any other apps where an asynchronous logic processor would have a speed advantage at the system level.

--

Rick C.

++ Get 1,000 miles of free Supercharging
++ Tesla referral code - https://ts.la/richard11209

Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does it exist?

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Subject: Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does it exist?
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 by: Paul Rubin - Sun, 18 Jul 2021 19:06 UTC

Rick C <gnuarm.deletethisbit@gmail.com> writes:
> No clock is supplied at all to an F18A.

I thought each F18A was clocked by a ring oscillator, but maybe I don't
understand what that is actually for.

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<20210716122615.2231d2f6@t530> <87lf662zgy.fsf@nightsong.com>
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Subject: Re: Asynchronous Logic , was GreenArrays Softsim, ga4 version, does
it exist?
From: gnuarm.d...@gmail.com (Rick C)
Injection-Date: Mon, 19 Jul 2021 10:10:29 +0000
Content-Type: text/plain; charset="UTF-8"
 by: Rick C - Mon, 19 Jul 2021 10:10 UTC

On Sunday, July 18, 2021 at 3:06:56 PM UTC-4, Paul Rubin wrote:
> Rick C <gnuarm.del...@gmail.com> writes:
> > No clock is supplied at all to an F18A.
> I thought each F18A was clocked by a ring oscillator, but maybe I don't
> understand what that is actually for.

Whatever the clocking mechanism is, it is internal to the F18A. That's my point. No clock is supplied.

--

Rick C.

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