\ Op Code File for MFX. Generated by MAKE-OPS v13

\ MODELS\RACE32\RACE32.ops

\ src dst codes J I H G F E D C B A 9 8 7 6 5 4 3 2 1 0
\ `--.--' `-.-' | | | | | | | | | | |
\ errors -------------' | | | | | | | | | | | |
\ constants -----------------' | | | | | | | | | | | - c8_6_5_3
\ stack ptr mem ---------------------' | | | | | | | | | | - S PM
\ loop ctr ----------------------------' | | | | | | | | | - L LC
\ return reg ----------------------------' | | | | | | | | - R RR
\ prog ctr --------------------------------' | | | | | | | - P PC
\ mem ads -----------------------------------' | | | | | | - F FLG
\ flag ----------------------------------------' | | | | | - M MA
\ carry -----------------------------------------' | | | | - C CRY
\ data reg ----------------------------------------' | | | - D DR
\ Treg high (sos) -----------------------------------' | | - T TH
\ Treg low (sos) --------------------------------------' | - t TL
\ accumulator (tos) -------------------------------------' - A AC

\ Deferred cmds:
\ Dsrc Ddst codes J I H G F E D C B A 9 8 7 6 5 4 3 2 1 0
\ `--.--' `-.-' | | | | | | |
\ errors -------------' | | | | | | | |
\ constants -----------------' | | | | | | |
\ i/o -------------------------------------' | | | | | |
\ static mem --------------------------------' | | | | |
\ dynamic mem ---------------------------------' | | | |
\ reg mem ---------------------------------------' | | |
\ Treg high (sos) -----------------------------------' | |
\ Treg low (sos) --------------------------------------' |
\ accumulator (tos) -------------------------------------'

\ now deferred now deferred
\ code type src dst Dsrc Ddst instr string emultion emulation operation
0 1 >XBCS tT D - - H" TR>DR" ' EMU_TR>DR ' NOP SIMPLE-OP: TR>DR
1 1 >XBCS D tT - - H" DR>TR" ' EMU_DR>TR ' NOP SIMPLE-OP: DR>TR
2 1 >XBCS A D - - H" AC>DR" ' EMU_AC>DR ' NOP SIMPLE-OP: AC>DR
3 1 >XBCS A F - - H" TR15>FLG" ' EMU_TR15>FLG ' NOP SIMPLE-OP: TR15>FLG
1 2 >XBCS - tT - - H" -1>TRL" ' EMU_-1>TRL ' NOP SIMPLE-OP: -1>TRL
2 2 >XBCS - tT - - H" -1>TRH" ' EMU_-1>TRH ' NOP SIMPLE-OP: -1>TRH
3 2 >XBCS - tT - - H" -1>TR" ' EMU_-1>TR ' NOP SIMPLE-OP: -1>TR
0 3 >XBCS - D - - H" 0>DR" ' EMU_0>DR ' NOP SIMPLE-OP: 0>DR
1 3 >XBCS - tT - - H" 0>TRL" ' EMU_0>TRL ' NOP SIMPLE-OP: 0>TRL
2 3 >XBCS - tT - - H" 0>TRH" ' EMU_0>TRH ' NOP SIMPLE-OP: 0>TRH
3 3 >XBCS - tT - - H" 0>TR" ' EMU_0>TR ' NOP SIMPLE-OP: 0>TR
0 4 >XBCS A D - - H" AC>DR" ' EMU_AC>DR ' NOP SIMPLE-OP: AC>DR
1 4 >XBCS A tT - - H" AC>TR" ' EMU_AC>TR ' NOP SIMPLE-OP: AC>TR
2 4 >XBCS AtT D - - H" AC_OR_TR>DR" ' EMU_AC_OR_TR>DR ' NOP SIMPLE-OP: AC_OR_TR>DR
3 4 >XBCS AD tT - - H" AC_AND_DR>TR" ' EMU_AC_AND_DR>TR ' NOP SIMPLE-OP: AC_AND_DR>TR
0 5 >XBCS - C - - H" 0>CRY" ' EMU_0>CRY ' NOP SIMPLE-OP: 0>CRY
1 5 >XBCS - C - - H" 1>CRY" ' EMU_1>CRY ' NOP SIMPLE-OP: 1>CRY
2 5 >XBCS C CF - - H" 0>CRY>FLG" ' EMU_0>CRY>FLG ' NOP SIMPLE-OP: 0>CRY>FLG
3 5 >XBCS CF CF - - H" CRY><FLG" ' EMU_CRY><FLG ' NOP SIMPLE-OP: CRY><FLG
\ code type src dst Dsrc Ddst instr string emultion emulation operation
0 6 >XBCS c6 L - - H" C6>REP" ' EMU_C6>REP ' NOP SIMPLE-OP: C6>REP
1 6 >XBCS Ac6 DL - - H" C6>REP~AC>DR" ' EMU_C6>REP~AC>DR ' NOP SIMPLE-OP: C6>REP~AC>DR
2 6 >XBCS tTc6 DL - - H" C6>REP~TR>DR" ' EMU_C6>REP~TR>DR ' NOP SIMPLE-OP: C6>REP~TR>DR
3 6 >XBCS tTDc6 tTDL - - H" C6>REP~TR><DR" ' EMU_C6>REP~TR><DR ' NOP SIMPLE-OP: C6>REP~TR><DR
0 7 >XBCS AtTc6 DL - - H" C6&AC>REP~0>DR" ' EMU_C6&AC>REP~0>DR ' NOP SIMPLE-OP: C6&AC>REP~0>DR
1 7 >XBCS AtTc6 DL - - H" C6&/AC>REP~0>DR" ' EMU_C6&/AC>REP~0>D ' NOP SIMPLE-OP: C6&/AC>REP~0>DR
2 7 >XBCS c6 L - - H" C6>LOOP" ' EMU_C6>LOOP ' NOP SIMPLE-OP: C6>LOOP
8 >CS - - A r H" AC>*MA_d" ' EMU_AC>*MA ' EMU_WE4 SIMPLE-OP: AC>*MA_d
9 >CS A tT - - H" AC>TRx" ' EMU_AC>TR ' NOP SIMPLE-OP: AC>TRx
1 A >XBCS - - A rds H" AC>*MA_BYT_d" ' EMU_AC>*MA_BYT ' EMU_WE1 SIMPLE-OP: AC>*MA_BYT_d
2 A >XBCS - - A rdso H" ACLW>*MA_d" ' EMU_ACLW>*MA ' EMU_WE2 SIMPLE-OP: ACLW>*MA_d
3 A >XBCS - - A rdso H" ACHW>*MA_d" ' EMU_ACHW>*MA ' EMU_WE3 SIMPLE-OP: ACHW>*MA_d
1 B >XBCS A tT A r H" AC>TR~AC>*MA_d" ' EMU_AC>TR ' EMU_WE4 SIMPLE-OP: AC>TR~AC>*MA_d
2 B >XBCS A D A r H" AC>DR~AC>*MA_d" ' EMU_AC>DR ' EMU_WE4 SIMPLE-OP: AC>DR~AC>*MA_d
3 B >XBCS - - A - H" AC>TR(CS)_d" ' EMU_AC>TR(CS) ' EMU_WE7 SIMPLE-OP: AC>TR(CS)_d
1 C >XBCS - tT ro tT H" *MA>TRL_d" ' EMU_*MA>TRL ' EMU_RE1 SIMPLE-OP: *MA>TRL_d
2 C >XBCS - tT rds tT H" *MA>TRH_d" ' EMU_*MA>TRH ' EMU_RE2 SIMPLE-OP: *MA>TRH_d
3 C >XBCS - tT r tT H" *MA>TR_d" ' EMU_*MA>TR ' EMU_RE3 SIMPLE-OP: *MA>TR_d
1 D >XBCS A tTD r tT H" AC>DR~*MA>TR_d" ' EMU_AC>DR ' EMU_RE3 SIMPLE-OP: AC>DR~*MA>TR_d
\ code type src dst Dsrc Ddst instr string emultion emulation operation
2 D >XBCS tT tTD r tT H" TR>DR~*MA>TR_d" ' EMU_TR>DR ' EMU_RE3 SIMPLE-OP: TR>DR~*MA>TR_d
F >CS - tT ro tT H" *MA>NXT_d" ' EMU_*MA>NXT ' EMU_RE4 SIMPLE-OP: *MA>NXT_d
0 10 >XBCS CPc6 P - - H" IF_CRY+JMP" ' EMU_IF_CRY+JMP ' NOP COUNT-OP: IF_CRY+JMP
1 10 >XBCS CPc6 P - - H" IF/CRY+JMP" ' EMU_IF/CRY+JMP ' NOP COUNT-OP: IF/CRY+JMP
2 10 >XBCS FPc6 P - - H" IF_FLG+JMP" ' EMU_IF_FLG+JMP ' NOP COUNT-OP: IF_FLG+JMP
3 10 >XBCS FPc6 P - - H" IF/FLG+JMP" ' EMU_IF/FLG+JMP ' NOP COUNT-OP: IF/FLG+JMP
0 11 >XBCS APc6 P - - H" IF_AC0+JMP" ' EMU_IF_AC0+JMP ' NOP COUNT-OP: IF_AC0+JMP
1 11 >XBCS APc6 P - - H" IF/AC0+JMP" ' EMU_IF/AC0+JMP ' NOP COUNT-OP: IF/AC0+JMP
2 11 >XBCS APc6 P - - H" IF_AC31+JMP" ' EMU_IF_AC31+JMP ' NOP COUNT-OP: IF_AC31+JMP
3 11 >XBCS APc6 P - - H" IF/AC31+JMP" ' EMU_IF/AC31+JMP ' NOP COUNT-OP: IF/AC31+JMP
0 12 >XBCS CPc6 P - - H" IF_CRY-JMP" ' EMU_IF_CRY-JMP ' NOP COUNT-OP: IF_CRY-JMP
1 12 >XBCS CPc6 P - - H" IF/CRY-JMP" ' EMU_IF/CRY-JMP ' NOP COUNT-OP: IF/CRY-JMP
2 12 >XBCS FPc6 P - - H" IF_FLG-JMP" ' EMU_IF_FLG-JMP ' NOP COUNT-OP: IF_FLG-JMP
3 12 >XBCS FPc6 P - - H" IF/FLG-JMP" ' EMU_IF/FLG-JMP ' NOP COUNT-OP: IF/FLG-JMP
0 13 >XBCS APc6 P - - H" IF_AC0-JMP" ' EMU_IF_AC0-JMP ' NOP COUNT-OP: IF_AC0-JMP
1 13 >XBCS APc6 P - - H" IF/AC0-JMP" ' EMU_IF/AC0-JMP ' NOP COUNT-OP: IF/AC0-JMP
2 13 >XBCS APc6 P - - H" IF_AC31-JMP" ' EMU_IF_AC31-JMP ' NOP COUNT-OP: IF_AC31-JMP
3 13 >XBCS APc6 P - - H" IF/AC31-JMP" ' EMU_IF/AC31-JMP ' NOP COUNT-OP: IF/AC31-JMP
0 14 >XBCS Pc8 P - - H" +JMP" ' EMU_+JMP ' NOP COUNT-OP: +JMP
\ code type src dst Dsrc Ddst instr string emultion emulation operation
1 14 >XBCS APc6 P - - H" IF/AC1+JMP" ' EMU_IF/AC1+JMP ' NOP COUNT-OP: IF/AC1+JMP
2 14 >XBCS APc6 P - - H" IF/AC2+JMP" ' EMU_IF/AC2+JMP ' NOP COUNT-OP: IF/AC2+JMP
3 14 >XBCS APc6 P - - H" IF/AC3+JMP" ' EMU_IF/AC3+JMP ' NOP COUNT-OP: IF/AC3+JMP
0 15 >XBCS APc6 P - - H" IF/AC4+JMP" ' EMU_IF/AC4+JMP ' NOP COUNT-OP: IF/AC4+JMP
1 15 >XBCS APc6 P - - H" IF/AC5+JMP" ' EMU_IF/AC5+JMP ' NOP COUNT-OP: IF/AC5+JMP
2 15 >XBCS APc6 P - - H" IF/AC6+JMP" ' EMU_IF/AC6+JMP ' NOP COUNT-OP: IF/AC6+JMP
3 15 >XBCS APc6 P - - H" IF/AC7+JMP" ' EMU_IF/AC7+JMP ' NOP COUNT-OP: IF/AC7+JMP
0 16 >XBCS Pc8 P - - H" -JMP" ' EMU_-JMP ' NOP COUNT-OP: -JMP
1 16 >XBCS PLc6 P - - H" IF_REP-JMP" ' EMU_IF_REP-JMP ' NOP COUNT-OP: IF_REP-JMP
2 16 >XBCS c8 P - - H" JMP&LINK" ' EMU_JMP&LINK ' NOP COUNT-OP: JMP&LINK
3 16 >XBCS R P - - H" RET_LINK" ' EMU_RET_LINK ' NOP COUNT-OP: RET_LINK
0 17 >XBCS t tT - - H" TR_RL" ' EMU_TR_RL ' NOP SIMPLE-OP: TR_RL
1 17 >XBCS At tT - - H" TR_RL_DR" ' EMU_TR_RL_DR ' NOP SIMPLE-OP: TR_RL_DR
2 17 >XBCS tD tT - - H" TR_RL_AC" ' EMU_TR_RL_AC ' NOP SIMPLE-OP: TR_RL_AC
3 17 >XBCS tTC tTC - - H" TR_RLC" ' EMU_TR_RLC ' NOP SIMPLE-OP: TR_RLC
0 18 >XBCS tT tT - - H" TR_RR" ' EMU_TR_RR ' NOP SIMPLE-OP: TR_RR
1 18 >XBCS tT tT - - H" TR_RR_DR" ' EMU_TR_RR_DR ' NOP SIMPLE-OP: TR_RR_DR
2 18 >XBCS tT tT - - H" TR_RR_AC" ' EMU_TR_RR_AC ' NOP SIMPLE-OP: TR_RR_AC
3 18 >XBCS tT tTC - - H" TR_RRC" ' EMU_TR_RRC ' NOP SIMPLE-OP: TR_RRC
\ code type src dst Dsrc Ddst instr string emultion emulation operation
0 19 >XBCS tT tT - - H" TR_RRB" ' EMU_TR_RRB ' NOP SIMPLE-OP: TR_RRB
1 19 >XBCS tT tT - - H" TR_RRB_DR" ' EMU_TR_RRB_DR ' NOP SIMPLE-OP: TR_RRB_DR
2 19 >XBCS tT tT - - H" TR_RRB_AC" ' EMU_TR_RRB_AC ' NOP SIMPLE-OP: TR_RRB_AC
3 19 >XBCS tT tT - - H" TR_SRB" ' EMU_TR_SRB ' NOP SIMPLE-OP: TR_SRB
0 1A >XBCS D D - - H" DR_RL" ' EMU_DR_RL ' NOP SIMPLE-OP: DR_RL
1 1A >XBCS D D - - H" DR_RL" ' EMU_DR_RL ' NOP SIMPLE-OP: DR_RL
2 1A >XBCS tD D - - H" DR_RL-TR" ' EMU_DR_RL_TR ' NOP SIMPLE-OP: DR_RL-TR
3 1A >XBCS DC DC - - H" DR_RLC" ' EMU_DR_RLC ' NOP SIMPLE-OP: DR_RLC
0 1B >XBCS D D - - H" DR_RR" ' EMU_DR_RR ' NOP SIMPLE-OP: DR_RR
1 1B >XBCS AD D - - H" DR_RR_AC" ' EMU_DR_RR_AC ' NOP SIMPLE-OP: DR_RR_AC
2 1B >XBCS TD D - - H" DR_RR_TR" ' EMU_DR_RR_TR ' NOP SIMPLE-OP: DR_RR_TR
3 1B >XBCS DC DC - - H" DR_RRC" ' EMU_DR_RRC ' NOP SIMPLE-OP: DR_RRC
0 1C >XBCS D D - - H" DR_RRB" ' EMU_DR_RRB ' NOP SIMPLE-OP: DR_RRB
1 1C >XBCS AD D - - H" DR_RRB_AC" ' EMU_DR_RRB_AC ' NOP SIMPLE-OP: DR_RRB_AC
2 1C >XBCS tD D - - H" DR_RRB_TR" ' EMU_DR_RRB_TR ' NOP SIMPLE-OP: DR_RRB_TR
3 1C >XBCS D D - - H" DR_SRB" ' EMU_DR_SRB ' NOP SIMPLE-OP: DR_SRB
2 1D >XBCS tD tTD - - H" TR_DR_RL_AC" ' EMU_TR_DR_RL_AC ' NOP SIMPLE-OP: TR_DR_RL_AC
0 1E >XBCS tTD tTD - - H" TR_DR_RR" ' EMU_TR_DR_RR ' NOP SIMPLE-OP: TR_DR_RR
2 1E >XBCS AtTD tTD - - H" TR_DR_RR_AC" ' EMU_TR_DR_RR_AC ' NOP SIMPLE-OP: TR_DR_RR_AC
\ code type src dst Dsrc Ddst instr string emultion emulation operation
2 1F >XBCS tTD tTD - - H" TR_DR_RRB_AC" ' EMU_TR_DR_RRB_AC ' NOP SIMPLE-OP: TR_DR_RRB_AC
0 >MA - M - - H" hold" ' EMU_MA>MA ' NOP JMPL-OP: hold
1 0 >MAPT A M - - H" IP>MA" ' EMU_PM>MA ' NOP JMPL-OP: IP>MA
1 1 >MAPT A M - - H" RP>MA" ' EMU_PM>MA ' NOP JMPL-OP: RP>MA
1 2 >MAPT A M - - H" SP>MA" ' EMU_PM>MA ' NOP JMPL-OP: SP>MA
1 3 >MAPT A M - - H" DP>MA" ' EMU_PM>MA ' NOP JMPL-OP: DP>MA
1 4 >MAPT Sc5 M - - H" MA+C>MA" ' EMU_MA+C>MA ' NOP JMPL-OP: MA+C>MA
1 5 >MAPT Sc5 M - - H" MA-C>MA" ' EMU_MA-C>MA ' NOP JMPL-OP: MA-C>MA
1 6 >MAPT Sc5 M - - H" MA+C>MAu" ' EMU_MA+C>MA ' NOP JMPL-OP: MA+C>MAu
1 7 >MAPT Sc5 M - - H" MA-C>MAu" ' EMU_MA-C>MA ' NOP JMPL-OP: MA-C>MAu
2 >MA M M - - H" AC>MA" ' EMU_AC>MA ' NOP JMPL-OP: AC>MA
3 >MA tTS M - - H" MA-TR>MAu" ' EMU_MA-TR>MA ' NOP JMPL-OP: MA-TR>MAu
4 >MA Mc6 M - - H" AC+C8>MA" ' EMU_AC+C8>MA ' NOP JMPL-OP: AC+C8>MA
5 0 >MAPT A M - - H" IP+2>MAu" ' EMU_PM+2>MA ' NOP JMPL-OP: IP+2>MAu
5 1 >MAPT tT M - - H" TR>MAu" ' EMU_TR>MA ' NOP JMPL-OP: TR>MAu
5 2 >MAPT tT M - - H" TR+2>MAu" ' EMU_TR+2>MA ' NOP JMPL-OP: TR+2>MAu
5 5 >MAPT tT M - - H" TR>MA" ' EMU_TR>MA ' NOP JMPL-OP: TR>MA
5 6 >MAPT tT M - - H" TR+2>MA" ' EMU_TR+2>MA ' NOP JMPL-OP: TR+2>MA
5 7 >MAPT S M - - H" MA+4>MA" ' EMU_MA+4>MA ' NOP JMPL-OP: MA+4>MA
\ code type src dst Dsrc Ddst instr string emultion emulation operation
6 0 >MAPT Ac5 M - - H" IP+C>MA" ' EMU_PM+C>MA ' NOP JMPL-OP: IP+C>MA
6 1 >MAPT Ac5 M - - H" RP+C>MA" ' EMU_PM+C>MA ' NOP JMPL-OP: RP+C>MA
6 2 >MAPT Ac5 M - - H" SP+C>MA" ' EMU_PM+C>MA ' NOP JMPL-OP: SP+C>MA
6 3 >MAPT Ac3 M - - H" DP+C5>MA" ' EMU_PM+C5>MA ' NOP JMPL-OP: DP+C5>MA
6 4 >MAPT Ac5 M - - H" IP+C>MAu" ' EMU_PM+C>MA ' NOP JMPL-OP: IP+C>MAu
6 5 >MAPT Ac5 M - - H" RP+C>MAu" ' EMU_PM+C>MA ' NOP JMPL-OP: RP+C>MAu
6 6 >MAPT Ac5 M - - H" SP+C>MAu" ' EMU_PM+C>MA ' NOP JMPL-OP: SP+C>MAu
6 7 >MAPT Ac3 M - - H" DP+C5>MAu" ' EMU_PM+C5>MA ' NOP JMPL-OP: DP+C5>MAu
7 0 >MAPT Ac5 M - - H" IP-C>MA" ' EMU_PM-C>MA ' NOP JMPL-OP: IP-C>MA
7 1 >MAPT Ac5 M - - H" RP-C>MA" ' EMU_PM-C>MA ' NOP JMPL-OP: RP-C>MA
7 2 >MAPT Ac5 M - - H" SP-C>MA" ' EMU_PM-C>MA ' NOP JMPL-OP: SP-C>MA
7 3 >MAPT Ac3 M - - H" DP-C5>MA" ' EMU_PM-C5>MA ' NOP JMPL-OP: DP-C5>MA
7 4 >MAPT Ac5 M - - H" IP-C>MAu" ' EMU_PM-C>MA ' NOP JMPL-OP: IP-C>MAu
7 5 >MAPT Ac5 M - - H" RP-C>MAu" ' EMU_PM-C>MA ' NOP JMPL-OP: RP-C>MAu
7 6 >MAPT Ac5 M - - H" SP-C>MAu" ' EMU_PM-C>MA ' NOP JMPL-OP: SP-C>MAu
7 7 >MAPT Ac3 M - - H" DP-C5>MAu" ' EMU_PM-C5>MA ' NOP JMPL-OP: DP-C5>MAu
1 >AC AM0 FM A - - H" MA>AC" ' EMU_MA>AC ' NOP SIMPLE-OP: MA>AC
2 0 >ACRA AM0 A AC - - H" AC-1>ACC" ' EMU_AC-1>ACC ' NOP SIMPLE-OP: AC-1>ACC
2 1 >ACRA AM0 A AC - - H" AC+1>ACC" ' EMU_AC+1>ACC ' NOP SIMPLE-OP: AC+1>ACC
\ code type src dst Dsrc Ddst instr string emultion emulation operation
2 2 >ACRA AM0 A A - - H" AC-1>AC" ' EMU_AC-1>AC ' NOP SIMPLE-OP: AC-1>AC
2 3 >ACRA AM0 A A - - H" AC+1>AC" ' EMU_AC+1>AC ' NOP SIMPLE-OP: AC+1>AC
2 4 >ACRA AM0 AC A - - H" AC+CRY>AC" ' EMU_AC+CRY>AC ' NOP SIMPLE-OP: AC+CRY>AC
2 5 >ACRA AM0 AC A - - H" AC+CRY>AC" ' EMU_AC+CRY>AC ' NOP SIMPLE-OP: AC+CRY>AC
2 7 >ACRA AM0 tT A - - H" TR+1>AC" ' EMU_TR+1>AC ' NOP SIMPLE-OP: TR+1>AC
3 1 >ACRA AM0 - A - - H" 0>AC" ' EMU_0>AC ' NOP SIMPLE-OP: 0>AC
3 2 >ACRA AM0 tT A - - H" TR>AC" ' EMU_TR>AC ' NOP SIMPLE-OP: TR>AC
3 3 >ACRA AM0 D A - - H" DR>AC" ' EMU_DR>AC ' NOP SIMPLE-OP: DR>AC
1 >AC AM1 C A - - H" CRY>AC" ' EMU_CRY>AC ' NOP SIMPLE-OP: CRY>AC
2 >AC AM1 tT A - - H" TR>ACx" ' EMU_TR>AC ' NOP SIMPLE-OP: TR>ACx
3 >AC AM1 D A - - H" DR>ACx" ' EMU_DR>AC ' NOP SIMPLE-OP: DR>ACx
1 >AC AM2 c8 A - - H" C8>AC" ' EMU_C8>AC ' NOP SIMPLE-OP: C8>AC
2 1 >ACRA AM2 AD A - - H" AC_XOR_DR>AC" ' EMU_AC_XOR_DR>AC ' NOP SIMPLE-OP: AC_XOR_DR>AC
2 2 >ACRA AM2 tT A - - H" TR+1>ACx" ' EMU_TR+1>AC ' NOP SIMPLE-OP: TR+1>ACx
2 4 >ACRA AM2 AtT AC - - H" AC-TR>ACC" ' EMU_AC-TR>ACC ' NOP SIMPLE-OP: AC-TR>ACC
2 5 >ACRA AM2 AtT AC - - H" AC+TR>ACC" ' EMU_AC+TR>ACC ' NOP SIMPLE-OP: AC+TR>ACC
2 6 >ACRA AM2 AtT A - - H" AC-TR>AC" ' EMU_AC-TR>AC ' NOP SIMPLE-OP: AC-TR>AC
2 7 >ACRA AM2 AtT A - - H" AC+TR>AC" ' EMU_AC+TR>AC ' NOP SIMPLE-OP: AC+TR>AC
1 0 >ACPT AM3 A A - - H" AC_SL" ' EMU_AC_SL ' NOP SIMPLE-OP: AC_SL
\ code type src dst Dsrc Ddst instr string emultion emulation operation
2 0 >ACPT AM3 AC AC - - H" AC_RLC" ' EMU_AC_RLC ' NOP SIMPLE-OP: AC_RLC
1 1 >ACPT AM3 A A - - H" AC_RL" ' EMU_AC_RL ' NOP SIMPLE-OP: AC_RL
2 1 >ACPT AM3 At A - - H" AC_RL_TR" ' EMU_AC_RL_TR ' NOP SIMPLE-OP: AC_RL_TR
3 1 >ACPT AM3 AD A - - H" AC_RL_DR" ' EMU_AC_RL_DR ' NOP SIMPLE-OP: AC_RL_DR
1 2 >ACPT AM3 A A - - H" AC_SR" ' EMU_AC_SR ' NOP SIMPLE-OP: AC_SR
2 2 >ACPT AM3 AC AC - - H" AC_RRC" ' EMU_AC_RRC ' NOP SIMPLE-OP: AC_RRC
1 3 >ACPT AM3 A A - - H" AC_RR" ' EMU_AC_RR ' NOP SIMPLE-OP: AC_RR
2 3 >ACPT AM3 AT A - - H" AC_RR_TR" ' EMU_AC_RR_TR ' NOP SIMPLE-OP: AC_RR_TR
3 3 >ACPT AM3 AD A - - H" AC_RR_DR" ' EMU_AC_RR_DR ' NOP SIMPLE-OP: AC_RR_DR
1 4 >ACPT AM3 A A - - H" AC_SRB" ' EMU_AC_SRB ' NOP SIMPLE-OP: AC_SRB
2 4 >ACPT AM3 A A - - H" AC_RRB" ' EMU_AC_RRB ' NOP SIMPLE-OP: AC_RRB
3 4 >ACPT AM3 AD A - - H" AC_RRB_AC" ' EMU_AC_RRB_AC ' NOP SIMPLE-OP: AC_RRB_AC
1 5 >ACPT AM3 At A - - H" AC_RRB_TR" ' EMU_AC_RRB_TR ' NOP SIMPLE-OP: AC_RRB_TR
2 5 >ACPT AM3 AD A - - H" AC_RRB_DR" ' EMU_AC_RRB_DR ' NOP SIMPLE-OP: AC_RRB_DR
1 6 >ACPT AM3 AtT A - - H" MPY>AC" ' EMU_MPY>AC ' NOP SIMPLE-OP: MPY>AC
2 6 >ACPT AM3 AtTDC A - - H" DIV>AC" ' EMU_DIV>AC ' NOP SIMPLE-OP: DIV>AC
7 5 2 >MAPTR - - - - H" RP-4>MAu" ' EMU_RP-4>MAu ' NOP SIMPLE-OP: RP-4>MAu
5 4 0 >MAPTR - - - - H" TR>MAu" ' EMU_TR>MAu ' NOP SIMPLE-OP: TR>MAu
6 5 2 >MAPTR - - - - H" RP+4>MAu" ' EMU_RP+4>MAu ' NOP SIMPLE-OP: RP+4>MAu
\ code type src dst Dsrc Ddst instr string emultion emulation operation
5 4 1 >MAPTR - - - - H" TR+2>MAu" ' EMU_TR+2>MAu ' NOP SIMPLE-OP: TR+2>MAu
6 4 1 >MAPTR - - - - H" IP+2>MAu" ' EMU_IP+2>MAu ' NOP SIMPLE-OP: IP+2>MAu
1 6 1 >MAPTR - - - - H" MA+2>MAu" ' EMU_MA+2>MAu ' NOP SIMPLE-OP: MA+2>MAu
6 6 2 >MAPTR - - - - H" SP+4>MAu" ' EMU_SP+4>MAu ' NOP SIMPLE-OP: SP+4>MAu
6 6 4 >MAPTR - - - - H" SP+8>MAu" ' EMU_SP+8>MAu ' NOP SIMPLE-OP: SP+8>MAu
7 5 4 >MAPTR - - - - H" RP-8>MAu" ' EMU_RP-8>MAu ' NOP SIMPLE-OP: RP-8>MAu
7 6 2 >MAPTR - - - - H" SP-4>MAu" ' EMU_SP-4>MAu ' NOP SIMPLE-OP: SP-4>MAu
7 2 2 >MAPTR - - - - H" SP-4>MA" ' EMU_SP-4>MA ' NOP SIMPLE-OP: SP-4>MA
6 1 2 >MAPTR - - - - H" RP+4>MA" ' EMU_RP+4>MA ' NOP SIMPLE-OP: RP+4>MA
6 5 4 >MAPTR - - - - H" RP+8>MAu" ' EMU_RP+8>MAu ' NOP SIMPLE-OP: RP+8>MAu
\ comment - - - - H" (SOS>TR)" ' EMU_(SOS>TR) ' NOP SIMPLE-OP: (SOS>TR)
\ comment - - - - H" (PUSH}" ' EMU_(PUSH} ' NOP SIMPLE-OP: (PUSH}
\ comment - - - - H" (POP)" ' EMU_(POP) ' NOP SIMPLE-OP: (POP)
\ comment - - - - H" (RP@>TR)" ' EMU_(RP@>TR) ' NOP SIMPLE-OP: (RP@>TR)
0 >XB - - - - H" AMD0_d" ' EMU_AMD0 ' EMU_dfr SIMPLE-OP: AMD0_d
1 >XB - - - - H" AMD1_d" ' EMU_AMD1 ' EMU_dfr SIMPLE-OP: AMD1_d
2 >XB - - - - H" AMD2_d" ' EMU_AMD2 ' EMU_dfr SIMPLE-OP: AMD2_d
3 >XB - - - - H" AMD3_d" ' EMU_AMD3 ' EMU_dfr SIMPLE-OP: AMD3_d
Done

On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
> \ Op Code File for MFX. Generated by MAKE-OPS v13
>
> \ MODELS\RACE32\RACE32.ops
>
> \ src dst codes J I H G F E D C B A 9 8 7 6 5 4 3 2 1 0
> \ `--.--' `-.-' | | | | | | | | | | |
> \ errors -------------' | | | | | | | | | | | |
> \ constants -----------------' | | | | | | | | | | | - c8_6_5_3
> \ stack ptr mem ---------------------' | | | | | | | | | | - S PM
> \ loop ctr ----------------------------' | | | | | | | | | - L LC
> \ return reg ----------------------------' | | | | | | | | - R RR
> \ prog ctr --------------------------------' | | | | | | | - P PC
> \ mem ads -----------------------------------' | | | | | | - F FLG
> \ flag ----------------------------------------' | | | | | - M MA
> \ carry -----------------------------------------' | | | | - C CRY
> \ data reg ----------------------------------------' | | | - D DR
> \ Treg high (sos) -----------------------------------' | | - T TH
> \ Treg low (sos) --------------------------------------' | - t TL
> \ accumulator (tos) -------------------------------------' - A AC
>
> \ Deferred cmds:
> \ Dsrc Ddst codes J I H G F E D C B A 9 8 7 6 5 4 3 2 1 0
> \ `--.--' `-.-' | | | | | | |
> \ errors -------------' | | | | | | | |
> \ constants -----------------' | | | | | | |
> \ i/o -------------------------------------' | | | | | |
> \ static mem --------------------------------' | | | | |
> \ dynamic mem ---------------------------------' | | | |
> \ reg mem ---------------------------------------' | | |
> \ Treg high (sos) -----------------------------------' | |
> \ Treg low (sos) --------------------------------------' |
> \ accumulator (tos) -------------------------------------'
>
> \ now deferred now deferred
> \ code type src dst Dsrc Ddst instr string emultion emulation operation
> 0 1 >XBCS tT D - - H" TR>DR" ' EMU_TR>DR ' NOP SIMPLE-OP: TR>DR
> 1 1 >XBCS D tT - - H" DR>TR" ' EMU_DR>TR ' NOP SIMPLE-OP: DR>TR
> 2 1 >XBCS A D - - H" AC>DR" ' EMU_AC>DR ' NOP SIMPLE-OP: AC>DR
> 3 1 >XBCS A F - - H" TR15>FLG" ' EMU_TR15>FLG ' NOP SIMPLE-OP: TR15>FLG
> 1 2 >XBCS - tT - - H" -1>TRL" ' EMU_-1>TRL ' NOP SIMPLE-OP: -1>TRL
> 2 2 >XBCS - tT - - H" -1>TRH" ' EMU_-1>TRH ' NOP SIMPLE-OP: -1>TRH
> 3 2 >XBCS - tT - - H" -1>TR" ' EMU_-1>TR ' NOP SIMPLE-OP: -1>TR
> 0 3 >XBCS - D - - H" 0>DR" ' EMU_0>DR ' NOP SIMPLE-OP: 0>DR
> 1 3 >XBCS - tT - - H" 0>TRL" ' EMU_0>TRL ' NOP SIMPLE-OP: 0>TRL
> 2 3 >XBCS - tT - - H" 0>TRH" ' EMU_0>TRH ' NOP SIMPLE-OP: 0>TRH
> 3 3 >XBCS - tT - - H" 0>TR" ' EMU_0>TR ' NOP SIMPLE-OP: 0>TR
> 0 4 >XBCS A D - - H" AC>DR" ' EMU_AC>DR ' NOP SIMPLE-OP: AC>DR
> 1 4 >XBCS A tT - - H" AC>TR" ' EMU_AC>TR ' NOP SIMPLE-OP: AC>TR
> 2 4 >XBCS AtT D - - H" AC_OR_TR>DR" ' EMU_AC_OR_TR>DR ' NOP SIMPLE-OP: AC_OR_TR>DR
> 3 4 >XBCS AD tT - - H" AC_AND_DR>TR" ' EMU_AC_AND_DR>TR ' NOP SIMPLE-OP: AC_AND_DR>TR
> 0 5 >XBCS - C - - H" 0>CRY" ' EMU_0>CRY ' NOP SIMPLE-OP: 0>CRY
> 1 5 >XBCS - C - - H" 1>CRY" ' EMU_1>CRY ' NOP SIMPLE-OP: 1>CRY
> 2 5 >XBCS C CF - - H" 0>CRY>FLG" ' EMU_0>CRY>FLG ' NOP SIMPLE-OP: 0>CRY>FLG
> 3 5 >XBCS CF CF - - H" CRY><FLG" ' EMU_CRY><FLG ' NOP SIMPLE-OP: CRY><FLG
> \ code type src dst Dsrc Ddst instr string emultion emulation operation
> 0 6 >XBCS c6 L - - H" C6>REP" ' EMU_C6>REP ' NOP SIMPLE-OP: C6>REP
> 1 6 >XBCS Ac6 DL - - H" C6>REP~AC>DR" ' EMU_C6>REP~AC>DR ' NOP SIMPLE-OP: C6>REP~AC>DR
> 2 6 >XBCS tTc6 DL - - H" C6>REP~TR>DR" ' EMU_C6>REP~TR>DR ' NOP SIMPLE-OP: C6>REP~TR>DR
> 3 6 >XBCS tTDc6 tTDL - - H" C6>REP~TR><DR" ' EMU_C6>REP~TR><DR ' NOP SIMPLE-OP: C6>REP~TR><DR
> 0 7 >XBCS AtTc6 DL - - H" C6&AC>REP~0>DR" ' EMU_C6&AC>REP~0>DR ' NOP SIMPLE-OP: C6&AC>REP~0>DR
> 1 7 >XBCS AtTc6 DL - - H" C6&/AC>REP~0>DR" ' EMU_C6&/AC>REP~0>D ' NOP SIMPLE-OP: C6&/AC>REP~0>DR
> 2 7 >XBCS c6 L - - H" C6>LOOP" ' EMU_C6>LOOP ' NOP SIMPLE-OP: C6>LOOP
> 8 >CS - - A r H" AC>*MA_d" ' EMU_AC>*MA ' EMU_WE4 SIMPLE-OP: AC>*MA_d
> 9 >CS A tT - - H" AC>TRx" ' EMU_AC>TR ' NOP SIMPLE-OP: AC>TRx
> 1 A >XBCS - - A rds H" AC>*MA_BYT_d" ' EMU_AC>*MA_BYT ' EMU_WE1 SIMPLE-OP: AC>*MA_BYT_d
> 2 A >XBCS - - A rdso H" ACLW>*MA_d" ' EMU_ACLW>*MA ' EMU_WE2 SIMPLE-OP: ACLW>*MA_d
> 3 A >XBCS - - A rdso H" ACHW>*MA_d" ' EMU_ACHW>*MA ' EMU_WE3 SIMPLE-OP: ACHW>*MA_d
> 1 B >XBCS A tT A r H" AC>TR~AC>*MA_d" ' EMU_AC>TR ' EMU_WE4 SIMPLE-OP: AC>TR~AC>*MA_d
> 2 B >XBCS A D A r H" AC>DR~AC>*MA_d" ' EMU_AC>DR ' EMU_WE4 SIMPLE-OP: AC>DR~AC>*MA_d
> 3 B >XBCS - - A - H" AC>TR(CS)_d" ' EMU_AC>TR(CS) ' EMU_WE7 SIMPLE-OP: AC>TR(CS)_d
> 1 C >XBCS - tT ro tT H" *MA>TRL_d" ' EMU_*MA>TRL ' EMU_RE1 SIMPLE-OP: *MA>TRL_d
> 2 C >XBCS - tT rds tT H" *MA>TRH_d" ' EMU_*MA>TRH ' EMU_RE2 SIMPLE-OP: *MA>TRH_d
> 3 C >XBCS - tT r tT H" *MA>TR_d" ' EMU_*MA>TR ' EMU_RE3 SIMPLE-OP: *MA>TR_d
> 1 D >XBCS A tTD r tT H" AC>DR~*MA>TR_d" ' EMU_AC>DR ' EMU_RE3 SIMPLE-OP: AC>DR~*MA>TR_d
> \ code type src dst Dsrc Ddst instr string emultion emulation operation
> 2 D >XBCS tT tTD r tT H" TR>DR~*MA>TR_d" ' EMU_TR>DR ' EMU_RE3 SIMPLE-OP: TR>DR~*MA>TR_d
> F >CS - tT ro tT H" *MA>NXT_d" ' EMU_*MA>NXT ' EMU_RE4 SIMPLE-OP: *MA>NXT_d
> 0 10 >XBCS CPc6 P - - H" IF_CRY+JMP" ' EMU_IF_CRY+JMP ' NOP COUNT-OP: IF_CRY+JMP
> 1 10 >XBCS CPc6 P - - H" IF/CRY+JMP" ' EMU_IF/CRY+JMP ' NOP COUNT-OP: IF/CRY+JMP
> 2 10 >XBCS FPc6 P - - H" IF_FLG+JMP" ' EMU_IF_FLG+JMP ' NOP COUNT-OP: IF_FLG+JMP
> 3 10 >XBCS FPc6 P - - H" IF/FLG+JMP" ' EMU_IF/FLG+JMP ' NOP COUNT-OP: IF/FLG+JMP
> 0 11 >XBCS APc6 P - - H" IF_AC0+JMP" ' EMU_IF_AC0+JMP ' NOP COUNT-OP: IF_AC0+JMP
> 1 11 >XBCS APc6 P - - H" IF/AC0+JMP" ' EMU_IF/AC0+JMP ' NOP COUNT-OP: IF/AC0+JMP
> 2 11 >XBCS APc6 P - - H" IF_AC31+JMP" ' EMU_IF_AC31+JMP ' NOP COUNT-OP: IF_AC31+JMP
> 3 11 >XBCS APc6 P - - H" IF/AC31+JMP" ' EMU_IF/AC31+JMP ' NOP COUNT-OP: IF/AC31+JMP
> 0 12 >XBCS CPc6 P - - H" IF_CRY-JMP" ' EMU_IF_CRY-JMP ' NOP COUNT-OP: IF_CRY-JMP
> 1 12 >XBCS CPc6 P - - H" IF/CRY-JMP" ' EMU_IF/CRY-JMP ' NOP COUNT-OP: IF/CRY-JMP
> 2 12 >XBCS FPc6 P - - H" IF_FLG-JMP" ' EMU_IF_FLG-JMP ' NOP COUNT-OP: IF_FLG-JMP
> 3 12 >XBCS FPc6 P - - H" IF/FLG-JMP" ' EMU_IF/FLG-JMP ' NOP COUNT-OP: IF/FLG-JMP
> 0 13 >XBCS APc6 P - - H" IF_AC0-JMP" ' EMU_IF_AC0-JMP ' NOP COUNT-OP: IF_AC0-JMP
> 1 13 >XBCS APc6 P - - H" IF/AC0-JMP" ' EMU_IF/AC0-JMP ' NOP COUNT-OP: IF/AC0-JMP
> 2 13 >XBCS APc6 P - - H" IF_AC31-JMP" ' EMU_IF_AC31-JMP ' NOP COUNT-OP: IF_AC31-JMP
> 3 13 >XBCS APc6 P - - H" IF/AC31-JMP" ' EMU_IF/AC31-JMP ' NOP COUNT-OP: IF/AC31-JMP
> 0 14 >XBCS Pc8 P - - H" +JMP" ' EMU_+JMP ' NOP COUNT-OP: +JMP
> \ code type src dst Dsrc Ddst instr string emultion emulation operation
> 1 14 >XBCS APc6 P - - H" IF/AC1+JMP" ' EMU_IF/AC1+JMP ' NOP COUNT-OP: IF/AC1+JMP
> 2 14 >XBCS APc6 P - - H" IF/AC2+JMP" ' EMU_IF/AC2+JMP ' NOP COUNT-OP: IF/AC2+JMP
> 3 14 >XBCS APc6 P - - H" IF/AC3+JMP" ' EMU_IF/AC3+JMP ' NOP COUNT-OP: IF/AC3+JMP
> 0 15 >XBCS APc6 P - - H" IF/AC4+JMP" ' EMU_IF/AC4+JMP ' NOP COUNT-OP: IF/AC4+JMP
> 1 15 >XBCS APc6 P - - H" IF/AC5+JMP" ' EMU_IF/AC5+JMP ' NOP COUNT-OP: IF/AC5+JMP
> 2 15 >XBCS APc6 P - - H" IF/AC6+JMP" ' EMU_IF/AC6+JMP ' NOP COUNT-OP: IF/AC6+JMP
> 3 15 >XBCS APc6 P - - H" IF/AC7+JMP" ' EMU_IF/AC7+JMP ' NOP COUNT-OP: IF/AC7+JMP
> 0 16 >XBCS Pc8 P - - H" -JMP" ' EMU_-JMP ' NOP COUNT-OP: -JMP
> 1 16 >XBCS PLc6 P - - H" IF_REP-JMP" ' EMU_IF_REP-JMP ' NOP COUNT-OP: IF_REP-JMP
> 2 16 >XBCS c8 P - - H" JMP&LINK" ' EMU_JMP&LINK ' NOP COUNT-OP: JMP&LINK
> 3 16 >XBCS R P - - H" RET_LINK" ' EMU_RET_LINK ' NOP COUNT-OP: RET_LINK
> 0 17 >XBCS t tT - - H" TR_RL" ' EMU_TR_RL ' NOP SIMPLE-OP: TR_RL
> 1 17 >XBCS At tT - - H" TR_RL_DR" ' EMU_TR_RL_DR ' NOP SIMPLE-OP: TR_RL_DR
> 2 17 >XBCS tD tT - - H" TR_RL_AC" ' EMU_TR_RL_AC ' NOP SIMPLE-OP: TR_RL_AC
> 3 17 >XBCS tTC tTC - - H" TR_RLC" ' EMU_TR_RLC ' NOP SIMPLE-OP: TR_RLC
> 0 18 >XBCS tT tT - - H" TR_RR" ' EMU_TR_RR ' NOP SIMPLE-OP: TR_RR
> 1 18 >XBCS tT tT - - H" TR_RR_DR" ' EMU_TR_RR_DR ' NOP SIMPLE-OP: TR_RR_DR
> 2 18 >XBCS tT tT - - H" TR_RR_AC" ' EMU_TR_RR_AC ' NOP SIMPLE-OP: TR_RR_AC
> 3 18 >XBCS tT tTC - - H" TR_RRC" ' EMU_TR_RRC ' NOP SIMPLE-OP: TR_RRC
> \ code type src dst Dsrc Ddst instr string emultion emulation operation
> 0 19 >XBCS tT tT - - H" TR_RRB" ' EMU_TR_RRB ' NOP SIMPLE-OP: TR_RRB
> 1 19 >XBCS tT tT - - H" TR_RRB_DR" ' EMU_TR_RRB_DR ' NOP SIMPLE-OP: TR_RRB_DR
> 2 19 >XBCS tT tT - - H" TR_RRB_AC" ' EMU_TR_RRB_AC ' NOP SIMPLE-OP: TR_RRB_AC
> 3 19 >XBCS tT tT - - H" TR_SRB" ' EMU_TR_SRB ' NOP SIMPLE-OP: TR_SRB
> 0 1A >XBCS D D - - H" DR_RL" ' EMU_DR_RL ' NOP SIMPLE-OP: DR_RL
> 1 1A >XBCS D D - - H" DR_RL" ' EMU_DR_RL ' NOP SIMPLE-OP: DR_RL
> 2 1A >XBCS tD D - - H" DR_RL-TR" ' EMU_DR_RL_TR ' NOP SIMPLE-OP: DR_RL-TR
> 3 1A >XBCS DC DC - - H" DR_RLC" ' EMU_DR_RLC ' NOP SIMPLE-OP: DR_RLC
> 0 1B >XBCS D D - - H" DR_RR" ' EMU_DR_RR ' NOP SIMPLE-OP: DR_RR
> 1 1B >XBCS AD D - - H" DR_RR_AC" ' EMU_DR_RR_AC ' NOP SIMPLE-OP: DR_RR_AC
> 2 1B >XBCS TD D - - H" DR_RR_TR" ' EMU_DR_RR_TR ' NOP SIMPLE-OP: DR_RR_TR
> 3 1B >XBCS DC DC - - H" DR_RRC" ' EMU_DR_RRC ' NOP SIMPLE-OP: DR_RRC
> 0 1C >XBCS D D - - H" DR_RRB" ' EMU_DR_RRB ' NOP SIMPLE-OP: DR_RRB
> 1 1C >XBCS AD D - - H" DR_RRB_AC" ' EMU_DR_RRB_AC ' NOP SIMPLE-OP: DR_RRB_AC
> 2 1C >XBCS tD D - - H" DR_RRB_TR" ' EMU_DR_RRB_TR ' NOP SIMPLE-OP: DR_RRB_TR
> 3 1C >XBCS D D - - H" DR_SRB" ' EMU_DR_SRB ' NOP SIMPLE-OP: DR_SRB
> 2 1D >XBCS tD tTD - - H" TR_DR_RL_AC" ' EMU_TR_DR_RL_AC ' NOP SIMPLE-OP: TR_DR_RL_AC
> 0 1E >XBCS tTD tTD - - H" TR_DR_RR" ' EMU_TR_DR_RR ' NOP SIMPLE-OP: TR_DR_RR
> 2 1E >XBCS AtTD tTD - - H" TR_DR_RR_AC" ' EMU_TR_DR_RR_AC ' NOP SIMPLE-OP: TR_DR_RR_AC
> \ code type src dst Dsrc Ddst instr string emultion emulation operation
> 2 1F >XBCS tTD tTD - - H" TR_DR_RRB_AC" ' EMU_TR_DR_RRB_AC ' NOP SIMPLE-OP: TR_DR_RRB_AC
> 0 >MA - M - - H" hold" ' EMU_MA>MA ' NOP JMPL-OP: hold
> 1 0 >MAPT A M - - H" IP>MA" ' EMU_PM>MA ' NOP JMPL-OP: IP>MA
> 1 1 >MAPT A M - - H" RP>MA" ' EMU_PM>MA ' NOP JMPL-OP: RP>MA
> 1 2 >MAPT A M - - H" SP>MA" ' EMU_PM>MA ' NOP JMPL-OP: SP>MA
> 1 3 >MAPT A M - - H" DP>MA" ' EMU_PM>MA ' NOP JMPL-OP: DP>MA
> 1 4 >MAPT Sc5 M - - H" MA+C>MA" ' EMU_MA+C>MA ' NOP JMPL-OP: MA+C>MA
> 1 5 >MAPT Sc5 M - - H" MA-C>MA" ' EMU_MA-C>MA ' NOP JMPL-OP: MA-C>MA
> 1 6 >MAPT Sc5 M - - H" MA+C>MAu" ' EMU_MA+C>MA ' NOP JMPL-OP: MA+C>MAu
> 1 7 >MAPT Sc5 M - - H" MA-C>MAu" ' EMU_MA-C>MA ' NOP JMPL-OP: MA-C>MAu
> 2 >MA M M - - H" AC>MA" ' EMU_AC>MA ' NOP JMPL-OP: AC>MA
> 3 >MA tTS M - - H" MA-TR>MAu" ' EMU_MA-TR>MA ' NOP JMPL-OP: MA-TR>MAu
> 4 >MA Mc6 M - - H" AC+C8>MA" ' EMU_AC+C8>MA ' NOP JMPL-OP: AC+C8>MA
> 5 0 >MAPT A M - - H" IP+2>MAu" ' EMU_PM+2>MA ' NOP JMPL-OP: IP+2>MAu
> 5 1 >MAPT tT M - - H" TR>MAu" ' EMU_TR>MA ' NOP JMPL-OP: TR>MAu
> 5 2 >MAPT tT M - - H" TR+2>MAu" ' EMU_TR+2>MA ' NOP JMPL-OP: TR+2>MAu
> 5 5 >MAPT tT M - - H" TR>MA" ' EMU_TR>MA ' NOP JMPL-OP: TR>MA
> 5 6 >MAPT tT M - - H" TR+2>MA" ' EMU_TR+2>MA ' NOP JMPL-OP: TR+2>MA
> 5 7 >MAPT S M - - H" MA+4>MA" ' EMU_MA+4>MA ' NOP JMPL-OP: MA+4>MA
> \ code type src dst Dsrc Ddst instr string emultion emulation operation
> 6 0 >MAPT Ac5 M - - H" IP+C>MA" ' EMU_PM+C>MA ' NOP JMPL-OP: IP+C>MA
> 6 1 >MAPT Ac5 M - - H" RP+C>MA" ' EMU_PM+C>MA ' NOP JMPL-OP: RP+C>MA
> 6 2 >MAPT Ac5 M - - H" SP+C>MA" ' EMU_PM+C>MA ' NOP JMPL-OP: SP+C>MA
> 6 3 >MAPT Ac3 M - - H" DP+C5>MA" ' EMU_PM+C5>MA ' NOP JMPL-OP: DP+C5>MA
> 6 4 >MAPT Ac5 M - - H" IP+C>MAu" ' EMU_PM+C>MA ' NOP JMPL-OP: IP+C>MAu
> 6 5 >MAPT Ac5 M - - H" RP+C>MAu" ' EMU_PM+C>MA ' NOP JMPL-OP: RP+C>MAu
> 6 6 >MAPT Ac5 M - - H" SP+C>MAu" ' EMU_PM+C>MA ' NOP JMPL-OP: SP+C>MAu
> 6 7 >MAPT Ac3 M - - H" DP+C5>MAu" ' EMU_PM+C5>MA ' NOP JMPL-OP: DP+C5>MAu
> 7 0 >MAPT Ac5 M - - H" IP-C>MA" ' EMU_PM-C>MA ' NOP JMPL-OP: IP-C>MA
> 7 1 >MAPT Ac5 M - - H" RP-C>MA" ' EMU_PM-C>MA ' NOP JMPL-OP: RP-C>MA
> 7 2 >MAPT Ac5 M - - H" SP-C>MA" ' EMU_PM-C>MA ' NOP JMPL-OP: SP-C>MA
> 7 3 >MAPT Ac3 M - - H" DP-C5>MA" ' EMU_PM-C5>MA ' NOP JMPL-OP: DP-C5>MA
> 7 4 >MAPT Ac5 M - - H" IP-C>MAu" ' EMU_PM-C>MA ' NOP JMPL-OP: IP-C>MAu
> 7 5 >MAPT Ac5 M - - H" RP-C>MAu" ' EMU_PM-C>MA ' NOP JMPL-OP: RP-C>MAu
> 7 6 >MAPT Ac5 M - - H" SP-C>MAu" ' EMU_PM-C>MA ' NOP JMPL-OP: SP-C>MAu
> 7 7 >MAPT Ac3 M - - H" DP-C5>MAu" ' EMU_PM-C5>MA ' NOP JMPL-OP: DP-C5>MAu
> 1 >AC AM0 FM A - - H" MA>AC" ' EMU_MA>AC ' NOP SIMPLE-OP: MA>AC
> 2 0 >ACRA AM0 A AC - - H" AC-1>ACC" ' EMU_AC-1>ACC ' NOP SIMPLE-OP: AC-1>ACC
> 2 1 >ACRA AM0 A AC - - H" AC+1>ACC" ' EMU_AC+1>ACC ' NOP SIMPLE-OP: AC+1>ACC
> \ code type src dst Dsrc Ddst instr string emultion emulation operation
> 2 2 >ACRA AM0 A A - - H" AC-1>AC" ' EMU_AC-1>AC ' NOP SIMPLE-OP: AC-1>AC
> 2 3 >ACRA AM0 A A - - H" AC+1>AC" ' EMU_AC+1>AC ' NOP SIMPLE-OP: AC+1>AC
> 2 4 >ACRA AM0 AC A - - H" AC+CRY>AC" ' EMU_AC+CRY>AC ' NOP SIMPLE-OP: AC+CRY>AC
> 2 5 >ACRA AM0 AC A - - H" AC+CRY>AC" ' EMU_AC+CRY>AC ' NOP SIMPLE-OP: AC+CRY>AC
> 2 7 >ACRA AM0 tT A - - H" TR+1>AC" ' EMU_TR+1>AC ' NOP SIMPLE-OP: TR+1>AC
> 3 1 >ACRA AM0 - A - - H" 0>AC" ' EMU_0>AC ' NOP SIMPLE-OP: 0>AC
> 3 2 >ACRA AM0 tT A - - H" TR>AC" ' EMU_TR>AC ' NOP SIMPLE-OP: TR>AC
> 3 3 >ACRA AM0 D A - - H" DR>AC" ' EMU_DR>AC ' NOP SIMPLE-OP: DR>AC
> 1 >AC AM1 C A - - H" CRY>AC" ' EMU_CRY>AC ' NOP SIMPLE-OP: CRY>AC
> 2 >AC AM1 tT A - - H" TR>ACx" ' EMU_TR>AC ' NOP SIMPLE-OP: TR>ACx
> 3 >AC AM1 D A - - H" DR>ACx" ' EMU_DR>AC ' NOP SIMPLE-OP: DR>ACx
> 1 >AC AM2 c8 A - - H" C8>AC" ' EMU_C8>AC ' NOP SIMPLE-OP: C8>AC
> 2 1 >ACRA AM2 AD A - - H" AC_XOR_DR>AC" ' EMU_AC_XOR_DR>AC ' NOP SIMPLE-OP: AC_XOR_DR>AC
> 2 2 >ACRA AM2 tT A - - H" TR+1>ACx" ' EMU_TR+1>AC ' NOP SIMPLE-OP: TR+1>ACx
> 2 4 >ACRA AM2 AtT AC - - H" AC-TR>ACC" ' EMU_AC-TR>ACC ' NOP SIMPLE-OP: AC-TR>ACC
> 2 5 >ACRA AM2 AtT AC - - H" AC+TR>ACC" ' EMU_AC+TR>ACC ' NOP SIMPLE-OP: AC+TR>ACC
> 2 6 >ACRA AM2 AtT A - - H" AC-TR>AC" ' EMU_AC-TR>AC ' NOP SIMPLE-OP: AC-TR>AC
> 2 7 >ACRA AM2 AtT A - - H" AC+TR>AC" ' EMU_AC+TR>AC ' NOP SIMPLE-OP: AC+TR>AC
> 1 0 >ACPT AM3 A A - - H" AC_SL" ' EMU_AC_SL ' NOP SIMPLE-OP: AC_SL
> \ code type src dst Dsrc Ddst instr string emultion emulation operation
> 2 0 >ACPT AM3 AC AC - - H" AC_RLC" ' EMU_AC_RLC ' NOP SIMPLE-OP: AC_RLC
> 1 1 >ACPT AM3 A A - - H" AC_RL" ' EMU_AC_RL ' NOP SIMPLE-OP: AC_RL
> 2 1 >ACPT AM3 At A - - H" AC_RL_TR" ' EMU_AC_RL_TR ' NOP SIMPLE-OP: AC_RL_TR
> 3 1 >ACPT AM3 AD A - - H" AC_RL_DR" ' EMU_AC_RL_DR ' NOP SIMPLE-OP: AC_RL_DR
> 1 2 >ACPT AM3 A A - - H" AC_SR" ' EMU_AC_SR ' NOP SIMPLE-OP: AC_SR
> 2 2 >ACPT AM3 AC AC - - H" AC_RRC" ' EMU_AC_RRC ' NOP SIMPLE-OP: AC_RRC
> 1 3 >ACPT AM3 A A - - H" AC_RR" ' EMU_AC_RR ' NOP SIMPLE-OP: AC_RR
> 2 3 >ACPT AM3 AT A - - H" AC_RR_TR" ' EMU_AC_RR_TR ' NOP SIMPLE-OP: AC_RR_TR
> 3 3 >ACPT AM3 AD A - - H" AC_RR_DR" ' EMU_AC_RR_DR ' NOP SIMPLE-OP: AC_RR_DR
> 1 4 >ACPT AM3 A A - - H" AC_SRB" ' EMU_AC_SRB ' NOP SIMPLE-OP: AC_SRB
> 2 4 >ACPT AM3 A A - - H" AC_RRB" ' EMU_AC_RRB ' NOP SIMPLE-OP: AC_RRB
> 3 4 >ACPT AM3 AD A - - H" AC_RRB_AC" ' EMU_AC_RRB_AC ' NOP SIMPLE-OP: AC_RRB_AC
> 1 5 >ACPT AM3 At A - - H" AC_RRB_TR" ' EMU_AC_RRB_TR ' NOP SIMPLE-OP: AC_RRB_TR
> 2 5 >ACPT AM3 AD A - - H" AC_RRB_DR" ' EMU_AC_RRB_DR ' NOP SIMPLE-OP: AC_RRB_DR
> 1 6 >ACPT AM3 AtT A - - H" MPY>AC" ' EMU_MPY>AC ' NOP SIMPLE-OP: MPY>AC
> 2 6 >ACPT AM3 AtTDC A - - H" DIV>AC" ' EMU_DIV>AC ' NOP SIMPLE-OP: DIV>AC
> 7 5 2 >MAPTR - - - - H" RP-4>MAu" ' EMU_RP-4>MAu ' NOP SIMPLE-OP: RP-4>MAu
> 5 4 0 >MAPTR - - - - H" TR>MAu" ' EMU_TR>MAu ' NOP SIMPLE-OP: TR>MAu
> 6 5 2 >MAPTR - - - - H" RP+4>MAu" ' EMU_RP+4>MAu ' NOP SIMPLE-OP: RP+4>MAu
> \ code type src dst Dsrc Ddst instr string emultion emulation operation
> 5 4 1 >MAPTR - - - - H" TR+2>MAu" ' EMU_TR+2>MAu ' NOP SIMPLE-OP: TR+2>MAu
> 6 4 1 >MAPTR - - - - H" IP+2>MAu" ' EMU_IP+2>MAu ' NOP SIMPLE-OP: IP+2>MAu
> 1 6 1 >MAPTR - - - - H" MA+2>MAu" ' EMU_MA+2>MAu ' NOP SIMPLE-OP: MA+2>MAu
> 6 6 2 >MAPTR - - - - H" SP+4>MAu" ' EMU_SP+4>MAu ' NOP SIMPLE-OP: SP+4>MAu
> 6 6 4 >MAPTR - - - - H" SP+8>MAu" ' EMU_SP+8>MAu ' NOP SIMPLE-OP: SP+8>MAu
> 7 5 4 >MAPTR - - - - H" RP-8>MAu" ' EMU_RP-8>MAu ' NOP SIMPLE-OP: RP-8>MAu
> 7 6 2 >MAPTR - - - - H" SP-4>MAu" ' EMU_SP-4>MAu ' NOP SIMPLE-OP: SP-4>MAu
> 7 2 2 >MAPTR - - - - H" SP-4>MA" ' EMU_SP-4>MA ' NOP SIMPLE-OP: SP-4>MA
> 6 1 2 >MAPTR - - - - H" RP+4>MA" ' EMU_RP+4>MA ' NOP SIMPLE-OP: RP+4>MA
> 6 5 4 >MAPTR - - - - H" RP+8>MAu" ' EMU_RP+8>MAu ' NOP SIMPLE-OP: RP+8>MAu
> \ comment - - - - H" (SOS>TR)" ' EMU_(SOS>TR) ' NOP SIMPLE-OP: (SOS>TR)
> \ comment - - - - H" (PUSH}" ' EMU_(PUSH} ' NOP SIMPLE-OP: (PUSH}
> \ comment - - - - H" (POP)" ' EMU_(POP) ' NOP SIMPLE-OP: (POP)
> \ comment - - - - H" (RP@>TR)" ' EMU_(RP@>TR) ' NOP SIMPLE-OP: (RP@>TR)
> 0 >XB - - - - H" AMD0_d" ' EMU_AMD0 ' EMU_dfr SIMPLE-OP: AMD0_d
> 1 >XB - - - - H" AMD1_d" ' EMU_AMD1 ' EMU_dfr SIMPLE-OP: AMD1_d
> 2 >XB - - - - H" AMD2_d" ' EMU_AMD2 ' EMU_dfr SIMPLE-OP: AMD2_d
> 3 >XB - - - - H" AMD3_d" ' EMU_AMD3 ' EMU_dfr SIMPLE-OP: AMD3_d
> Done

On Thursday, November 25, 2021 at 1:39:20 AM UTC-8, jpit...@gmail.com wrote:
> On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
> > \ Op Code File for MFX. Generated by MAKE-OPS v13
> >
> > \ MODELS\RACE32\RACE32.ops
> >
> > \ src dst codes J I H G F E D C B A 9 8 7 6 5 4 3 2 1 0
> > \ `--.--' `-.-' | | | | | | | | | | |
> > \ errors -------------' | | | | | | | | | | | |
> > \ constants -----------------' | | | | | | | | | | | - c8_6_5_3
> > \ stack ptr mem ---------------------' | | | | | | | | | | - S PM
> > \ loop ctr ----------------------------' | | | | | | | | | - L LC
> > \ return reg ----------------------------' | | | | | | | | - R RR
> > \ prog ctr --------------------------------' | | | | | | | - P PC
> > \ mem ads -----------------------------------' | | | | | | - F FLG
> > \ flag ----------------------------------------' | | | | | - M MA
> > \ carry -----------------------------------------' | | | | - C CRY
> > \ data reg ----------------------------------------' | | | - D DR
> > \ Treg high (sos) -----------------------------------' | | - T TH
> > \ Treg low (sos) --------------------------------------' | - t TL
> > \ accumulator (tos) -------------------------------------' - A AC
> >
> > \ Deferred cmds:
> > \ Dsrc Ddst codes J I H G F E D C B A 9 8 7 6 5 4 3 2 1 0
> > \ `--.--' `-.-' | | | | | | |
> > \ errors -------------' | | | | | | | |
> > \ constants -----------------' | | | | | | |
> > \ i/o -------------------------------------' | | | | | |
> > \ static mem --------------------------------' | | | | |
> > \ dynamic mem ---------------------------------' | | | |
> > \ reg mem ---------------------------------------' | | |
> > \ Treg high (sos) -----------------------------------' | |
> > \ Treg low (sos) --------------------------------------' |
> > \ accumulator (tos) -------------------------------------'
> >
> > \ now deferred now deferred
> > \ code type src dst Dsrc Ddst instr string emultion emulation operation
> > 0 1 >XBCS tT D - - H" TR>DR" ' EMU_TR>DR ' NOP SIMPLE-OP: TR>DR
> > 1 1 >XBCS D tT - - H" DR>TR" ' EMU_DR>TR ' NOP SIMPLE-OP: DR>TR
> > 2 1 >XBCS A D - - H" AC>DR" ' EMU_AC>DR ' NOP SIMPLE-OP: AC>DR
> > 3 1 >XBCS A F - - H" TR15>FLG" ' EMU_TR15>FLG ' NOP SIMPLE-OP: TR15>FLG
> > 1 2 >XBCS - tT - - H" -1>TRL" ' EMU_-1>TRL ' NOP SIMPLE-OP: -1>TRL
> > 2 2 >XBCS - tT - - H" -1>TRH" ' EMU_-1>TRH ' NOP SIMPLE-OP: -1>TRH
> > 3 2 >XBCS - tT - - H" -1>TR" ' EMU_-1>TR ' NOP SIMPLE-OP: -1>TR
> > 0 3 >XBCS - D - - H" 0>DR" ' EMU_0>DR ' NOP SIMPLE-OP: 0>DR
> > 1 3 >XBCS - tT - - H" 0>TRL" ' EMU_0>TRL ' NOP SIMPLE-OP: 0>TRL
> > 2 3 >XBCS - tT - - H" 0>TRH" ' EMU_0>TRH ' NOP SIMPLE-OP: 0>TRH
> > 3 3 >XBCS - tT - - H" 0>TR" ' EMU_0>TR ' NOP SIMPLE-OP: 0>TR
> > 0 4 >XBCS A D - - H" AC>DR" ' EMU_AC>DR ' NOP SIMPLE-OP: AC>DR
> > 1 4 >XBCS A tT - - H" AC>TR" ' EMU_AC>TR ' NOP SIMPLE-OP: AC>TR
> > 2 4 >XBCS AtT D - - H" AC_OR_TR>DR" ' EMU_AC_OR_TR>DR ' NOP SIMPLE-OP: AC_OR_TR>DR
> > 3 4 >XBCS AD tT - - H" AC_AND_DR>TR" ' EMU_AC_AND_DR>TR ' NOP SIMPLE-OP: AC_AND_DR>TR
> > 0 5 >XBCS - C - - H" 0>CRY" ' EMU_0>CRY ' NOP SIMPLE-OP: 0>CRY
> > 1 5 >XBCS - C - - H" 1>CRY" ' EMU_1>CRY ' NOP SIMPLE-OP: 1>CRY
> > 2 5 >XBCS C CF - - H" 0>CRY>FLG" ' EMU_0>CRY>FLG ' NOP SIMPLE-OP: 0>CRY>FLG
> > 3 5 >XBCS CF CF - - H" CRY><FLG" ' EMU_CRY><FLG ' NOP SIMPLE-OP: CRY><FLG
> > \ code type src dst Dsrc Ddst instr string emultion emulation operation
> > 0 6 >XBCS c6 L - - H" C6>REP" ' EMU_C6>REP ' NOP SIMPLE-OP: C6>REP
> > 1 6 >XBCS Ac6 DL - - H" C6>REP~AC>DR" ' EMU_C6>REP~AC>DR ' NOP SIMPLE-OP: C6>REP~AC>DR
> > 2 6 >XBCS tTc6 DL - - H" C6>REP~TR>DR" ' EMU_C6>REP~TR>DR ' NOP SIMPLE-OP: C6>REP~TR>DR
> > 3 6 >XBCS tTDc6 tTDL - - H" C6>REP~TR><DR" ' EMU_C6>REP~TR><DR ' NOP SIMPLE-OP: C6>REP~TR><DR
> > 0 7 >XBCS AtTc6 DL - - H" C6&AC>REP~0>DR" ' EMU_C6&AC>REP~0>DR ' NOP SIMPLE-OP: C6&AC>REP~0>DR
> > 1 7 >XBCS AtTc6 DL - - H" C6&/AC>REP~0>DR" ' EMU_C6&/AC>REP~0>D ' NOP SIMPLE-OP: C6&/AC>REP~0>DR
> > 2 7 >XBCS c6 L - - H" C6>LOOP" ' EMU_C6>LOOP ' NOP SIMPLE-OP: C6>LOOP
> > 8 >CS - - A r H" AC>*MA_d" ' EMU_AC>*MA ' EMU_WE4 SIMPLE-OP: AC>*MA_d
> > 9 >CS A tT - - H" AC>TRx" ' EMU_AC>TR ' NOP SIMPLE-OP: AC>TRx
> > 1 A >XBCS - - A rds H" AC>*MA_BYT_d" ' EMU_AC>*MA_BYT ' EMU_WE1 SIMPLE-OP: AC>*MA_BYT_d
> > 2 A >XBCS - - A rdso H" ACLW>*MA_d" ' EMU_ACLW>*MA ' EMU_WE2 SIMPLE-OP: ACLW>*MA_d
> > 3 A >XBCS - - A rdso H" ACHW>*MA_d" ' EMU_ACHW>*MA ' EMU_WE3 SIMPLE-OP: ACHW>*MA_d
> > 1 B >XBCS A tT A r H" AC>TR~AC>*MA_d" ' EMU_AC>TR ' EMU_WE4 SIMPLE-OP: AC>TR~AC>*MA_d
> > 2 B >XBCS A D A r H" AC>DR~AC>*MA_d" ' EMU_AC>DR ' EMU_WE4 SIMPLE-OP: AC>DR~AC>*MA_d
> > 3 B >XBCS - - A - H" AC>TR(CS)_d" ' EMU_AC>TR(CS) ' EMU_WE7 SIMPLE-OP: AC>TR(CS)_d
> > 1 C >XBCS - tT ro tT H" *MA>TRL_d" ' EMU_*MA>TRL ' EMU_RE1 SIMPLE-OP: *MA>TRL_d
> > 2 C >XBCS - tT rds tT H" *MA>TRH_d" ' EMU_*MA>TRH ' EMU_RE2 SIMPLE-OP: *MA>TRH_d
> > 3 C >XBCS - tT r tT H" *MA>TR_d" ' EMU_*MA>TR ' EMU_RE3 SIMPLE-OP: *MA>TR_d
> > 1 D >XBCS A tTD r tT H" AC>DR~*MA>TR_d" ' EMU_AC>DR ' EMU_RE3 SIMPLE-OP: AC>DR~*MA>TR_d
> > \ code type src dst Dsrc Ddst instr string emultion emulation operation
> > 2 D >XBCS tT tTD r tT H" TR>DR~*MA>TR_d" ' EMU_TR>DR ' EMU_RE3 SIMPLE-OP: TR>DR~*MA>TR_d
> > F >CS - tT ro tT H" *MA>NXT_d" ' EMU_*MA>NXT ' EMU_RE4 SIMPLE-OP: *MA>NXT_d
> > 0 10 >XBCS CPc6 P - - H" IF_CRY+JMP" ' EMU_IF_CRY+JMP ' NOP COUNT-OP: IF_CRY+JMP
> > 1 10 >XBCS CPc6 P - - H" IF/CRY+JMP" ' EMU_IF/CRY+JMP ' NOP COUNT-OP: IF/CRY+JMP
> > 2 10 >XBCS FPc6 P - - H" IF_FLG+JMP" ' EMU_IF_FLG+JMP ' NOP COUNT-OP: IF_FLG+JMP
> > 3 10 >XBCS FPc6 P - - H" IF/FLG+JMP" ' EMU_IF/FLG+JMP ' NOP COUNT-OP: IF/FLG+JMP
> > 0 11 >XBCS APc6 P - - H" IF_AC0+JMP" ' EMU_IF_AC0+JMP ' NOP COUNT-OP: IF_AC0+JMP
> > 1 11 >XBCS APc6 P - - H" IF/AC0+JMP" ' EMU_IF/AC0+JMP ' NOP COUNT-OP: IF/AC0+JMP
> > 2 11 >XBCS APc6 P - - H" IF_AC31+JMP" ' EMU_IF_AC31+JMP ' NOP COUNT-OP: IF_AC31+JMP
> > 3 11 >XBCS APc6 P - - H" IF/AC31+JMP" ' EMU_IF/AC31+JMP ' NOP COUNT-OP: IF/AC31+JMP
> > 0 12 >XBCS CPc6 P - - H" IF_CRY-JMP" ' EMU_IF_CRY-JMP ' NOP COUNT-OP: IF_CRY-JMP
> > 1 12 >XBCS CPc6 P - - H" IF/CRY-JMP" ' EMU_IF/CRY-JMP ' NOP COUNT-OP: IF/CRY-JMP
> > 2 12 >XBCS FPc6 P - - H" IF_FLG-JMP" ' EMU_IF_FLG-JMP ' NOP COUNT-OP: IF_FLG-JMP
> > 3 12 >XBCS FPc6 P - - H" IF/FLG-JMP" ' EMU_IF/FLG-JMP ' NOP COUNT-OP: IF/FLG-JMP
> > 0 13 >XBCS APc6 P - - H" IF_AC0-JMP" ' EMU_IF_AC0-JMP ' NOP COUNT-OP: IF_AC0-JMP
> > 1 13 >XBCS APc6 P - - H" IF/AC0-JMP" ' EMU_IF/AC0-JMP ' NOP COUNT-OP: IF/AC0-JMP
> > 2 13 >XBCS APc6 P - - H" IF_AC31-JMP" ' EMU_IF_AC31-JMP ' NOP COUNT-OP: IF_AC31-JMP
> > 3 13 >XBCS APc6 P - - H" IF/AC31-JMP" ' EMU_IF/AC31-JMP ' NOP COUNT-OP: IF/AC31-JMP
> > 0 14 >XBCS Pc8 P - - H" +JMP" ' EMU_+JMP ' NOP COUNT-OP: +JMP
> > \ code type src dst Dsrc Ddst instr string emultion emulation operation
> > 1 14 >XBCS APc6 P - - H" IF/AC1+JMP" ' EMU_IF/AC1+JMP ' NOP COUNT-OP: IF/AC1+JMP
> > 2 14 >XBCS APc6 P - - H" IF/AC2+JMP" ' EMU_IF/AC2+JMP ' NOP COUNT-OP: IF/AC2+JMP
> > 3 14 >XBCS APc6 P - - H" IF/AC3+JMP" ' EMU_IF/AC3+JMP ' NOP COUNT-OP: IF/AC3+JMP
> > 0 15 >XBCS APc6 P - - H" IF/AC4+JMP" ' EMU_IF/AC4+JMP ' NOP COUNT-OP: IF/AC4+JMP
> > 1 15 >XBCS APc6 P - - H" IF/AC5+JMP" ' EMU_IF/AC5+JMP ' NOP COUNT-OP: IF/AC5+JMP
> > 2 15 >XBCS APc6 P - - H" IF/AC6+JMP" ' EMU_IF/AC6+JMP ' NOP COUNT-OP: IF/AC6+JMP
> > 3 15 >XBCS APc6 P - - H" IF/AC7+JMP" ' EMU_IF/AC7+JMP ' NOP COUNT-OP: IF/AC7+JMP
> > 0 16 >XBCS Pc8 P - - H" -JMP" ' EMU_-JMP ' NOP COUNT-OP: -JMP
> > 1 16 >XBCS PLc6 P - - H" IF_REP-JMP" ' EMU_IF_REP-JMP ' NOP COUNT-OP: IF_REP-JMP
> > 2 16 >XBCS c8 P - - H" JMP&LINK" ' EMU_JMP&LINK ' NOP COUNT-OP: JMP&LINK
> > 3 16 >XBCS R P - - H" RET_LINK" ' EMU_RET_LINK ' NOP COUNT-OP: RET_LINK
> > 0 17 >XBCS t tT - - H" TR_RL" ' EMU_TR_RL ' NOP SIMPLE-OP: TR_RL
> > 1 17 >XBCS At tT - - H" TR_RL_DR" ' EMU_TR_RL_DR ' NOP SIMPLE-OP: TR_RL_DR
> > 2 17 >XBCS tD tT - - H" TR_RL_AC" ' EMU_TR_RL_AC ' NOP SIMPLE-OP: TR_RL_AC
> > 3 17 >XBCS tTC tTC - - H" TR_RLC" ' EMU_TR_RLC ' NOP SIMPLE-OP: TR_RLC
> > 0 18 >XBCS tT tT - - H" TR_RR" ' EMU_TR_RR ' NOP SIMPLE-OP: TR_RR
> > 1 18 >XBCS tT tT - - H" TR_RR_DR" ' EMU_TR_RR_DR ' NOP SIMPLE-OP: TR_RR_DR
> > 2 18 >XBCS tT tT - - H" TR_RR_AC" ' EMU_TR_RR_AC ' NOP SIMPLE-OP: TR_RR_AC
> > 3 18 >XBCS tT tTC - - H" TR_RRC" ' EMU_TR_RRC ' NOP SIMPLE-OP: TR_RRC
> > \ code type src dst Dsrc Ddst instr string emultion emulation operation
> > 0 19 >XBCS tT tT - - H" TR_RRB" ' EMU_TR_RRB ' NOP SIMPLE-OP: TR_RRB
> > 1 19 >XBCS tT tT - - H" TR_RRB_DR" ' EMU_TR_RRB_DR ' NOP SIMPLE-OP: TR_RRB_DR
> > 2 19 >XBCS tT tT - - H" TR_RRB_AC" ' EMU_TR_RRB_AC ' NOP SIMPLE-OP: TR_RRB_AC
> > 3 19 >XBCS tT tT - - H" TR_SRB" ' EMU_TR_SRB ' NOP SIMPLE-OP: TR_SRB
> > 0 1A >XBCS D D - - H" DR_RL" ' EMU_DR_RL ' NOP SIMPLE-OP: DR_RL
> > 1 1A >XBCS D D - - H" DR_RL" ' EMU_DR_RL ' NOP SIMPLE-OP: DR_RL
> > 2 1A >XBCS tD D - - H" DR_RL-TR" ' EMU_DR_RL_TR ' NOP SIMPLE-OP: DR_RL-TR
> > 3 1A >XBCS DC DC - - H" DR_RLC" ' EMU_DR_RLC ' NOP SIMPLE-OP: DR_RLC
> > 0 1B >XBCS D D - - H" DR_RR" ' EMU_DR_RR ' NOP SIMPLE-OP: DR_RR
> > 1 1B >XBCS AD D - - H" DR_RR_AC" ' EMU_DR_RR_AC ' NOP SIMPLE-OP: DR_RR_AC
> > 2 1B >XBCS TD D - - H" DR_RR_TR" ' EMU_DR_RR_TR ' NOP SIMPLE-OP: DR_RR_TR
> > 3 1B >XBCS DC DC - - H" DR_RRC" ' EMU_DR_RRC ' NOP SIMPLE-OP: DR_RRC
> > 0 1C >XBCS D D - - H" DR_RRB" ' EMU_DR_RRB ' NOP SIMPLE-OP: DR_RRB
> > 1 1C >XBCS AD D - - H" DR_RRB_AC" ' EMU_DR_RRB_AC ' NOP SIMPLE-OP: DR_RRB_AC
> > 2 1C >XBCS tD D - - H" DR_RRB_TR" ' EMU_DR_RRB_TR ' NOP SIMPLE-OP: DR_RRB_TR
> > 3 1C >XBCS D D - - H" DR_SRB" ' EMU_DR_SRB ' NOP SIMPLE-OP: DR_SRB
> > 2 1D >XBCS tD tTD - - H" TR_DR_RL_AC" ' EMU_TR_DR_RL_AC ' NOP SIMPLE-OP: TR_DR_RL_AC
> > 0 1E >XBCS tTD tTD - - H" TR_DR_RR" ' EMU_TR_DR_RR ' NOP SIMPLE-OP: TR_DR_RR
> > 2 1E >XBCS AtTD tTD - - H" TR_DR_RR_AC" ' EMU_TR_DR_RR_AC ' NOP SIMPLE-OP: TR_DR_RR_AC
> > \ code type src dst Dsrc Ddst instr string emultion emulation operation
> > 2 1F >XBCS tTD tTD - - H" TR_DR_RRB_AC" ' EMU_TR_DR_RRB_AC ' NOP SIMPLE-OP: TR_DR_RRB_AC
> > 0 >MA - M - - H" hold" ' EMU_MA>MA ' NOP JMPL-OP: hold
> > 1 0 >MAPT A M - - H" IP>MA" ' EMU_PM>MA ' NOP JMPL-OP: IP>MA
> > 1 1 >MAPT A M - - H" RP>MA" ' EMU_PM>MA ' NOP JMPL-OP: RP>MA
> > 1 2 >MAPT A M - - H" SP>MA" ' EMU_PM>MA ' NOP JMPL-OP: SP>MA
> > 1 3 >MAPT A M - - H" DP>MA" ' EMU_PM>MA ' NOP JMPL-OP: DP>MA
> > 1 4 >MAPT Sc5 M - - H" MA+C>MA" ' EMU_MA+C>MA ' NOP JMPL-OP: MA+C>MA
> > 1 5 >MAPT Sc5 M - - H" MA-C>MA" ' EMU_MA-C>MA ' NOP JMPL-OP: MA-C>MA
> > 1 6 >MAPT Sc5 M - - H" MA+C>MAu" ' EMU_MA+C>MA ' NOP JMPL-OP: MA+C>MAu
> > 1 7 >MAPT Sc5 M - - H" MA-C>MAu" ' EMU_MA-C>MA ' NOP JMPL-OP: MA-C>MAu
> > 2 >MA M M - - H" AC>MA" ' EMU_AC>MA ' NOP JMPL-OP: AC>MA
> > 3 >MA tTS M - - H" MA-TR>MAu" ' EMU_MA-TR>MA ' NOP JMPL-OP: MA-TR>MAu
> > 4 >MA Mc6 M - - H" AC+C8>MA" ' EMU_AC+C8>MA ' NOP JMPL-OP: AC+C8>MA
> > 5 0 >MAPT A M - - H" IP+2>MAu" ' EMU_PM+2>MA ' NOP JMPL-OP: IP+2>MAu
> > 5 1 >MAPT tT M - - H" TR>MAu" ' EMU_TR>MA ' NOP JMPL-OP: TR>MAu
> > 5 2 >MAPT tT M - - H" TR+2>MAu" ' EMU_TR+2>MA ' NOP JMPL-OP: TR+2>MAu
> > 5 5 >MAPT tT M - - H" TR>MA" ' EMU_TR>MA ' NOP JMPL-OP: TR>MA
> > 5 6 >MAPT tT M - - H" TR+2>MA" ' EMU_TR+2>MA ' NOP JMPL-OP: TR+2>MA
> > 5 7 >MAPT S M - - H" MA+4>MA" ' EMU_MA+4>MA ' NOP JMPL-OP: MA+4>MA
> > \ code type src dst Dsrc Ddst instr string emultion emulation operation
> > 6 0 >MAPT Ac5 M - - H" IP+C>MA" ' EMU_PM+C>MA ' NOP JMPL-OP: IP+C>MA
> > 6 1 >MAPT Ac5 M - - H" RP+C>MA" ' EMU_PM+C>MA ' NOP JMPL-OP: RP+C>MA
> > 6 2 >MAPT Ac5 M - - H" SP+C>MA" ' EMU_PM+C>MA ' NOP JMPL-OP: SP+C>MA
> > 6 3 >MAPT Ac3 M - - H" DP+C5>MA" ' EMU_PM+C5>MA ' NOP JMPL-OP: DP+C5>MA
> > 6 4 >MAPT Ac5 M - - H" IP+C>MAu" ' EMU_PM+C>MA ' NOP JMPL-OP: IP+C>MAu
> > 6 5 >MAPT Ac5 M - - H" RP+C>MAu" ' EMU_PM+C>MA ' NOP JMPL-OP: RP+C>MAu
> > 6 6 >MAPT Ac5 M - - H" SP+C>MAu" ' EMU_PM+C>MA ' NOP JMPL-OP: SP+C>MAu
> > 6 7 >MAPT Ac3 M - - H" DP+C5>MAu" ' EMU_PM+C5>MA ' NOP JMPL-OP: DP+C5>MAu
> > 7 0 >MAPT Ac5 M - - H" IP-C>MA" ' EMU_PM-C>MA ' NOP JMPL-OP: IP-C>MA
> > 7 1 >MAPT Ac5 M - - H" RP-C>MA" ' EMU_PM-C>MA ' NOP JMPL-OP: RP-C>MA
> > 7 2 >MAPT Ac5 M - - H" SP-C>MA" ' EMU_PM-C>MA ' NOP JMPL-OP: SP-C>MA
> > 7 3 >MAPT Ac3 M - - H" DP-C5>MA" ' EMU_PM-C5>MA ' NOP JMPL-OP: DP-C5>MA
> > 7 4 >MAPT Ac5 M - - H" IP-C>MAu" ' EMU_PM-C>MA ' NOP JMPL-OP: IP-C>MAu
> > 7 5 >MAPT Ac5 M - - H" RP-C>MAu" ' EMU_PM-C>MA ' NOP JMPL-OP: RP-C>MAu
> > 7 6 >MAPT Ac5 M - - H" SP-C>MAu" ' EMU_PM-C>MA ' NOP JMPL-OP: SP-C>MAu
> > 7 7 >MAPT Ac3 M - - H" DP-C5>MAu" ' EMU_PM-C5>MA ' NOP JMPL-OP: DP-C5>MAu
> > 1 >AC AM0 FM A - - H" MA>AC" ' EMU_MA>AC ' NOP SIMPLE-OP: MA>AC
> > 2 0 >ACRA AM0 A AC - - H" AC-1>ACC" ' EMU_AC-1>ACC ' NOP SIMPLE-OP: AC-1>ACC
> > 2 1 >ACRA AM0 A AC - - H" AC+1>ACC" ' EMU_AC+1>ACC ' NOP SIMPLE-OP: AC+1>ACC
> > \ code type src dst Dsrc Ddst instr string emultion emulation operation
> > 2 2 >ACRA AM0 A A - - H" AC-1>AC" ' EMU_AC-1>AC ' NOP SIMPLE-OP: AC-1>AC
> > 2 3 >ACRA AM0 A A - - H" AC+1>AC" ' EMU_AC+1>AC ' NOP SIMPLE-OP: AC+1>AC
> > 2 4 >ACRA AM0 AC A - - H" AC+CRY>AC" ' EMU_AC+CRY>AC ' NOP SIMPLE-OP: AC+CRY>AC
> > 2 5 >ACRA AM0 AC A - - H" AC+CRY>AC" ' EMU_AC+CRY>AC ' NOP SIMPLE-OP: AC+CRY>AC
> > 2 7 >ACRA AM0 tT A - - H" TR+1>AC" ' EMU_TR+1>AC ' NOP SIMPLE-OP: TR+1>AC
> > 3 1 >ACRA AM0 - A - - H" 0>AC" ' EMU_0>AC ' NOP SIMPLE-OP: 0>AC
> > 3 2 >ACRA AM0 tT A - - H" TR>AC" ' EMU_TR>AC ' NOP SIMPLE-OP: TR>AC
> > 3 3 >ACRA AM0 D A - - H" DR>AC" ' EMU_DR>AC ' NOP SIMPLE-OP: DR>AC
> > 1 >AC AM1 C A - - H" CRY>AC" ' EMU_CRY>AC ' NOP SIMPLE-OP: CRY>AC
> > 2 >AC AM1 tT A - - H" TR>ACx" ' EMU_TR>AC ' NOP SIMPLE-OP: TR>ACx
> > 3 >AC AM1 D A - - H" DR>ACx" ' EMU_DR>AC ' NOP SIMPLE-OP: DR>ACx
> > 1 >AC AM2 c8 A - - H" C8>AC" ' EMU_C8>AC ' NOP SIMPLE-OP: C8>AC
> > 2 1 >ACRA AM2 AD A - - H" AC_XOR_DR>AC" ' EMU_AC_XOR_DR>AC ' NOP SIMPLE-OP: AC_XOR_DR>AC
> > 2 2 >ACRA AM2 tT A - - H" TR+1>ACx" ' EMU_TR+1>AC ' NOP SIMPLE-OP: TR+1>ACx
> > 2 4 >ACRA AM2 AtT AC - - H" AC-TR>ACC" ' EMU_AC-TR>ACC ' NOP SIMPLE-OP: AC-TR>ACC
> > 2 5 >ACRA AM2 AtT AC - - H" AC+TR>ACC" ' EMU_AC+TR>ACC ' NOP SIMPLE-OP: AC+TR>ACC
> > 2 6 >ACRA AM2 AtT A - - H" AC-TR>AC" ' EMU_AC-TR>AC ' NOP SIMPLE-OP: AC-TR>AC
> > 2 7 >ACRA AM2 AtT A - - H" AC+TR>AC" ' EMU_AC+TR>AC ' NOP SIMPLE-OP: AC+TR>AC
> > 1 0 >ACPT AM3 A A - - H" AC_SL" ' EMU_AC_SL ' NOP SIMPLE-OP: AC_SL
> > \ code type src dst Dsrc Ddst instr string emultion emulation operation
> > 2 0 >ACPT AM3 AC AC - - H" AC_RLC" ' EMU_AC_RLC ' NOP SIMPLE-OP: AC_RLC
> > 1 1 >ACPT AM3 A A - - H" AC_RL" ' EMU_AC_RL ' NOP SIMPLE-OP: AC_RL
> > 2 1 >ACPT AM3 At A - - H" AC_RL_TR" ' EMU_AC_RL_TR ' NOP SIMPLE-OP: AC_RL_TR
> > 3 1 >ACPT AM3 AD A - - H" AC_RL_DR" ' EMU_AC_RL_DR ' NOP SIMPLE-OP: AC_RL_DR
> > 1 2 >ACPT AM3 A A - - H" AC_SR" ' EMU_AC_SR ' NOP SIMPLE-OP: AC_SR
> > 2 2 >ACPT AM3 AC AC - - H" AC_RRC" ' EMU_AC_RRC ' NOP SIMPLE-OP: AC_RRC
> > 1 3 >ACPT AM3 A A - - H" AC_RR" ' EMU_AC_RR ' NOP SIMPLE-OP: AC_RR
> > 2 3 >ACPT AM3 AT A - - H" AC_RR_TR" ' EMU_AC_RR_TR ' NOP SIMPLE-OP: AC_RR_TR
> > 3 3 >ACPT AM3 AD A - - H" AC_RR_DR" ' EMU_AC_RR_DR ' NOP SIMPLE-OP: AC_RR_DR
> > 1 4 >ACPT AM3 A A - - H" AC_SRB" ' EMU_AC_SRB ' NOP SIMPLE-OP: AC_SRB
> > 2 4 >ACPT AM3 A A - - H" AC_RRB" ' EMU_AC_RRB ' NOP SIMPLE-OP: AC_RRB
> > 3 4 >ACPT AM3 AD A - - H" AC_RRB_AC" ' EMU_AC_RRB_AC ' NOP SIMPLE-OP: AC_RRB_AC
> > 1 5 >ACPT AM3 At A - - H" AC_RRB_TR" ' EMU_AC_RRB_TR ' NOP SIMPLE-OP: AC_RRB_TR
> > 2 5 >ACPT AM3 AD A - - H" AC_RRB_DR" ' EMU_AC_RRB_DR ' NOP SIMPLE-OP: AC_RRB_DR
> > 1 6 >ACPT AM3 AtT A - - H" MPY>AC" ' EMU_MPY>AC ' NOP SIMPLE-OP: MPY>AC
> > 2 6 >ACPT AM3 AtTDC A - - H" DIV>AC" ' EMU_DIV>AC ' NOP SIMPLE-OP: DIV>AC
> > 7 5 2 >MAPTR - - - - H" RP-4>MAu" ' EMU_RP-4>MAu ' NOP SIMPLE-OP: RP-4>MAu
> > 5 4 0 >MAPTR - - - - H" TR>MAu" ' EMU_TR>MAu ' NOP SIMPLE-OP: TR>MAu
> > 6 5 2 >MAPTR - - - - H" RP+4>MAu" ' EMU_RP+4>MAu ' NOP SIMPLE-OP: RP+4>MAu
> > \ code type src dst Dsrc Ddst instr string emultion emulation operation
> > 5 4 1 >MAPTR - - - - H" TR+2>MAu" ' EMU_TR+2>MAu ' NOP SIMPLE-OP: TR+2>MAu
> > 6 4 1 >MAPTR - - - - H" IP+2>MAu" ' EMU_IP+2>MAu ' NOP SIMPLE-OP: IP+2>MAu
> > 1 6 1 >MAPTR - - - - H" MA+2>MAu" ' EMU_MA+2>MAu ' NOP SIMPLE-OP: MA+2>MAu
> > 6 6 2 >MAPTR - - - - H" SP+4>MAu" ' EMU_SP+4>MAu ' NOP SIMPLE-OP: SP+4>MAu
> > 6 6 4 >MAPTR - - - - H" SP+8>MAu" ' EMU_SP+8>MAu ' NOP SIMPLE-OP: SP+8>MAu
> > 7 5 4 >MAPTR - - - - H" RP-8>MAu" ' EMU_RP-8>MAu ' NOP SIMPLE-OP: RP-8>MAu
> > 7 6 2 >MAPTR - - - - H" SP-4>MAu" ' EMU_SP-4>MAu ' NOP SIMPLE-OP: SP-4>MAu
> > 7 2 2 >MAPTR - - - - H" SP-4>MA" ' EMU_SP-4>MA ' NOP SIMPLE-OP: SP-4>MA
> > 6 1 2 >MAPTR - - - - H" RP+4>MA" ' EMU_RP+4>MA ' NOP SIMPLE-OP: RP+4>MA
> > 6 5 4 >MAPTR - - - - H" RP+8>MAu" ' EMU_RP+8>MAu ' NOP SIMPLE-OP: RP+8>MAu
> > \ comment - - - - H" (SOS>TR)" ' EMU_(SOS>TR) ' NOP SIMPLE-OP: (SOS>TR)
> > \ comment - - - - H" (PUSH}" ' EMU_(PUSH} ' NOP SIMPLE-OP: (PUSH}
> > \ comment - - - - H" (POP)" ' EMU_(POP) ' NOP SIMPLE-OP: (POP)
> > \ comment - - - - H" (RP@>TR)" ' EMU_(RP@>TR) ' NOP SIMPLE-OP: (RP@>TR)
> > 0 >XB - - - - H" AMD0_d" ' EMU_AMD0 ' EMU_dfr SIMPLE-OP: AMD0_d
> > 1 >XB - - - - H" AMD1_d" ' EMU_AMD1 ' EMU_dfr SIMPLE-OP: AMD1_d
> > 2 >XB - - - - H" AMD2_d" ' EMU_AMD2 ' EMU_dfr SIMPLE-OP: AMD2_d
> > 3 >XB - - - - H" AMD3_d" ' EMU_AMD3 ' EMU_dfr SIMPLE-OP: AMD3_d
> > Done
> Thank you very much John - let's see what happens next.
> Just for the fun of it I formatted it slightly in a way that makes the blocks a bit clearer to me
> https://www.dropbox.com/sh/ah8umk0hgq1818s/AAC8nNEueZZcIYJ8uGP4F4wPa?dl=0

> Forth AI coder's note:
> FPGA stands for field-programmable gate array.
>
As that guy in the commercial says: "Thank you captain obvious"

On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit...@gmail.com wrote:
> On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
> > \ Op Code File for MFX. Generated by MAKE-OPS v13
> >
> > \ MODELS\RACE32\RACE32.ops
> >
> > \ src dst codes J I H G F E D C B A 9 8 7 6 5 4 3 2 1 0
> > \ `--.--' `-.-' | | | | | | | | | | |
> > \ errors -------------' | | | | | | | | | | | |
> > \ constants -----------------' | | | | | | | | | | | - c8_6_5_3
> > \ stack ptr mem ---------------------' | | | | | | | | | | - S PM
> > \ loop ctr ----------------------------' | | | | | | | | | - L LC
> > \ return reg ----------------------------' | | | | | | | | - R RR
> > \ prog ctr --------------------------------' | | | | | | | - P PC
> > \ mem ads -----------------------------------' | | | | | | - F FLG
> > \ flag ----------------------------------------' | | | | | - M MA
> > \ carry -----------------------------------------' | | | | - C CRY
> > \ data reg ----------------------------------------' | | | - D DR
> > \ Treg high (sos) -----------------------------------' | | - T TH
> > \ Treg low (sos) --------------------------------------' | - t TL
> > \ accumulator (tos) -------------------------------------' - A AC
> >
> > \ Deferred cmds:
> > \ Dsrc Ddst codes J I H G F E D C B A 9 8 7 6 5 4 3 2 1 0
> > \ `--.--' `-.-' | | | | | | |
> > \ errors -------------' | | | | | | | |
> > \ constants -----------------' | | | | | | |
> > \ i/o -------------------------------------' | | | | | |
> > \ static mem --------------------------------' | | | | |
> > \ dynamic mem ---------------------------------' | | | |
> > \ reg mem ---------------------------------------' | | |
> > \ Treg high (sos) -----------------------------------' | |
> > \ Treg low (sos) --------------------------------------' |
> > \ accumulator (tos) -------------------------------------'
> >
> > \ now deferred now deferred
> > \ code type src dst Dsrc Ddst instr string emultion emulation operation
> > 0 1 >XBCS tT D - - H" TR>DR" ' EMU_TR>DR ' NOP SIMPLE-OP: TR>DR
> > 1 1 >XBCS D tT - - H" DR>TR" ' EMU_DR>TR ' NOP SIMPLE-OP: DR>TR
> > 2 1 >XBCS A D - - H" AC>DR" ' EMU_AC>DR ' NOP SIMPLE-OP: AC>DR
> > 3 1 >XBCS A F - - H" TR15>FLG" ' EMU_TR15>FLG ' NOP SIMPLE-OP: TR15>FLG
> > 1 2 >XBCS - tT - - H" -1>TRL" ' EMU_-1>TRL ' NOP SIMPLE-OP: -1>TRL
> > 2 2 >XBCS - tT - - H" -1>TRH" ' EMU_-1>TRH ' NOP SIMPLE-OP: -1>TRH
> > 3 2 >XBCS - tT - - H" -1>TR" ' EMU_-1>TR ' NOP SIMPLE-OP: -1>TR
> > 0 3 >XBCS - D - - H" 0>DR" ' EMU_0>DR ' NOP SIMPLE-OP: 0>DR
> > 1 3 >XBCS - tT - - H" 0>TRL" ' EMU_0>TRL ' NOP SIMPLE-OP: 0>TRL
> > 2 3 >XBCS - tT - - H" 0>TRH" ' EMU_0>TRH ' NOP SIMPLE-OP: 0>TRH
> > 3 3 >XBCS - tT - - H" 0>TR" ' EMU_0>TR ' NOP SIMPLE-OP: 0>TR
> > 0 4 >XBCS A D - - H" AC>DR" ' EMU_AC>DR ' NOP SIMPLE-OP: AC>DR
> > 1 4 >XBCS A tT - - H" AC>TR" ' EMU_AC>TR ' NOP SIMPLE-OP: AC>TR
> > 2 4 >XBCS AtT D - - H" AC_OR_TR>DR" ' EMU_AC_OR_TR>DR ' NOP SIMPLE-OP: AC_OR_TR>DR
> > 3 4 >XBCS AD tT - - H" AC_AND_DR>TR" ' EMU_AC_AND_DR>TR ' NOP SIMPLE-OP: AC_AND_DR>TR
> > 0 5 >XBCS - C - - H" 0>CRY" ' EMU_0>CRY ' NOP SIMPLE-OP: 0>CRY
> > 1 5 >XBCS - C - - H" 1>CRY" ' EMU_1>CRY ' NOP SIMPLE-OP: 1>CRY
> > 2 5 >XBCS C CF - - H" 0>CRY>FLG" ' EMU_0>CRY>FLG ' NOP SIMPLE-OP: 0>CRY>FLG
> > 3 5 >XBCS CF CF - - H" CRY><FLG" ' EMU_CRY><FLG ' NOP SIMPLE-OP: CRY><FLG
> > \ code type src dst Dsrc Ddst instr string emultion emulation operation
> > 0 6 >XBCS c6 L - - H" C6>REP" ' EMU_C6>REP ' NOP SIMPLE-OP: C6>REP
> > 1 6 >XBCS Ac6 DL - - H" C6>REP~AC>DR" ' EMU_C6>REP~AC>DR ' NOP SIMPLE-OP: C6>REP~AC>DR
> > 2 6 >XBCS tTc6 DL - - H" C6>REP~TR>DR" ' EMU_C6>REP~TR>DR ' NOP SIMPLE-OP: C6>REP~TR>DR
> > 3 6 >XBCS tTDc6 tTDL - - H" C6>REP~TR><DR" ' EMU_C6>REP~TR><DR ' NOP SIMPLE-OP: C6>REP~TR><DR
> > 0 7 >XBCS AtTc6 DL - - H" C6&AC>REP~0>DR" ' EMU_C6&AC>REP~0>DR ' NOP SIMPLE-OP: C6&AC>REP~0>DR
> > 1 7 >XBCS AtTc6 DL - - H" C6&/AC>REP~0>DR" ' EMU_C6&/AC>REP~0>D ' NOP SIMPLE-OP: C6&/AC>REP~0>DR
> > 2 7 >XBCS c6 L - - H" C6>LOOP" ' EMU_C6>LOOP ' NOP SIMPLE-OP: C6>LOOP
> > 8 >CS - - A r H" AC>*MA_d" ' EMU_AC>*MA ' EMU_WE4 SIMPLE-OP: AC>*MA_d
> > 9 >CS A tT - - H" AC>TRx" ' EMU_AC>TR ' NOP SIMPLE-OP: AC>TRx
> > 1 A >XBCS - - A rds H" AC>*MA_BYT_d" ' EMU_AC>*MA_BYT ' EMU_WE1 SIMPLE-OP: AC>*MA_BYT_d
> > 2 A >XBCS - - A rdso H" ACLW>*MA_d" ' EMU_ACLW>*MA ' EMU_WE2 SIMPLE-OP: ACLW>*MA_d
> > 3 A >XBCS - - A rdso H" ACHW>*MA_d" ' EMU_ACHW>*MA ' EMU_WE3 SIMPLE-OP: ACHW>*MA_d
> > 1 B >XBCS A tT A r H" AC>TR~AC>*MA_d" ' EMU_AC>TR ' EMU_WE4 SIMPLE-OP: AC>TR~AC>*MA_d
> > 2 B >XBCS A D A r H" AC>DR~AC>*MA_d" ' EMU_AC>DR ' EMU_WE4 SIMPLE-OP: AC>DR~AC>*MA_d
> > 3 B >XBCS - - A - H" AC>TR(CS)_d" ' EMU_AC>TR(CS) ' EMU_WE7 SIMPLE-OP: AC>TR(CS)_d
> > 1 C >XBCS - tT ro tT H" *MA>TRL_d" ' EMU_*MA>TRL ' EMU_RE1 SIMPLE-OP: *MA>TRL_d
> > 2 C >XBCS - tT rds tT H" *MA>TRH_d" ' EMU_*MA>TRH ' EMU_RE2 SIMPLE-OP: *MA>TRH_d
> > 3 C >XBCS - tT r tT H" *MA>TR_d" ' EMU_*MA>TR ' EMU_RE3 SIMPLE-OP: *MA>TR_d
> > 1 D >XBCS A tTD r tT H" AC>DR~*MA>TR_d" ' EMU_AC>DR ' EMU_RE3 SIMPLE-OP: AC>DR~*MA>TR_d
> > \ code type src dst Dsrc Ddst instr string emultion emulation operation
> > 2 D >XBCS tT tTD r tT H" TR>DR~*MA>TR_d" ' EMU_TR>DR ' EMU_RE3 SIMPLE-OP: TR>DR~*MA>TR_d
> > F >CS - tT ro tT H" *MA>NXT_d" ' EMU_*MA>NXT ' EMU_RE4 SIMPLE-OP: *MA>NXT_d
> > 0 10 >XBCS CPc6 P - - H" IF_CRY+JMP" ' EMU_IF_CRY+JMP ' NOP COUNT-OP: IF_CRY+JMP
> > 1 10 >XBCS CPc6 P - - H" IF/CRY+JMP" ' EMU_IF/CRY+JMP ' NOP COUNT-OP: IF/CRY+JMP
> > 2 10 >XBCS FPc6 P - - H" IF_FLG+JMP" ' EMU_IF_FLG+JMP ' NOP COUNT-OP: IF_FLG+JMP
> > 3 10 >XBCS FPc6 P - - H" IF/FLG+JMP" ' EMU_IF/FLG+JMP ' NOP COUNT-OP: IF/FLG+JMP
> > 0 11 >XBCS APc6 P - - H" IF_AC0+JMP" ' EMU_IF_AC0+JMP ' NOP COUNT-OP: IF_AC0+JMP
> > 1 11 >XBCS APc6 P - - H" IF/AC0+JMP" ' EMU_IF/AC0+JMP ' NOP COUNT-OP: IF/AC0+JMP
> > 2 11 >XBCS APc6 P - - H" IF_AC31+JMP" ' EMU_IF_AC31+JMP ' NOP COUNT-OP: IF_AC31+JMP
> > 3 11 >XBCS APc6 P - - H" IF/AC31+JMP" ' EMU_IF/AC31+JMP ' NOP COUNT-OP: IF/AC31+JMP
> > 0 12 >XBCS CPc6 P - - H" IF_CRY-JMP" ' EMU_IF_CRY-JMP ' NOP COUNT-OP: IF_CRY-JMP
> > 1 12 >XBCS CPc6 P - - H" IF/CRY-JMP" ' EMU_IF/CRY-JMP ' NOP COUNT-OP: IF/CRY-JMP
> > 2 12 >XBCS FPc6 P - - H" IF_FLG-JMP" ' EMU_IF_FLG-JMP ' NOP COUNT-OP: IF_FLG-JMP
> > 3 12 >XBCS FPc6 P - - H" IF/FLG-JMP" ' EMU_IF/FLG-JMP ' NOP COUNT-OP: IF/FLG-JMP
> > 0 13 >XBCS APc6 P - - H" IF_AC0-JMP" ' EMU_IF_AC0-JMP ' NOP COUNT-OP: IF_AC0-JMP
> > 1 13 >XBCS APc6 P - - H" IF/AC0-JMP" ' EMU_IF/AC0-JMP ' NOP COUNT-OP: IF/AC0-JMP
> > 2 13 >XBCS APc6 P - - H" IF_AC31-JMP" ' EMU_IF_AC31-JMP ' NOP COUNT-OP: IF_AC31-JMP
> > 3 13 >XBCS APc6 P - - H" IF/AC31-JMP" ' EMU_IF/AC31-JMP ' NOP COUNT-OP: IF/AC31-JMP
> > 0 14 >XBCS Pc8 P - - H" +JMP" ' EMU_+JMP ' NOP COUNT-OP: +JMP
> > \ code type src dst Dsrc Ddst instr string emultion emulation operation
> > 1 14 >XBCS APc6 P - - H" IF/AC1+JMP" ' EMU_IF/AC1+JMP ' NOP COUNT-OP: IF/AC1+JMP
> > 2 14 >XBCS APc6 P - - H" IF/AC2+JMP" ' EMU_IF/AC2+JMP ' NOP COUNT-OP: IF/AC2+JMP
> > 3 14 >XBCS APc6 P - - H" IF/AC3+JMP" ' EMU_IF/AC3+JMP ' NOP COUNT-OP: IF/AC3+JMP
> > 0 15 >XBCS APc6 P - - H" IF/AC4+JMP" ' EMU_IF/AC4+JMP ' NOP COUNT-OP: IF/AC4+JMP
> > 1 15 >XBCS APc6 P - - H" IF/AC5+JMP" ' EMU_IF/AC5+JMP ' NOP COUNT-OP: IF/AC5+JMP
> > 2 15 >XBCS APc6 P - - H" IF/AC6+JMP" ' EMU_IF/AC6+JMP ' NOP COUNT-OP: IF/AC6+JMP
> > 3 15 >XBCS APc6 P - - H" IF/AC7+JMP" ' EMU_IF/AC7+JMP ' NOP COUNT-OP: IF/AC7+JMP
> > 0 16 >XBCS Pc8 P - - H" -JMP" ' EMU_-JMP ' NOP COUNT-OP: -JMP
> > 1 16 >XBCS PLc6 P - - H" IF_REP-JMP" ' EMU_IF_REP-JMP ' NOP COUNT-OP: IF_REP-JMP
> > 2 16 >XBCS c8 P - - H" JMP&LINK" ' EMU_JMP&LINK ' NOP COUNT-OP: JMP&LINK
> > 3 16 >XBCS R P - - H" RET_LINK" ' EMU_RET_LINK ' NOP COUNT-OP: RET_LINK
> > 0 17 >XBCS t tT - - H" TR_RL" ' EMU_TR_RL ' NOP SIMPLE-OP: TR_RL
> > 1 17 >XBCS At tT - - H" TR_RL_DR" ' EMU_TR_RL_DR ' NOP SIMPLE-OP: TR_RL_DR
> > 2 17 >XBCS tD tT - - H" TR_RL_AC" ' EMU_TR_RL_AC ' NOP SIMPLE-OP: TR_RL_AC
> > 3 17 >XBCS tTC tTC - - H" TR_RLC" ' EMU_TR_RLC ' NOP SIMPLE-OP: TR_RLC
> > 0 18 >XBCS tT tT - - H" TR_RR" ' EMU_TR_RR ' NOP SIMPLE-OP: TR_RR
> > 1 18 >XBCS tT tT - - H" TR_RR_DR" ' EMU_TR_RR_DR ' NOP SIMPLE-OP: TR_RR_DR
> > 2 18 >XBCS tT tT - - H" TR_RR_AC" ' EMU_TR_RR_AC ' NOP SIMPLE-OP: TR_RR_AC
> > 3 18 >XBCS tT tTC - - H" TR_RRC" ' EMU_TR_RRC ' NOP SIMPLE-OP: TR_RRC
> > \ code type src dst Dsrc Ddst instr string emultion emulation operation
> > 0 19 >XBCS tT tT - - H" TR_RRB" ' EMU_TR_RRB ' NOP SIMPLE-OP: TR_RRB
> > 1 19 >XBCS tT tT - - H" TR_RRB_DR" ' EMU_TR_RRB_DR ' NOP SIMPLE-OP: TR_RRB_DR
> > 2 19 >XBCS tT tT - - H" TR_RRB_AC" ' EMU_TR_RRB_AC ' NOP SIMPLE-OP: TR_RRB_AC
> > 3 19 >XBCS tT tT - - H" TR_SRB" ' EMU_TR_SRB ' NOP SIMPLE-OP: TR_SRB
> > 0 1A >XBCS D D - - H" DR_RL" ' EMU_DR_RL ' NOP SIMPLE-OP: DR_RL
> > 1 1A >XBCS D D - - H" DR_RL" ' EMU_DR_RL ' NOP SIMPLE-OP: DR_RL
> > 2 1A >XBCS tD D - - H" DR_RL-TR" ' EMU_DR_RL_TR ' NOP SIMPLE-OP: DR_RL-TR
> > 3 1A >XBCS DC DC - - H" DR_RLC" ' EMU_DR_RLC ' NOP SIMPLE-OP: DR_RLC
> > 0 1B >XBCS D D - - H" DR_RR" ' EMU_DR_RR ' NOP SIMPLE-OP: DR_RR
> > 1 1B >XBCS AD D - - H" DR_RR_AC" ' EMU_DR_RR_AC ' NOP SIMPLE-OP: DR_RR_AC
> > 2 1B >XBCS TD D - - H" DR_RR_TR" ' EMU_DR_RR_TR ' NOP SIMPLE-OP: DR_RR_TR
> > 3 1B >XBCS DC DC - - H" DR_RRC" ' EMU_DR_RRC ' NOP SIMPLE-OP: DR_RRC
> > 0 1C >XBCS D D - - H" DR_RRB" ' EMU_DR_RRB ' NOP SIMPLE-OP: DR_RRB
> > 1 1C >XBCS AD D - - H" DR_RRB_AC" ' EMU_DR_RRB_AC ' NOP SIMPLE-OP: DR_RRB_AC
> > 2 1C >XBCS tD D - - H" DR_RRB_TR" ' EMU_DR_RRB_TR ' NOP SIMPLE-OP: DR_RRB_TR
> > 3 1C >XBCS D D - - H" DR_SRB" ' EMU_DR_SRB ' NOP SIMPLE-OP: DR_SRB
> > 2 1D >XBCS tD tTD - - H" TR_DR_RL_AC" ' EMU_TR_DR_RL_AC ' NOP SIMPLE-OP: TR_DR_RL_AC
> > 0 1E >XBCS tTD tTD - - H" TR_DR_RR" ' EMU_TR_DR_RR ' NOP SIMPLE-OP: TR_DR_RR
> > 2 1E >XBCS AtTD tTD - - H" TR_DR_RR_AC" ' EMU_TR_DR_RR_AC ' NOP SIMPLE-OP: TR_DR_RR_AC
> > \ code type src dst Dsrc Ddst instr string emultion emulation operation
> > 2 1F >XBCS tTD tTD - - H" TR_DR_RRB_AC" ' EMU_TR_DR_RRB_AC ' NOP SIMPLE-OP: TR_DR_RRB_AC
> > 0 >MA - M - - H" hold" ' EMU_MA>MA ' NOP JMPL-OP: hold
> > 1 0 >MAPT A M - - H" IP>MA" ' EMU_PM>MA ' NOP JMPL-OP: IP>MA
> > 1 1 >MAPT A M - - H" RP>MA" ' EMU_PM>MA ' NOP JMPL-OP: RP>MA
> > 1 2 >MAPT A M - - H" SP>MA" ' EMU_PM>MA ' NOP JMPL-OP: SP>MA
> > 1 3 >MAPT A M - - H" DP>MA" ' EMU_PM>MA ' NOP JMPL-OP: DP>MA
> > 1 4 >MAPT Sc5 M - - H" MA+C>MA" ' EMU_MA+C>MA ' NOP JMPL-OP: MA+C>MA
> > 1 5 >MAPT Sc5 M - - H" MA-C>MA" ' EMU_MA-C>MA ' NOP JMPL-OP: MA-C>MA
> > 1 6 >MAPT Sc5 M - - H" MA+C>MAu" ' EMU_MA+C>MA ' NOP JMPL-OP: MA+C>MAu
> > 1 7 >MAPT Sc5 M - - H" MA-C>MAu" ' EMU_MA-C>MA ' NOP JMPL-OP: MA-C>MAu
> > 2 >MA M M - - H" AC>MA" ' EMU_AC>MA ' NOP JMPL-OP: AC>MA
> > 3 >MA tTS M - - H" MA-TR>MAu" ' EMU_MA-TR>MA ' NOP JMPL-OP: MA-TR>MAu
> > 4 >MA Mc6 M - - H" AC+C8>MA" ' EMU_AC+C8>MA ' NOP JMPL-OP: AC+C8>MA
> > 5 0 >MAPT A M - - H" IP+2>MAu" ' EMU_PM+2>MA ' NOP JMPL-OP: IP+2>MAu
> > 5 1 >MAPT tT M - - H" TR>MAu" ' EMU_TR>MA ' NOP JMPL-OP: TR>MAu
> > 5 2 >MAPT tT M - - H" TR+2>MAu" ' EMU_TR+2>MA ' NOP JMPL-OP: TR+2>MAu
> > 5 5 >MAPT tT M - - H" TR>MA" ' EMU_TR>MA ' NOP JMPL-OP: TR>MA
> > 5 6 >MAPT tT M - - H" TR+2>MA" ' EMU_TR+2>MA ' NOP JMPL-OP: TR+2>MA
> > 5 7 >MAPT S M - - H" MA+4>MA" ' EMU_MA+4>MA ' NOP JMPL-OP: MA+4>MA
> > \ code type src dst Dsrc Ddst instr string emultion emulation operation
> > 6 0 >MAPT Ac5 M - - H" IP+C>MA" ' EMU_PM+C>MA ' NOP JMPL-OP: IP+C>MA
> > 6 1 >MAPT Ac5 M - - H" RP+C>MA" ' EMU_PM+C>MA ' NOP JMPL-OP: RP+C>MA
> > 6 2 >MAPT Ac5 M - - H" SP+C>MA" ' EMU_PM+C>MA ' NOP JMPL-OP: SP+C>MA
> > 6 3 >MAPT Ac3 M - - H" DP+C5>MA" ' EMU_PM+C5>MA ' NOP JMPL-OP: DP+C5>MA
> > 6 4 >MAPT Ac5 M - - H" IP+C>MAu" ' EMU_PM+C>MA ' NOP JMPL-OP: IP+C>MAu
> > 6 5 >MAPT Ac5 M - - H" RP+C>MAu" ' EMU_PM+C>MA ' NOP JMPL-OP: RP+C>MAu
> > 6 6 >MAPT Ac5 M - - H" SP+C>MAu" ' EMU_PM+C>MA ' NOP JMPL-OP: SP+C>MAu
> > 6 7 >MAPT Ac3 M - - H" DP+C5>MAu" ' EMU_PM+C5>MA ' NOP JMPL-OP: DP+C5>MAu
> > 7 0 >MAPT Ac5 M - - H" IP-C>MA" ' EMU_PM-C>MA ' NOP JMPL-OP: IP-C>MA
> > 7 1 >MAPT Ac5 M - - H" RP-C>MA" ' EMU_PM-C>MA ' NOP JMPL-OP: RP-C>MA
> > 7 2 >MAPT Ac5 M - - H" SP-C>MA" ' EMU_PM-C>MA ' NOP JMPL-OP: SP-C>MA
> > 7 3 >MAPT Ac3 M - - H" DP-C5>MA" ' EMU_PM-C5>MA ' NOP JMPL-OP: DP-C5>MA
> > 7 4 >MAPT Ac5 M - - H" IP-C>MAu" ' EMU_PM-C>MA ' NOP JMPL-OP: IP-C>MAu
> > 7 5 >MAPT Ac5 M - - H" RP-C>MAu" ' EMU_PM-C>MA ' NOP JMPL-OP: RP-C>MAu
> > 7 6 >MAPT Ac5 M - - H" SP-C>MAu" ' EMU_PM-C>MA ' NOP JMPL-OP: SP-C>MAu
> > 7 7 >MAPT Ac3 M - - H" DP-C5>MAu" ' EMU_PM-C5>MA ' NOP JMPL-OP: DP-C5>MAu
> > 1 >AC AM0 FM A - - H" MA>AC" ' EMU_MA>AC ' NOP SIMPLE-OP: MA>AC
> > 2 0 >ACRA AM0 A AC - - H" AC-1>ACC" ' EMU_AC-1>ACC ' NOP SIMPLE-OP: AC-1>ACC
> > 2 1 >ACRA AM0 A AC - - H" AC+1>ACC" ' EMU_AC+1>ACC ' NOP SIMPLE-OP: AC+1>ACC
> > \ code type src dst Dsrc Ddst instr string emultion emulation operation
> > 2 2 >ACRA AM0 A A - - H" AC-1>AC" ' EMU_AC-1>AC ' NOP SIMPLE-OP: AC-1>AC
> > 2 3 >ACRA AM0 A A - - H" AC+1>AC" ' EMU_AC+1>AC ' NOP SIMPLE-OP: AC+1>AC
> > 2 4 >ACRA AM0 AC A - - H" AC+CRY>AC" ' EMU_AC+CRY>AC ' NOP SIMPLE-OP: AC+CRY>AC
> > 2 5 >ACRA AM0 AC A - - H" AC+CRY>AC" ' EMU_AC+CRY>AC ' NOP SIMPLE-OP: AC+CRY>AC
> > 2 7 >ACRA AM0 tT A - - H" TR+1>AC" ' EMU_TR+1>AC ' NOP SIMPLE-OP: TR+1>AC
> > 3 1 >ACRA AM0 - A - - H" 0>AC" ' EMU_0>AC ' NOP SIMPLE-OP: 0>AC
> > 3 2 >ACRA AM0 tT A - - H" TR>AC" ' EMU_TR>AC ' NOP SIMPLE-OP: TR>AC
> > 3 3 >ACRA AM0 D A - - H" DR>AC" ' EMU_DR>AC ' NOP SIMPLE-OP: DR>AC
> > 1 >AC AM1 C A - - H" CRY>AC" ' EMU_CRY>AC ' NOP SIMPLE-OP: CRY>AC
> > 2 >AC AM1 tT A - - H" TR>ACx" ' EMU_TR>AC ' NOP SIMPLE-OP: TR>ACx
> > 3 >AC AM1 D A - - H" DR>ACx" ' EMU_DR>AC ' NOP SIMPLE-OP: DR>ACx
> > 1 >AC AM2 c8 A - - H" C8>AC" ' EMU_C8>AC ' NOP SIMPLE-OP: C8>AC
> > 2 1 >ACRA AM2 AD A - - H" AC_XOR_DR>AC" ' EMU_AC_XOR_DR>AC ' NOP SIMPLE-OP: AC_XOR_DR>AC
> > 2 2 >ACRA AM2 tT A - - H" TR+1>ACx" ' EMU_TR+1>AC ' NOP SIMPLE-OP: TR+1>ACx
> > 2 4 >ACRA AM2 AtT AC - - H" AC-TR>ACC" ' EMU_AC-TR>ACC ' NOP SIMPLE-OP: AC-TR>ACC
> > 2 5 >ACRA AM2 AtT AC - - H" AC+TR>ACC" ' EMU_AC+TR>ACC ' NOP SIMPLE-OP: AC+TR>ACC
> > 2 6 >ACRA AM2 AtT A - - H" AC-TR>AC" ' EMU_AC-TR>AC ' NOP SIMPLE-OP: AC-TR>AC
> > 2 7 >ACRA AM2 AtT A - - H" AC+TR>AC" ' EMU_AC+TR>AC ' NOP SIMPLE-OP: AC+TR>AC
> > 1 0 >ACPT AM3 A A - - H" AC_SL" ' EMU_AC_SL ' NOP SIMPLE-OP: AC_SL
> > \ code type src dst Dsrc Ddst instr string emultion emulation operation
> > 2 0 >ACPT AM3 AC AC - - H" AC_RLC" ' EMU_AC_RLC ' NOP SIMPLE-OP: AC_RLC
> > 1 1 >ACPT AM3 A A - - H" AC_RL" ' EMU_AC_RL ' NOP SIMPLE-OP: AC_RL
> > 2 1 >ACPT AM3 At A - - H" AC_RL_TR" ' EMU_AC_RL_TR ' NOP SIMPLE-OP: AC_RL_TR
> > 3 1 >ACPT AM3 AD A - - H" AC_RL_DR" ' EMU_AC_RL_DR ' NOP SIMPLE-OP: AC_RL_DR
> > 1 2 >ACPT AM3 A A - - H" AC_SR" ' EMU_AC_SR ' NOP SIMPLE-OP: AC_SR
> > 2 2 >ACPT AM3 AC AC - - H" AC_RRC" ' EMU_AC_RRC ' NOP SIMPLE-OP: AC_RRC
> > 1 3 >ACPT AM3 A A - - H" AC_RR" ' EMU_AC_RR ' NOP SIMPLE-OP: AC_RR
> > 2 3 >ACPT AM3 AT A - - H" AC_RR_TR" ' EMU_AC_RR_TR ' NOP SIMPLE-OP: AC_RR_TR
> > 3 3 >ACPT AM3 AD A - - H" AC_RR_DR" ' EMU_AC_RR_DR ' NOP SIMPLE-OP: AC_RR_DR
> > 1 4 >ACPT AM3 A A - - H" AC_SRB" ' EMU_AC_SRB ' NOP SIMPLE-OP: AC_SRB
> > 2 4 >ACPT AM3 A A - - H" AC_RRB" ' EMU_AC_RRB ' NOP SIMPLE-OP: AC_RRB
> > 3 4 >ACPT AM3 AD A - - H" AC_RRB_AC" ' EMU_AC_RRB_AC ' NOP SIMPLE-OP: AC_RRB_AC
> > 1 5 >ACPT AM3 At A - - H" AC_RRB_TR" ' EMU_AC_RRB_TR ' NOP SIMPLE-OP: AC_RRB_TR
> > 2 5 >ACPT AM3 AD A - - H" AC_RRB_DR" ' EMU_AC_RRB_DR ' NOP SIMPLE-OP: AC_RRB_DR
> > 1 6 >ACPT AM3 AtT A - - H" MPY>AC" ' EMU_MPY>AC ' NOP SIMPLE-OP: MPY>AC
> > 2 6 >ACPT AM3 AtTDC A - - H" DIV>AC" ' EMU_DIV>AC ' NOP SIMPLE-OP: DIV>AC
> > 7 5 2 >MAPTR - - - - H" RP-4>MAu" ' EMU_RP-4>MAu ' NOP SIMPLE-OP: RP-4>MAu
> > 5 4 0 >MAPTR - - - - H" TR>MAu" ' EMU_TR>MAu ' NOP SIMPLE-OP: TR>MAu
> > 6 5 2 >MAPTR - - - - H" RP+4>MAu" ' EMU_RP+4>MAu ' NOP SIMPLE-OP: RP+4>MAu
> > \ code type src dst Dsrc Ddst instr string emultion emulation operation
> > 5 4 1 >MAPTR - - - - H" TR+2>MAu" ' EMU_TR+2>MAu ' NOP SIMPLE-OP: TR+2>MAu
> > 6 4 1 >MAPTR - - - - H" IP+2>MAu" ' EMU_IP+2>MAu ' NOP SIMPLE-OP: IP+2>MAu
> > 1 6 1 >MAPTR - - - - H" MA+2>MAu" ' EMU_MA+2>MAu ' NOP SIMPLE-OP: MA+2>MAu
> > 6 6 2 >MAPTR - - - - H" SP+4>MAu" ' EMU_SP+4>MAu ' NOP SIMPLE-OP: SP+4>MAu
> > 6 6 4 >MAPTR - - - - H" SP+8>MAu" ' EMU_SP+8>MAu ' NOP SIMPLE-OP: SP+8>MAu
> > 7 5 4 >MAPTR - - - - H" RP-8>MAu" ' EMU_RP-8>MAu ' NOP SIMPLE-OP: RP-8>MAu
> > 7 6 2 >MAPTR - - - - H" SP-4>MAu" ' EMU_SP-4>MAu ' NOP SIMPLE-OP: SP-4>MAu
> > 7 2 2 >MAPTR - - - - H" SP-4>MA" ' EMU_SP-4>MA ' NOP SIMPLE-OP: SP-4>MA
> > 6 1 2 >MAPTR - - - - H" RP+4>MA" ' EMU_RP+4>MA ' NOP SIMPLE-OP: RP+4>MA
> > 6 5 4 >MAPTR - - - - H" RP+8>MAu" ' EMU_RP+8>MAu ' NOP SIMPLE-OP: RP+8>MAu
> > \ comment - - - - H" (SOS>TR)" ' EMU_(SOS>TR) ' NOP SIMPLE-OP: (SOS>TR)
> > \ comment - - - - H" (PUSH}" ' EMU_(PUSH} ' NOP SIMPLE-OP: (PUSH}
> > \ comment - - - - H" (POP)" ' EMU_(POP) ' NOP SIMPLE-OP: (POP)
> > \ comment - - - - H" (RP@>TR)" ' EMU_(RP@>TR) ' NOP SIMPLE-OP: (RP@>TR)
> > 0 >XB - - - - H" AMD0_d" ' EMU_AMD0 ' EMU_dfr SIMPLE-OP: AMD0_d
> > 1 >XB - - - - H" AMD1_d" ' EMU_AMD1 ' EMU_dfr SIMPLE-OP: AMD1_d
> > 2 >XB - - - - H" AMD2_d" ' EMU_AMD2 ' EMU_dfr SIMPLE-OP: AMD2_d
> > 3 >XB - - - - H" AMD3_d" ' EMU_AMD3 ' EMU_dfr SIMPLE-OP: AMD3_d
> > Done

On Thursday, November 25, 2021 at 12:06:47 AM UTC-7, johnro...@gmail.com wrote:
> \ Op Code File for MFX. Generated by MAKE-OPS v13
>
> \ MODELS\RACE32\RACE32.ops
>
> \ src dst codes J I H G F E D C B A 9 8 7 6 5 4 3 2 1 0
> \ `--.--' `-.-' | | | | | | | | | | |
> \ errors -------------' | | | | | | | | | | | |
> \ constants -----------------' | | | | | | | | | | | - c8_6_5_3
> \ stack ptr mem ---------------------' | | | | | | | | | | - S PM
> \ loop ctr ----------------------------' | | | | | | | | | - L LC
> \ return reg ----------------------------' | | | | | | | | - R RR
> \ prog ctr --------------------------------' | | | | | | | - P PC
> \ mem ads -----------------------------------' | | | | | | - F FLG
> \ flag ----------------------------------------' | | | | | - M MA
> \ carry -----------------------------------------' | | | | - C CRY
> \ data reg ----------------------------------------' | | | - D DR
> \ Treg high (sos) -----------------------------------' | | - T TH
> \ Treg low (sos) --------------------------------------' | - t TL
> \ accumulator (tos) -------------------------------------' - A AC
>
> \ Deferred cmds:
> \ Dsrc Ddst codes J I H G F E D C B A 9 8 7 6 5 4 3 2 1 0
> \ `--.--' `-.-' | | | | | | |
> \ errors -------------' | | | | | | | |
> \ constants -----------------' | | | | | | |
> \ i/o -------------------------------------' | | | | | |
> \ static mem --------------------------------' | | | | |
> \ dynamic mem ---------------------------------' | | | |
> \ reg mem ---------------------------------------' | | |
> \ Treg high (sos) -----------------------------------' | |
> \ Treg low (sos) --------------------------------------' |
> \ accumulator (tos) -------------------------------------'
> ...

I don't know what data-format this file is in, or what software might use it.
I can make a few observations though.
I don't see anything here that indicates that the opcode has five fields and that
each field is an instruction, with all five instructions executing in parallel
(the opcode taking one clock cycle) as was done on the MiniForth.
I don't think that this new RACE processor running on an FPGA is a VLIW processor
as the MiniForth running on the Lattice isp1048 PLD was. I think that it just
executes instructions sequentially like any traditional processor.

Most likely, this MAKEOPS program (version 13, no less) is a replacement for my DUJOUR.4TH
file that I had back in 1994. Tom Hart (impersonating John Hart) is posting the output from
this MAKEOPS program because he knows that the MAKEOPS program was written after
I left and hence is unfamiliar to me. He is posting this for the purpose of proving that I don't know anything
about MFX and/or that MFX has advanced considerably beyond the humble beginnings that I wrote in 1994.

On this thread: https://groups.google.com/g/comp.lang.forth/c/wydQr643gX0/m/3EctGDucAQAJ
I said this:
On Tuesday, November 9, 2021 at 5:16:05 PM UTC-7, Hugh Aguilar wrote:
> Ilya's technique with multi-core loosely-coupled Forth processors is appropriate
> for FPGAs because they have a lot of resources but they lack connectivity.
> The MiniForth was built on the Lattice isp1048 PLD in 1994 that had very little
> resources but a lot of connectivity --- VLIW was appropriate then.
> Most likely, this is the point that Ilya is trying to make --- VLIW is obsolete now.

Many HDL programmers (Verilog or VHDL) have told me that VLIW can't be done
on an FPGA due to a lack of connectivity. The instructions in each field have different
destination registers, but their source registers are the destination registers of other fields.
This means that registers can be written to (by an instruction in one field) and read from
(by an instruction in another field) concurrently, because both instructions are in the same
opcode and all instructions (up to five) in an opcode execute concurrently (one clock cycle
per opcode). This business of reading and writing registers concurrently means that the
registers have to be hardware (not internal memory of the FPGA), and the registers have to
have a lot of connectivity. This is how a PLD worked back in the 1990s. This is not how
an FPGA works nowadays. Back in the 1990s, PLDs had very little resources (no support
for addition/subtraction, no internal memory, etc.), but they had a lot of connectivity.
Now FPGAs have a lot of resources but not much connectivity. This is why loosely-coupled
parallelism (such as done in Ilya's multi-core processors) is a good fit for FPGAs, but
tightly-coupled parallelism (such as done in the MiniForth) is a bad fit for FPGAs.
Tightly-coupled parallelism might still be a good fit for ASICs, but this isn't going to happen
because ASICs have a huge upfront cost, so this isn't done unless there is already a customer
lined up to purchase the chips in a large volume.

The upshot of all of this, is that Testra's RACE processor is obsolete.
It is a single-core processor with a lot of interrupt latency, but the world has moved on to
multi-core processors (most of which don't use interrupts at all, because each core is dedicated
to pushing data in or out of some I/O port). I'm still proud of having written MFX, but this doesn't
necessarily mean that I think VLIW is a good idea nowadays --- our opportunity was in 1995,
but we blew it --- that opportunity was gone by the turn of the century, which is two decades past now.

My expertise is in VLIW --- that makes me obsolete --- nobody cares about VLIW nowadays.

On Sunday, November 28, 2021 at 6:05:27 PM UTC-4, Hugh Aguilar wrote:
>
> I don't know what data-format this file is in, or what software might use it.
> I can make a few observations though.
> I don't see anything here that indicates that the opcode has five fields and that
> each field is an instruction, with all five instructions executing in parallel
> (the opcode taking one clock cycle) as was done on the MiniForth.
> I don't think that this new RACE processor running on an FPGA is a VLIW processor
> as the MiniForth running on the Lattice isp1048 PLD was. I think that it just
> executes instructions sequentially like any traditional processor.
>
> Most likely, this MAKEOPS program (version 13, no less) is a replacement for my DUJOUR.4TH
> file that I had back in 1994. Tom Hart (impersonating John Hart) is posting the output from
> this MAKEOPS program because he knows that the MAKEOPS program was written after
> I left and hence is unfamiliar to me. He is posting this for the purpose of proving that I don't know anything
> about MFX and/or that MFX has advanced considerably beyond the humble beginnings that I wrote in 1994.
>
> On this thread: https://groups.google.com/g/comp.lang.forth/c/wydQr643gX0/m/3EctGDucAQAJ
> I said this:
> On Tuesday, November 9, 2021 at 5:16:05 PM UTC-7, Hugh Aguilar wrote:
> > Ilya's technique with multi-core loosely-coupled Forth processors is appropriate
> > for FPGAs because they have a lot of resources but they lack connectivity.

This is pure BS. FPGAs are known for being mostly interconnectivity, otherwise known as routing. In the early days when the FPGA makers understood this and the designers (who were mostly new to this technology) would complain about the issues, the sales people would say they sell you the routing and give you the logic for free meaning the chip is mostly routing.

> > The MiniForth was built on the Lattice isp1048 PLD in 1994 that had very little
> > resources but a lot of connectivity --- VLIW was appropriate then.
> > Most likely, this is the point that Ilya is trying to make --- VLIW is obsolete now.
>
> Many HDL programmers (Verilog or VHDL) have told me that VLIW can't be done
> on an FPGA due to a lack of connectivity.

More BS. Anyone who tells you that doesn't know FPGAs and I seriously doubt any designer who knows FPGAs and understands VLIW would say such a thing.

> The instructions in each field have different
> destination registers, but their source registers are the destination registers of other fields.
> This means that registers can be written to (by an instruction in one field) and read from
> (by an instruction in another field) concurrently, because both instructions are in the same
> opcode and all instructions (up to five) in an opcode execute concurrently (one clock cycle
> per opcode). This business of reading and writing registers concurrently means that the
> registers have to be hardware (not internal memory of the FPGA), and the registers have to
> have a lot of connectivity.

Again, more BS. The registers in an FPGA can be read by many destinations and written on the same clock cycle. When you say "internal memory" do you mean the block RAM (dedicated blocks of memory of 8kbits or larger) or do you include the memory that in many brands of FPGA are the configuration storage for the LUT of which there are MANY! These small memories can be 16x1, 16x2, 32x1 and many other configurations depending on the device. This is what is typically used for register file storage requiring a LUT for each separately addressed read bit. If you need to address different registers from many destinations you can just use FPGA registers as the register files just like external chips, except without the horrendous numbers of I/O pins.

> This is how a PLD worked back in the 1990s. This is not how
> an FPGA works nowadays. Back in the 1990s, PLDs had very little resources (no support
> for addition/subtraction, no internal memory, etc.), but they had a lot of connectivity.
> Now FPGAs have a lot of resources but not much connectivity. This is why loosely-coupled
> parallelism (such as done in Ilya's multi-core processors) is a good fit for FPGAs, but
> tightly-coupled parallelism (such as done in the MiniForth) is a bad fit for FPGAs.
> Tightly-coupled parallelism might still be a good fit for ASICs, but this isn't going to happen
> because ASICs have a huge upfront cost, so this isn't done unless there is already a customer
> lined up to purchase the chips in a large volume.

There is nothing done in the MiniForth processor you have discussed that could not be done completely in an FPGA. Nothing. It would be faster, cheaper and potentially handle a lot more.

> The upshot of all of this, is that Testra's RACE processor is obsolete.
> It is a single-core processor with a lot of interrupt latency, but the world has moved on to
> multi-core processors (most of which don't use interrupts at all, because each core is dedicated
> to pushing data in or out of some I/O port). I'm still proud of having written MFX, but this doesn't
> necessarily mean that I think VLIW is a good idea nowadays --- our opportunity was in 1995,
> but we blew it --- that opportunity was gone by the turn of the century, which is two decades past now.
>
> My expertise is in VLIW --- that makes me obsolete --- nobody cares about VLIW nowadays.

What you call VLIW, if I recall correctly, is what others call microcode. That is also a very good match with FPGAs as they can provide instruction memory of any width you might want. FPGAs are the perfect target for a VLIW.. The issue is most people aren't interested in the programming hassles for the limited improvement in processing capabilities. They are able to get the job done with simpler tools and processors.

If anyone identifies an application that would profitably be addressed with a VLIW architecture, I would be happy to oblige with a board and an FPGA design to suit. But these days I don't want to play. I want to make money.

VLIW can be very fast, but you need to be skilled to program it. Hugh sounds like he was once that skilled having written a compiler that targeted a VLIW instruction set, but what are the chances of him ever being lucid enough to repeat the task?

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

On Monday, November 29, 2021 at 9:41:48 AM UTC-7, gnuarm.del...@gmail.com wrote:
> On Sunday, November 28, 2021 at 6:05:27 PM UTC-4, Hugh Aguilar wrote:
> > Many HDL programmers (Verilog or VHDL) have told me that VLIW can't be done
> > on an FPGA due to a lack of connectivity.
> More BS. Anyone who tells you that doesn't know FPGAs and I seriously doubt any designer who knows FPGAs
> and understands VLIW would say such a thing.

You have never implemented a VLIW processor.
When you say that you "understand VLIW" you mean that you read a magazine article about it.

> What you call VLIW, if I recall correctly, is what others call microcode.

No. What I call VLIW is what other call VLIW.
This is a processor with multiple instructions per opcode (in distinct fields).
All of the instructions in the opcode execute concurrently, with one clock cycle per opcode.

> If anyone identifies an application that would profitably be addressed with a VLIW architecture, I would be happy to oblige
> with a board and an FPGA design to suit. But these days I don't want to play. I want to make money.

Rick Collins is a scam artist.
He has zero experience with implementing VLIW processors, but he expects people
to pay him to do this job that he has never done before and knows nothing about.

If he tries to implement a VLIW processor in an FPGA, it won't rout.
He says that it will rout. How does he know that??? He has never tried the experiment.
He is substituting wishful-thinking for actual experience --- a typical sales-clown.

It might be possible to use a large expensive FPGA for a small simple VLIW processor, but that is inefficient.
VLIW is a mismatch for FPGA chips' advantages and disadvantages.

> VLIW can be very fast, but you need to be skilled to program it.

Rick Collins is incompetent as a programmer.
Here is a thread in January of 2021 in which he struggles to figure out a way to convert a number
into a hexadecimal string. A search through comp.lang.forth shows that he has been struggling
with this problem since 2015 (or, at least, he has been public about his struggle since 2015).
https://groups.google.com/g/comp.lang.forth/c/vkv3OO4hMTo/m/UsuFK_dWDgAJ
Note that he attacks me, saying that my code doesn't work --- but it does work --- this is easy!

Most likely, Rick Collins' plan in regard to getting a customer who wants a VLIW processor,
is to make the processor execute the instructions in the opcode sequentially in some predetermined order.
So, other than the fact that several instructions get packed into each opcode, reducing the code-memory
usage, this is still just a traditional processor. The BUGS18 is an example of this; it has three 6-bit fields
in each 18-bit opcode (64 Forth words), and the fields execute sequentially. This is not VLIW.
The customer will likely not figure out that he has been scammed. LOL

On Thursday, December 2, 2021 at 7:31:32 PM UTC-5, Hugh Aguilar wrote:
> On Monday, November 29, 2021 at 9:41:48 AM UTC-7, gnuarm.del...@gmail.com wrote:
> > On Sunday, November 28, 2021 at 6:05:27 PM UTC-4, Hugh Aguilar wrote:
> > > Many HDL programmers (Verilog or VHDL) have told me that VLIW can't be done
> > > on an FPGA due to a lack of connectivity.
> > More BS. Anyone who tells you that doesn't know FPGAs and I seriously doubt any designer who knows FPGAs
> > and understands VLIW would say such a thing.
> You have never implemented a VLIW processor.
> When you say that you "understand VLIW" you mean that you read a magazine article about it.

No, I mean I worked on an attached array processor that used a VLIW, which in those days was called "microcode". To avoid the time of decode, the control points in the machine were each controlled by individual bits in the 100+ bit instruction word.

The machine actually had two programmable units, one to control the computations in the ALU, register file and cache memory and another to move data between main memory and cache. The ALU had five compute units, two adders, two multipliers and a divide/square root unit (I think the divide square root unit usurped a multiplier when used). Each could operate independently in parallel with separate instruction fields in the "opcode" on data fetched from the register file with 8 reads and four writes operating in parallel.. That seems to fit your definition of VLIW.

I don't think VLIW was a thing at the time this was designed. Wikipedia talks about the term being coined in the 1980's when this array processor was already being shipped.

> > What you call VLIW, if I recall correctly, is what others call microcode.
> No. What I call VLIW is what other call VLIW.
> This is a processor with multiple instructions per opcode (in distinct fields).

That is the way TI designed the TMS6xxx line of processors, with eight 32 bit instructions per "opcode".

> All of the instructions in the opcode execute concurrently, with one clock cycle per opcode.

Yup, that's the way the array processor worked.

> > If anyone identifies an application that would profitably be addressed with a VLIW architecture, I would be happy to oblige
> > with a board and an FPGA design to suit. But these days I don't want to play. I want to make money.
> Rick Collins is a scam artist.
> He has zero experience with implementing VLIW processors, but he expects people
> to pay him to do this job that he has never done before and knows nothing about.

All my life I have done things I've never done before and knew little about until I did them. That's because I'm capable of learning. It's an amazing skill. It has served me well.

> If he tries to implement a VLIW processor in an FPGA, it won't rout.
> He says that it will rout. How does he know that??? He has never tried the experiment.
> He is substituting wishful-thinking for actual experience --- a typical sales-clown.

You mean I have done many, many FPGA designs and actually know something about them while you literally know nothing other than what you may have read in a magazine article or been misinformed about by someone who knows no more than you.

These days there is very little you can't do in an FPGA. The idea of a design not routing being a limitation means you don't understand FPGAs. If it doesn't route, use a larger FPGA with more routing! Anyone who knows the basics of FPGAs understands that.

> It might be possible to use a large expensive FPGA for a small simple VLIW processor, but that is inefficient.
> VLIW is a mismatch for FPGA chips' advantages and disadvantages.

If it's a small, simple design it will route in a small FPGA. But you don't even understand connectivity in electronic designs, so I don't expect you to understand that.

> > VLIW can be very fast, but you need to be skilled to program it.
> Rick Collins is incompetent as a programmer.
> Here is a thread in January of 2021 in which he struggles to figure out a way to convert a number
> into a hexadecimal string. A search through comp.lang.forth shows that he has been struggling
> with this problem since 2015 (or, at least, he has been public about his struggle since 2015).
> https://groups.google.com/g/comp.lang.forth/c/vkv3OO4hMTo/m/UsuFK_dWDgAJ
> Note that he attacks me, saying that my code doesn't work --- but it does work --- this is easy!

You are funny. I seem to recall a programming problem that you had completely wrong, I provided a correct answer to and you refused to acknowledge it.. Everyone in the group told you that you were wrong and I was right, but you just couldn't accept that. I suppose now you are going to melt down and explode like a TV robot confronted with a self contradiction.

> Most likely, Rick Collins' plan in regard to getting a customer who wants a VLIW processor,
> is to make the processor execute the instructions in the opcode sequentially in some predetermined order.

Why are you so dense? It's easy in an FPGA. Just have multiple compute units and assign a separate instruction field for each one. This is not rocket science.

> So, other than the fact that several instructions get packed into each opcode, reducing the code-memory
> usage, this is still just a traditional processor. The BUGS18 is an example of this; it has three 6-bit fields
> in each 18-bit opcode (64 Forth words), and the fields execute sequentially. This is not VLIW.
> The customer will likely not figure out that he has been scammed. LOL

Wow! Do you ever do anything useful? Or are you just so lost in the ozone you are incapable of doing useful work at all these days?

I also was peripherally connected with a Navy project to design a common platform signal processor that could have been implemented on the array processor I worked with. What they wanted was a common programming environment that was data directed and graphical. But for who knows what reason they insisted on designing hardware to run it on. The hardware needed to be tailored to the various application environments which ended up killing the hardware project and the software project went down with it too. The architecture of the hardware was vaguely similar to the array processor I worked on, but was more closely tied to the software architecture. This was actually a liability because it had to be custom at a time when commercial hardware was starting to lead anything military by leaps and bounds. Too expensive, too slow and too late - the project died. Had they stuck with data flow in the software design process, compiling to a VLIW array processor, they could have used commercial hardware that got faster and faster every year. They do this a lot now.
Oh well...

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209

On Friday, December 3, 2021 at 12:34:59 AM UTC-7, gnuarm.del...@gmail.com wrote:
> On Thursday, December 2, 2021 at 7:31:32 PM UTC-5, Hugh Aguilar wrote:
> > > VLIW can be very fast, but you need to be skilled to program it.
> > Rick Collins is incompetent as a programmer.
> > Here is a thread in January of 2021 in which he struggles to figure out a way to convert a number
> > into a hexadecimal string. A search through comp.lang.forth shows that he has been struggling
> > with this problem since 2015 (or, at least, he has been public about his struggle since 2015).
> > https://groups.google.com/g/comp.lang.forth/c/vkv3OO4hMTo/m/UsuFK_dWDgAJ
> > Note that he attacks me, saying that my code doesn't work --- but it does work --- this is easy!
> You are funny. I seem to recall a programming problem that you had completely wrong,
> I provided a correct answer to and you refused to acknowledge it. Everyone in the group told you that you were wrong
> and I was right, but you just couldn't accept that. I suppose now you are going to melt down and explode
> like a TV robot confronted with a self contradiction.

This is from that thread:

On Thursday, January 21, 2021 at 2:18:20 AM UTC-7, gnuarm.del...@gmail.com wrote:
> On Thursday, January 21, 2021 at 3:15:35 AM UTC-5, dxforth wrote:
> > On 21/01/2021 00:24, NN wrote:
> > > On Wednesday, 20 January 2021 at 08:43:21 UTC, Alexander Wegel wrote:
> > >> Hugh Aguilar <hughag...@gmail.com> wrote:
> > >>
> > >> > It is not really that I (Hugh Aguilar, slammed by Bernd Payson for being
> > >> > unwise) don't know how to use a flag as a mask in logic-arithmetic --- it
> > >> > is just that I don't want to --- this is my own code (written in ANS-Forth,
> > >> > and one of the previous versions mentioned above as not being acceptable):
> > >> >
> > >> > : indexed-char \ index adr cnt -- char
> > >> > \ the string will be used as an array of chars
> > >> > rover 0< abort" *** INDEXED-CHAR given a negative index ***"
> > >> > rover <= abort" *** INDEXED-CHAR given an index too large ***"
> > >> > + c@ ;
> > >> >
> > >> > : hexit>char \ [0,15] -- char
> > >> > s" 0123456789ABCDEF" indexed-char ;
> > >> >
> > >> > This is an example of how I relate to Forth differently from most ANS-Forth
> > >> > and Forth-200x enthusiasts
> > >> It's inefficient, doing a lot of superfluous checking and juggling. As
> > >> Hugh Aguilar would say: "you screwed it up".
> > >
> > >
> > > Therein lies the problem ....
> > >
> > > the question should really be is the function giving the correct output in the
> > > environment its being used ?
> > >
> > > What you might consider inefficient for your use , might be perfectable for
> > > someone else.
> > >
> > > The programmer can always come back at a later stage and rewrite it should
> > > the need arise.
> > >
> > > So was the function correct ?
> > >
> > I can imagine an ascii to binary routine potentially requiring checks,
> > but not the reverse.
> Sure, the way this routine is written anything outside the range of 0-15 will cause an access outside the declared array resulting in an ambiguous condition. Either flag the error or the bits of interest should be masked off first to preclude the error. As written the calling routine would need to do the masking.
>
> --
>
> Rick C.

Here is the thread from 2015 in which Rick Collins first began struggling with
the problem of converting numbers into hex chars. In this thread Elizabeth Rather
praises as having "proper documentation" making it "readable and maintainable"
whereas she slams my code as being "unacceptable."
Note that Bernd Paysan is slamming me for not being wise and not being capable
of learning about masks and logical operations. This insult was prior to
me getting into this thread --- I had not yet entered the thread because
it seemed too trivial to bother with --- Bernd Paysan just insults me gratuitously
as a way of reminding everybody that he is supporting Elizabeth Rather and hence
has her full support. This is why he is on the Forth-200x committee!

We had this example of using a flag as a mask was given by Rick Collins
(modified slightly here to make it ANS-Forth):

: >CHAR ( [0,15] -- char )
DUP 9 > 7 AND + [CHAR] 0 + ;

A Forther (Hans Bezemer) complained that this code is bad style,
and the Forth-200x committee-member Bernd Payson defended it:

On Sunday, May 24, 2015 at 5:21:05 PM UTC-7, Bernd Paysan wrote:
> Hans Bezemer wrote:
> > ...True, it
> > is a clever piece of programming, but in our opinion it is bad
> > style. Why? Because you are using a flag as a bitmask, which is a
> > completely different datatype. Although there is no such thing as
> > “data typing” in Forth, this way of programming makes it
> > difficult to understand and maintain a program, which the
> > ANS-Forth standard acknowledges:
>
> Honestly, this is only a problem if you don't know that idiom. A lot of
> people don't know that you can use masks and logical operations, so they
> will find that operation strange.
> ...
> Therefore, I would reiterate what I told Hugh some times: If you don't know
> something, it's *not* the fault of the person who uses and knows that thing.
> It's entirely your fault, and if you want to be a wise person, you'd rather
> learn it that complain.
>
> IMHO the whole datatype based thinking about cells in Forth is ill-advised.
> First, and foremost, a cell is a bit pattern, and if you add and subtract
> it, it's a mod 2^n ring. You can use that to some degrees as integer, but
> it's not an integer. It's a cell.
>
> --
> Bernd Paysan
> "If you want it done right, you have to do it yourself"

Elizabeth Rather responded:

> Thank, you, Bernd, well-said.
>
> Cheers,
> Elizabeth

A little later we had this:

On Tuesday, May 26, 2015 at 11:37:37 AM UTC-7, Elizabeth D. Rather wrote:
> On 5/26/15 8:15 AM, rickman wrote:
> > On 5/26/2015 1:20 PM, WJ wrote:
> >> That code is unreadable and unmaintainable. It's very hard
> >> to figure out how it accomplishes its task. I would not
> >> pay a programmer to produce code like that.
> >>
> >> This is somewhat more understandable:
> >>
> >> : >char
> >> dup 9 > if [char] A 10 - else [char] 0 then
> >> + ;
> >
> > If you have any reason to look at the definition of >char then I can't
> > see how you would not understand how it works. Perhaps this would be a
> > better definition...
> >
> > \ Convert n to ASCII char
> > : >CHAR ( n -- char ) DUP 9 > 7 AND + ASCII 0 + ;
> >
> > Lol, saying it is unreadable and unmaintainable is a bit of a stretch. I
> > think that exact code has been read and understood as well as maintained
> > for many years now. I am pretty sure I have seen something similar to
> > it way back when I was learning assembly language. I think it took me
> > two minutes to see what it was doing.
>
> Indeed, proper documentation as in rickman's version above is essential
> to readable & maintainable code. Neither of the previous versions is
> acceptable, although I find the shorter code quite clear (and, as
> rickman notes, it's been around for many years). I would have preferred
> [CHAR] instead of ASCII, however, as it's Standard.
>
> Cheers,
> Elizabeth

On 4/12/2021 16:07, Hugh Aguilar wrote:
> ...
> We had this example of using a flag as a mask was given by Rick Collins
> (modified slightly here to make it ANS-Forth):
>
> : >CHAR ( [0,15] -- char )
> DUP 9 > 7 AND + [CHAR] 0 + ;
>
> A Forther (Hans Bezemer) complained that this code is bad style,
> and the Forth-200x committee-member Bernd Payson defended it

As would I given it was classical and the suggested alternatives
weren't unequivocally better (unlike my READ-LINE spec :)

: >CHAR ( [0,15] -- char )
DUP 9 > 7 AND + [CHAR] 0 + ;

see >char
>CHAR
( 004F0890 83FB09 ) CMP EBX, 09
( 004F0893 0F9FC2 ) SETNLE/G DL
( 004F0896 F6DA ) NEG DL
( 004F0898 0FBED2 ) MOVSX EDX, DL
( 004F089B 83E207 ) AND EDX, 07
( 004F089E 03DA ) ADD EBX, EDX
( 004F08A0 83C330 ) ADD EBX, 30
( 004F08A3 C3 ) NEXT,
( 20 bytes, 8 instructions )

: hexit>char \ [0,15] -- char
s" 0123456789ABCDEF" drop + c@ ;

see hexit>char
HEXIT>CHAR
( 004F08D0 E8AB19F2FF ) CALL 00412280 (S") "0123456789ABCDEF"
( 004F08E8 8B5D00 ) MOV EBX, [EBP]
( 004F08EB 035D04 ) ADD EBX, [EBP+04]
( 004F08EE 8D6D08 ) LEA EBP, [EBP+08]
( 004F08F1 E806A0F1FF ) CALL 0040A8FC C@
( 004F08F6 C3 ) NEXT,
( 39 bytes, 6 instructions )

On Saturday, December 4, 2021 at 9:25:45 AM UTC+3, dxforth wrote:
> On 4/12/2021 16:07, Hugh Aguilar wrote:
> > ...
> > We had this example of using a flag as a mask was given by Rick Collins
> > (modified slightly here to make it ANS-Forth):
> >
> > : >CHAR ( [0,15] -- char )
> > DUP 9 > 7 AND + [CHAR] 0 + ;
> >
> > A Forther (Hans Bezemer) complained that this code is bad style,
> > and the Forth-200x committee-member Bernd Payson defended it
> As would I given it was classical and the suggested alternatives
> weren't unequivocally better (unlike my READ-LINE spec :)
> : >CHAR ( [0,15] -- char )
> DUP 9 > 7 AND + [CHAR] 0 + ;
> see >char
> >CHAR
> ( 004F0890 83FB09 ) CMP EBX, 09
> ( 004F0893 0F9FC2 ) SETNLE/G DL
> ( 004F0896 F6DA ) NEG DL
> ( 004F0898 0FBED2 ) MOVSX EDX, DL
> ( 004F089B 83E207 ) AND EDX, 07
> ( 004F089E 03DA ) ADD EBX, EDX
> ( 004F08A0 83C330 ) ADD EBX, 30
> ( 004F08A3 C3 ) NEXT,
> ( 20 bytes, 8 instructions )
> : hexit>char \ [0,15] -- char
> s" 0123456789ABCDEF" drop + c@ ;
>
> see hexit>char
> HEXIT>CHAR
> ( 004F08D0 E8AB19F2FF ) CALL 00412280 (S") "0123456789ABCDEF"
> ( 004F08E8 8B5D00 ) MOV EBX, [EBP]
> ( 004F08EB 035D04 ) ADD EBX, [EBP+04]
> ( 004F08EE 8D6D08 ) LEA EBP, [EBP+08]
> ( 004F08F1 E806A0F1FF ) CALL 0040A8FC C@
> ( 004F08F6 C3 ) NEXT,
> ( 39 bytes, 6 instructions )

Well, at least first variant doesn't segfault on invalid input...

Btw, lxf generates much better assembler:

: T1 DUP 9 > 7 AND + [CHAR] 0 + ;
: T2 S" 0123456789ABCDEF" DROP + C@ ;

see t1
8691F10 804FBE4 20 88C8000 5 normal T1

804FBE4 83FB09 cmp ebx , # 9h
804FBE7 0F9FC0 setg al
804FBEA 0FBEC0 movsx eax , al
804FBED F7D8 neg eax
804FBEF 83E007 and eax , # 7h
804FBF2 01C3 add ebx , eax
804FBF4 83C330 add ebx , # 30h
804FBF7 C3 ret near
ok
see t2
8691F24 804FBF8 10 88C8000 5 normal T2

804FBF8 81C3F89C3808 add ebx , # 8389CF8h
804FBFE 0FB61B movzx ebx , byte ptr [ebx]
804FC01 C3 ret near
ok

On 4/12/2021 18:06, Nickolay Kolchin wrote:
> ...
> Well, at least first variant doesn't segfault on invalid input...

The second included a test but was removed for comparison.

>
> Btw, lxf generates much better assembler:

Still longer factoring in the string. OTOH should now be faster than
the others. On VFX (in-lined string) it ran 10x slower than first
variant, so no gain at all.

On Saturday, December 4, 2021 at 12:07:07 AM UTC-5, Hugh Aguilar wrote:
> On Friday, December 3, 2021 at 12:34:59 AM UTC-7, gnuarm.del...@gmail.com wrote:
> > On Thursday, December 2, 2021 at 7:31:32 PM UTC-5, Hugh Aguilar wrote:
> > > > VLIW can be very fast, but you need to be skilled to program it.
> > > Rick Collins is incompetent as a programmer.
> > > Here is a thread in January of 2021 in which he struggles to figure out a way to convert a number
> > > into a hexadecimal string. A search through comp.lang.forth shows that he has been struggling
> > > with this problem since 2015 (or, at least, he has been public about his struggle since 2015).
> > > https://groups.google.com/g/comp.lang.forth/c/vkv3OO4hMTo/m/UsuFK_dWDgAJ
> > > Note that he attacks me, saying that my code doesn't work --- but it does work --- this is easy!
> > You are funny. I seem to recall a programming problem that you had completely wrong,
> > I provided a correct answer to and you refused to acknowledge it. Everyone in the group told you that you were wrong
> > and I was right, but you just couldn't accept that. I suppose now you are going to melt down and explode
> > like a TV robot confronted with a self contradiction.
> This is from that thread:

<<< pointless example snipped >>>

I don't think that was the example I was thinking about. It was something different that you probably put out of your mind because you literally attacked my version and posted your own which didn't actually work over the full range of valid input. I don't recall the function, it may have been a log conversion.

I'm sure you will not be able to rest until you find it which is not my goal. I simply wish to point out that while you love to criticize others for their imperfect code making them "incompetent" programmers, you have fails of your own. So does that make YOU an incompetent programmer? No. It makes you human. Why don't you accept that we are all human and treat the rest of us as you would like to be treated?

Meanwhile, we seem to have stopped talking about VLIW being a good match for FPGAs.

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

On Saturday, December 4, 2021 at 8:06:47 AM UTC+1, Nickolay Kolchin wrote:
> On Saturday, December 4, 2021 at 9:25:45 AM UTC+3, dxforth wrote:
[..]
> Well, at least first variant doesn't segfault on invalid input...
>
> Btw, lxf generates much better assembler:
>
> : T1 DUP 9 > 7 AND + [CHAR] 0 + ;
> : T2 S" 0123456789ABCDEF" DROP + C@ ;
>
> see t1
> 8691F10 804FBE4 20 88C8000 5 normal T1
>
> 804FBE4 83FB09 cmp ebx , # 9h
> 804FBE7 0F9FC0 setg al
> 804FBEA 0FBEC0 movsx eax , al
> 804FBED F7D8 neg eax
> 804FBEF 83E007 and eax , # 7h
> 804FBF2 01C3 add ebx , eax
> 804FBF4 83C330 add ebx , # 30h
> 804FBF7 C3 ret near
> ok
> see t2
> 8691F24 804FBF8 10 88C8000 5 normal T2
>
> 804FBF8 81C3F89C3808 add ebx , # 8389CF8h
> 804FBFE 0FB61B movzx ebx , byte ptr [ebx]
> 804FC01 C3 ret near
> ok

iForth64:
FORTH> : T1 DUP 9 > 7 AND + [CHAR] 0 + ; ok
FORTH> : T2 S" 0123456789ABCDEF" DROP + C@ ; ok
FORTH> ' t1 idis
$0133D700 : T1
$0133D70A pop rbx
$0133D70B cmp rbx, 9 b#
$0133D70F setg cl
$0133D713 movzx rcx, cl
$0133D717 neg rcx
$0133D71A and rcx, 7 b#
$0133D71E lea rbx, [rbx rcx*1 #48 +] qword
$0133D723 push rbx
$0133D724 ; ok
FORTH> see t2
Flags: ANSI
$0133D780 : T2
$0133D78A pop rbx
$0133D78B movzx rdi, [rbx $0132CF88 +] byte
$0133D793 push rdi
$0133D794 ;

-marcel

On Sunday, December 5, 2021 at 10:46:37 AM UTC+3, Marcel Hendrix wrote:
> On Saturday, December 4, 2021 at 8:06:47 AM UTC+1, Nickolay Kolchin wrote:
> > On Saturday, December 4, 2021 at 9:25:45 AM UTC+3, dxforth wrote:
> [..]
> > Well, at least first variant doesn't segfault on invalid input...
> >
> > Btw, lxf generates much better assembler:
> >
> > : T1 DUP 9 > 7 AND + [CHAR] 0 + ;
> > : T2 S" 0123456789ABCDEF" DROP + C@ ;
> >
> > see t1
> > 8691F10 804FBE4 20 88C8000 5 normal T1
> >
> > 804FBE4 83FB09 cmp ebx , # 9h
> > 804FBE7 0F9FC0 setg al
> > 804FBEA 0FBEC0 movsx eax , al
> > 804FBED F7D8 neg eax
> > 804FBEF 83E007 and eax , # 7h
> > 804FBF2 01C3 add ebx , eax
> > 804FBF4 83C330 add ebx , # 30h
> > 804FBF7 C3 ret near
> > ok
> > see t2
> > 8691F24 804FBF8 10 88C8000 5 normal T2
> >
> > 804FBF8 81C3F89C3808 add ebx , # 8389CF8h
> > 804FBFE 0FB61B movzx ebx , byte ptr [ebx]
> > 804FC01 C3 ret near
> > ok
> iForth64:
> FORTH> : T1 DUP 9 > 7 AND + [CHAR] 0 + ; ok
> FORTH> : T2 S" 0123456789ABCDEF" DROP + C@ ; ok
> FORTH> ' t1 idis
> $0133D700 : T1
> $0133D70A pop rbx
> $0133D70B cmp rbx, 9 b#
> $0133D70F setg cl
> $0133D713 movzx rcx, cl
> $0133D717 neg rcx
> $0133D71A and rcx, 7 b#
> $0133D71E lea rbx, [rbx rcx*1 #48 +] qword
> $0133D723 push rbx
> $0133D724 ; ok
> FORTH> see t2
> Flags: ANSI
> $0133D780 : T2
> $0133D78A pop rbx
> $0133D78B movzx rdi, [rbx $0132CF88 +] byte
> $0133D793 push rdi
> $0133D794 ;
>

You are the only one that was able to combine BX operations in single LEA!

On Friday, December 3, 2021 at 12:34:59 AM UTC-7, gnuarm.del...@gmail.com wrote:
> On Thursday, December 2, 2021 at 7:31:32 PM UTC-5, Hugh Aguilar wrote:
> > On Monday, November 29, 2021 at 9:41:48 AM UTC-7, gnuarm.del...@gmail.com wrote:
> > > If anyone identifies an application that would profitably be addressed with a VLIW architecture,
> > > I would be happy to oblige
> > > with a board and an FPGA design to suit. But these days I don't want to play. I want to make money.
> > Rick Collins is a scam artist.
> > He has zero experience with implementing VLIW processors, but he expects people
> > to pay him to do this job that he has never done before and knows nothing about.
> All my life I have done things I've never done before and knew little about until I did them.
> That's because I'm capable of learning. It's an amazing skill. It has served me well.

This is the year 2021 and Rick Collin's "amazing skill" of learning has not yet been put to use
to allow him to learn how integer addition works in computers:

On Saturday, December 11, 2021 at 2:29:36 PM UTC-7, gnuarm.del...@gmail.com wrote:
> On Saturday, December 11, 2021 at 3:51:59 PM UTC-5, Hugh Aguilar wrote:
> > I considered MFX assembly-language to be fun. :-)
> > My idea of fun doesn't necessarily correspond to most people's idea of fun.
> > The only addressing-mode supported was inherent --- none of the instructions had operands.
> > There was no way to change the control-flow except with the NXT instruction.
> > There was no instruction to do 16-bit integer addition --- this required a pretty complicated function.
> > This was a "serious hardware project" though --- it was used in laser-etching machines.
> > The days of being able to build your own processor that competes with mainstream processors
> > is past. :-( In 1994, the competition was using an MC68000 programmed in C, but the
> > MiniForth built on a Lattice isp1048 PLD and an 8032 was higher performing and less expensive.
> > Nowadays pretty much everybody uses the ARM Cortex for motion-control, programmed in C.
> > Somebody like Nickolay Kolchin would get hired for that --- I would not --- my experience is too
> > esoteric and obsolete, plus Tom Hart refuses to admit that I wrote MFX anyway.

> You say it doesn't have "16-bit integer addition", so what does it have? How is addition done?

Rick Collins wants customers to pay him to implement a VLIW processor,
but he has no experience with implementing a VLIW processor. Here he is expecting
me to explain to him how 16-bit integer addition is implemented in software.

I didn't know how 16-bit integer addition could be done either, back in 1994.
Steve Brault wrote the + primitive. This is the only general-purpose code in MFX
that I didn't write. I would have figured it out though. I just had a lot of other
programming to do, so I hadn't gotten around to delving into that yet.
That was in 1994 --- now I have seen how 16-bit integer addition is implemented
so now I know --- I'm not going to teach Rick Collins how processors work internally.

On Sunday, December 12, 2021 at 2:42:32 PM UTC-5, Hugh Aguilar wrote:
> On Friday, December 3, 2021 at 12:34:59 AM UTC-7, gnuarm.del...@gmail.com wrote:
> > On Thursday, December 2, 2021 at 7:31:32 PM UTC-5, Hugh Aguilar wrote:
> > > On Monday, November 29, 2021 at 9:41:48 AM UTC-7, gnuarm.del...@gmail..com wrote:
> > > > If anyone identifies an application that would profitably be addressed with a VLIW architecture,
> > > > I would be happy to oblige
> > > > with a board and an FPGA design to suit. But these days I don't want to play. I want to make money.
> > > Rick Collins is a scam artist.
> > > He has zero experience with implementing VLIW processors, but he expects people
> > > to pay him to do this job that he has never done before and knows nothing about.
> > All my life I have done things I've never done before and knew little about until I did them.
> > That's because I'm capable of learning. It's an amazing skill. It has served me well.
> This is the year 2021 and Rick Collin's "amazing skill" of learning has not yet been put to use
> to allow him to learn how integer addition works in computers:
>
> On Saturday, December 11, 2021 at 2:29:36 PM UTC-7, gnuarm.del...@gmail.com wrote:
> > On Saturday, December 11, 2021 at 3:51:59 PM UTC-5, Hugh Aguilar wrote:
> > > I considered MFX assembly-language to be fun. :-)
> > > My idea of fun doesn't necessarily correspond to most people's idea of fun.
> > > The only addressing-mode supported was inherent --- none of the instructions had operands.
> > > There was no way to change the control-flow except with the NXT instruction.
> > > There was no instruction to do 16-bit integer addition --- this required a pretty complicated function.
> > > This was a "serious hardware project" though --- it was used in laser-etching machines.
> > > The days of being able to build your own processor that competes with mainstream processors
> > > is past. :-( In 1994, the competition was using an MC68000 programmed in C, but the
> > > MiniForth built on a Lattice isp1048 PLD and an 8032 was higher performing and less expensive.
> > > Nowadays pretty much everybody uses the ARM Cortex for motion-control, programmed in C.
> > > Somebody like Nickolay Kolchin would get hired for that --- I would not --- my experience is too
> > > esoteric and obsolete, plus Tom Hart refuses to admit that I wrote MFX anyway.
>
> > You say it doesn't have "16-bit integer addition", so what does it have? How is addition done?
>
> Rick Collins wants customers to pay him to implement a VLIW processor,
> but he has no experience with implementing a VLIW processor. Here he is expecting
> me to explain to him how 16-bit integer addition is implemented in software.
>
> I didn't know how 16-bit integer addition could be done either, back in 1994.
> Steve Brault wrote the + primitive. This is the only general-purpose code in MFX
> that I didn't write. I would have figured it out though. I just had a lot of other
> programming to do, so I hadn't gotten around to delving into that yet.
> That was in 1994 --- now I have seen how 16-bit integer addition is implemented
> so now I know --- I'm not going to teach Rick Collins how processors work internally.

Ok, so Hugh is being cryptic as usual. What exactly does the machine do other than a 16 bit add? I can only assume that you are talking about the machine being somehow limited and since I know nothing of this arcane architecture from another century (or nearly so at least) I have no idea what that limitation is. Does it have an 8 bit add? Does it have a 1 bit add? Is it necessary to implement an addition through logic operations? That would certainly be tedious.

I don't expect a real answer from you as you are too far gone to actually discuss anything. But on the off chance you might tell us what you are talking about, I'm willing to listen. I would add that I certainly don't need you to teach me anything about implementing arithmetic operations in hardware. I seem to recall you were a bit confused about the fast carry chain implementation in FPGAs. Certainly you know nothing of routing in FPGAs.

So why not put down your boxing gloves and discuss the add function you are being so cryptic about. What is this limitation you are talking about. What instructions does the CPU have to implement adds with that is not a 16 bit integer add? Or are you talking about the hardware logic?

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

On Sunday, December 12, 2021 at 6:25:12 PM UTC-7, gnuarm.del...@gmail.com wrote:
> On Sunday, December 12, 2021 at 2:42:32 PM UTC-5, Hugh Aguilar wrote:
> > On Friday, December 3, 2021 at 12:34:59 AM UTC-7, gnuarm.del...@gmail.com wrote:
> > > On Thursday, December 2, 2021 at 7:31:32 PM UTC-5, Hugh Aguilar wrote:
> > > > On Monday, November 29, 2021 at 9:41:48 AM UTC-7, gnuarm.del...@gmail.com wrote:
> > > > > If anyone identifies an application that would profitably be addressed with a VLIW architecture,
> > > > > I would be happy to oblige
> > > > > with a board and an FPGA design to suit. But these days I don't want to play. I want to make money.
> > > > Rick Collins is a scam artist.
> > > > He has zero experience with implementing VLIW processors, but he expects people
> > > > to pay him to do this job that he has never done before and knows nothing about.
> > > All my life I have done things I've never done before and knew little about until I did them.
> > > That's because I'm capable of learning. It's an amazing skill. It has served me well.
> > This is the year 2021 and Rick Collin's "amazing skill" of learning has not yet been put to use
> > to allow him to learn how integer addition works in computers:
> >
> > On Saturday, December 11, 2021 at 2:29:36 PM UTC-7, gnuarm.del...@gmail.com wrote:
> > > On Saturday, December 11, 2021 at 3:51:59 PM UTC-5, Hugh Aguilar wrote:
> > > > I considered MFX assembly-language to be fun. :-)
> > > > My idea of fun doesn't necessarily correspond to most people's idea of fun.
> > > > The only addressing-mode supported was inherent --- none of the instructions had operands.
> > > > There was no way to change the control-flow except with the NXT instruction.
> > > > There was no instruction to do 16-bit integer addition --- this required a pretty complicated function.
> > > > This was a "serious hardware project" though --- it was used in laser-etching machines.
> > > > The days of being able to build your own processor that competes with mainstream processors
> > > > is past. :-( In 1994, the competition was using an MC68000 programmed in C, but the
> > > > MiniForth built on a Lattice isp1048 PLD and an 8032 was higher performing and less expensive.
> > > > Nowadays pretty much everybody uses the ARM Cortex for motion-control, programmed in C.
> > > > Somebody like Nickolay Kolchin would get hired for that --- I would not --- my experience is too
> > > > esoteric and obsolete, plus Tom Hart refuses to admit that I wrote MFX anyway.
> >
> > > You say it doesn't have "16-bit integer addition", so what does it have? How is addition done?
> >
> > Rick Collins wants customers to pay him to implement a VLIW processor,
> > but he has no experience with implementing a VLIW processor. Here he is expecting
> > me to explain to him how 16-bit integer addition is implemented in software.
> >
> > I didn't know how 16-bit integer addition could be done either, back in 1994.
> > Steve Brault wrote the + primitive. This is the only general-purpose code in MFX
> > that I didn't write. I would have figured it out though. I just had a lot of other
> > programming to do, so I hadn't gotten around to delving into that yet.
> > That was in 1994 --- now I have seen how 16-bit integer addition is implemented
> > so now I know --- I'm not going to teach Rick Collins how processors work internally.
> Ok, so Hugh is being cryptic as usual. What exactly does the machine do other than a 16 bit add?
> I can only assume that you are talking about the machine being somehow limited and since
> I know nothing of this arcane architecture from another century (or nearly so at least)
> I have no idea what that limitation is. Does it have an 8 bit add? Does it have a 1 bit add?
> Is it necessary to implement an addition through logic operations? That would certainly be tedious.

You don't know how addition works. You're a fake expert --- you don't really know anything.

> I don't expect a real answer from you as you are too far gone to actually discuss anything.

I'm tired of you endlessly flinging these insults at me
I want you to just piss off --- shining a spotlight on your gross ignorance of basic
concepts such as how integer addition works will hopefully just make you go away.

> But on the off chance you might tell us what you are talking about, I'm willing to listen.
> I would add that I certainly don't need you to teach me anything about implementing arithmetic...

I'm not willing to teach you basic concepts such as how integer addition works.
PISS OFF! FAKE EXPERT!

On Monday, December 13, 2021 at 9:32:04 PM UTC-4, Hugh Aguilar wrote:
> On Sunday, December 12, 2021 at 6:25:12 PM UTC-7, gnuarm.del...@gmail.com wrote:
> > On Sunday, December 12, 2021 at 2:42:32 PM UTC-5, Hugh Aguilar wrote:
> > > On Friday, December 3, 2021 at 12:34:59 AM UTC-7, gnuarm.del...@gmail..com wrote:
> > > > On Thursday, December 2, 2021 at 7:31:32 PM UTC-5, Hugh Aguilar wrote:
> > > > > On Monday, November 29, 2021 at 9:41:48 AM UTC-7, gnuarm.del...@gmail.com wrote:
> > > > > > If anyone identifies an application that would profitably be addressed with a VLIW architecture,
> > > > > > I would be happy to oblige
> > > > > > with a board and an FPGA design to suit. But these days I don't want to play. I want to make money.
> > > > > Rick Collins is a scam artist.
> > > > > He has zero experience with implementing VLIW processors, but he expects people
> > > > > to pay him to do this job that he has never done before and knows nothing about.
> > > > All my life I have done things I've never done before and knew little about until I did them.
> > > > That's because I'm capable of learning. It's an amazing skill. It has served me well.
> > > This is the year 2021 and Rick Collin's "amazing skill" of learning has not yet been put to use
> > > to allow him to learn how integer addition works in computers:
> > >
> > > On Saturday, December 11, 2021 at 2:29:36 PM UTC-7, gnuarm.del...@gmail.com wrote:
> > > > On Saturday, December 11, 2021 at 3:51:59 PM UTC-5, Hugh Aguilar wrote:
> > > > > I considered MFX assembly-language to be fun. :-)
> > > > > My idea of fun doesn't necessarily correspond to most people's idea of fun.
> > > > > The only addressing-mode supported was inherent --- none of the instructions had operands.
> > > > > There was no way to change the control-flow except with the NXT instruction.
> > > > > There was no instruction to do 16-bit integer addition --- this required a pretty complicated function.
> > > > > This was a "serious hardware project" though --- it was used in laser-etching machines.
> > > > > The days of being able to build your own processor that competes with mainstream processors
> > > > > is past. :-( In 1994, the competition was using an MC68000 programmed in C, but the
> > > > > MiniForth built on a Lattice isp1048 PLD and an 8032 was higher performing and less expensive.
> > > > > Nowadays pretty much everybody uses the ARM Cortex for motion-control, programmed in C.
> > > > > Somebody like Nickolay Kolchin would get hired for that --- I would not --- my experience is too
> > > > > esoteric and obsolete, plus Tom Hart refuses to admit that I wrote MFX anyway.
> > >
> > > > You say it doesn't have "16-bit integer addition", so what does it have? How is addition done?
> > >
> > > Rick Collins wants customers to pay him to implement a VLIW processor,
> > > but he has no experience with implementing a VLIW processor. Here he is expecting
> > > me to explain to him how 16-bit integer addition is implemented in software.
> > >
> > > I didn't know how 16-bit integer addition could be done either, back in 1994.
> > > Steve Brault wrote the + primitive. This is the only general-purpose code in MFX
> > > that I didn't write. I would have figured it out though. I just had a lot of other
> > > programming to do, so I hadn't gotten around to delving into that yet..
> > > That was in 1994 --- now I have seen how 16-bit integer addition is implemented
> > > so now I know --- I'm not going to teach Rick Collins how processors work internally.
> > Ok, so Hugh is being cryptic as usual. What exactly does the machine do other than a 16 bit add?
> > I can only assume that you are talking about the machine being somehow limited and since
> > I know nothing of this arcane architecture from another century (or nearly so at least)
> > I have no idea what that limitation is. Does it have an 8 bit add? Does it have a 1 bit add?
> > Is it necessary to implement an addition through logic operations? That would certainly be tedious.
> You don't know how addition works. You're a fake expert --- you don't really know anything.

I think it is you who is the fake. You claim I know nothing and yet are unwilling to show that by demonstration. You probably don't even understand what I wrote.

> > I don't expect a real answer from you as you are too far gone to actually discuss anything.
> I'm tired of you endlessly flinging these insults at me

That's not as much an insult as a simple statement of fact. As I said, I don't expect anything from you other than a tirade and you have responded exactly in that way. Silly of me to act as if there was any chance of anything different. Maybe I'm the one who is insane because I would appear to have some expectation you might engage in a technical discussion rather than a rant.

> I want you to just piss off --- shining a spotlight on your gross ignorance of basic
> concepts such as how integer addition works will hopefully just make you go away.

So far you've only shown the spotlight on your own ignorance. You don't even know what the MFX addition primitive is.

> > But on the off chance you might tell us what you are talking about, I'm willing to listen.
> > I would add that I certainly don't need you to teach me anything about implementing arithmetic...
>
> I'm not willing to teach you basic concepts such as how integer addition works.
> PISS OFF! FAKE EXPERT!

Sure, I'll stop when you do.

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209

<clip>
> > > >
> > > > > You say it doesn't have "16-bit integer addition", so what does it have? How is addition done?
> > > >
<clip>
The PLD for our first reconfigurable processor didn't support arithmetic functions, so addition was done in
two steps. First, the 16bit numbers were XORed, then the carry was propagated 4bits at a time, so it took
5 cycles to do an add. We moved the design to the FPGA without changing the architecture but added a
second set of registers for a virtual core that ran an i/o process that used to run on an 8032.
The new design is 32bit, and looking back it would have been better to have moved directly to it, but
I had't finished our Forth FPGA design tools at that time. Translating Forth to logic for the PLD was easy
but the method didn't work well for FPGA's. The PLD logic cells had 18 inputs, LUTs have 4 or 5.

On Wednesday, December 15, 2021 at 8:57:46 PM UTC-4, johnro...@gmail.com wrote:
> <clip>
> > > > >
> > > > > > You say it doesn't have "16-bit integer addition", so what does it have? How is addition done?
> > > > >
> <clip>
> The PLD for our first reconfigurable processor didn't support arithmetic functions, so addition was done in
> two steps. First, the 16bit numbers were XORed, then the carry was propagated 4bits at a time, so it took
> 5 cycles to do an add. We moved the design to the FPGA without changing the architecture but added a
> second set of registers for a virtual core that ran an i/o process that used to run on an 8032.
> The new design is 32bit, and looking back it would have been better to have moved directly to it, but
> I had't finished our Forth FPGA design tools at that time. Translating Forth to logic for the PLD was easy
> but the method didn't work well for FPGA's. The PLD logic cells had 18 inputs, LUTs have 4 or 5.

XORing the two addends will give the sum of each bit position of addends, but how exactly did you calculate the 4 bits of carry? Was there a special instruction for that? The individual bit position carry is just an AND of the two input bits, but gets a bit more complex if including the carry in as does the SUM which is the XOR of all three inputs at that point.

BTW, who are you? In Google groups you only show up as " johnro...@gmail.com"...

--

Rick C.

++ Get 1,000 miles of free Supercharging
++ Tesla referral code - https://ts.la/richard11209

On Wednesday, December 15, 2021 at 10:31:31 PM UTC-7, gnuarm.del...@gmail.com wrote:
> On Wednesday, December 15, 2021 at 8:57:46 PM UTC-4, johnro...@gmail.com wrote:
> > <clip>
> > > > > >
> > > > > > > You say it doesn't have "16-bit integer addition", so what does it have? How is addition done?
> > > > > >
> > <clip>
> > The PLD for our first reconfigurable processor didn't support arithmetic functions, so addition was done in
> > two steps. First, the 16bit numbers were XORed, then the carry was propagated 4bits at a time, so it took
> > 5 cycles to do an add. We moved the design to the FPGA without changing the architecture but added a
> > second set of registers for a virtual core that ran an i/o process that used to run on an 8032.
> > The new design is 32bit, and looking back it would have been better to have moved directly to it, but
> > I had't finished our Forth FPGA design tools at that time. Translating Forth to logic for the PLD was easy
> > but the method didn't work well for FPGA's. The PLD logic cells had 18 inputs, LUTs have 4 or 5.

> XORing the two addends will give the sum of each bit position of addends, but how exactly did you calculate the 4 bits of carry? Was there a special instruction for that? The individual bit position carry is just an AND of the two input bits, but gets a bit more complex if including the carry in as does the SUM which is the XOR of all three inputs at that point.
>
AC TR XOR -> AX
01 ]: AC TR XOR >>O AC ;[ MAP \ AC_XOR_TR>AC

10 ]: AC AX TR - CRY- 10000 * OR 10 U/ >>O AC ;[ MAP \ AC-TR-CRY>>AC
11 ]: AC AX TR + CRY+ 10000 * OR 10 U/ >>O AC ;[ MAP \ AC+TR+CRY>>AC
12 ]: AC AC CRY- 10000 * OR 10 U/ >>O AC ;[ MAP \ AC-CRY>>AC
13 ]: AC AC CRY+ 10000 * OR 10 U/ >>O AC ;[ MAP \ AC+CRY>>AC

John H

On Thursday, December 16, 2021 at 2:05:44 AM UTC-4, johnro...@gmail.com wrote:
> On Wednesday, December 15, 2021 at 10:31:31 PM UTC-7, gnuarm.del...@gmail..com wrote:
> > On Wednesday, December 15, 2021 at 8:57:46 PM UTC-4, johnro...@gmail.com wrote:
> > > <clip>
> > > > > > >
> > > > > > > > You say it doesn't have "16-bit integer addition", so what does it have? How is addition done?
> > > > > > >
> > > <clip>
> > > The PLD for our first reconfigurable processor didn't support arithmetic functions, so addition was done in
> > > two steps. First, the 16bit numbers were XORed, then the carry was propagated 4bits at a time, so it took
> > > 5 cycles to do an add. We moved the design to the FPGA without changing the architecture but added a
> > > second set of registers for a virtual core that ran an i/o process that used to run on an 8032.
> > > The new design is 32bit, and looking back it would have been better to have moved directly to it, but
> > > I had't finished our Forth FPGA design tools at that time. Translating Forth to logic for the PLD was easy
> > > but the method didn't work well for FPGA's. The PLD logic cells had 18 inputs, LUTs have 4 or 5.
>
> > XORing the two addends will give the sum of each bit position of addends, but how exactly did you calculate the 4 bits of carry? Was there a special instruction for that? The individual bit position carry is just an AND of the two input bits, but gets a bit more complex if including the carry in as does the SUM which is the XOR of all three inputs at that point.
> >
> AC TR XOR -> AX
>
> 01 ]: AC TR XOR >>O AC ;[ MAP \ AC_XOR_TR>AC
>
> 10 ]: AC AX TR - CRY- 10000 * OR 10 U/ >>O AC ;[ MAP \ AC-TR-CRY>>AC
> 11 ]: AC AX TR + CRY+ 10000 * OR 10 U/ >>O AC ;[ MAP \ AC+TR+CRY>>AC
> 12 ]: AC AC CRY- 10000 * OR 10 U/ >>O AC ;[ MAP \ AC-CRY>>AC
> 13 ]: AC AC CRY+ 10000 * OR 10 U/ >>O AC ;[ MAP \ AC+CRY>>AC

Hmmm... I don't know your terminology, but I assume the two addends start in AC and TR which are then XORed with the result in AX. I don't follow the remainder of this at all. Is each line an instruction? I assume the numbers are all binary, so 10000 * is a shift left by 4 bits? Should I assume the shift is performed on the result of the previous operation?

What exactly happens with AC AX TR - CRY-? Is TR a destination? What does CRY- do? If you don't have an addition or subtraction operator, what do '+' and '-' do?

Ah, AC AX TR is simply loading operands onto the stack and - operates on the top two? 10000 * operates on the ToS. I assume the OR operates on the top two elements on the stack and 10 U/ right shifts ToS by one bit. Not following what >>0 AC does.

--

Rick C.

--- Get 1,000 miles of free Supercharging
--- Tesla referral code - https://ts.la/richard11209

On Wednesday, December 15, 2021 at 5:57:46 PM UTC-7, johnro...@gmail.com wrote:
> Translating Forth to logic for the PLD was easy...

I can't imagine John Hart saying that his software to program the Lattice isp1048 PLD
was "easy" --- I recall that he was very proud of this accomplishment --- I also recall
that getting the MiniForth to rout was difficult and required some luck (routing is an
intractable problem, so luck is a major factor in whether or not a design works).
I think this is Tom Hart impersonating John Hart --- I recall that Tom Hart got a thrill
out of belittling other people's accomplishments.

After I wrote MFX, Tom Hart told me that the only reason why I was employed
at Testra was that I worked for cheap. He was essentially say that writing MFX
was easy enough to have been done by anybody, so the only criteria was getting it
done as cheaply as possible, and he would never give me a raise. After I quit and used
Testra as a job reference, he said that I had accomplished nothing and that
I was not eligible for rehire --- this was because his only criteria for an employee
was loyalty. I have no doubt that at the same time he was telling the customers
that writing MFX was easy given his awesome programming ability.

Tom Hart is a fool. He thinks that when he belittles other people's accomplishments
he is impressing the spectators with his technical superiority that he can look down
at any programming task and declare it to be easy. This is foolish because he is declaring
Testra accomplishments to have been easy, so the potential customers think:
"If this product was trivial to build, then why should we pay for it? If it was so easy
that anybody could do it, then it should be given away for free --- we are only willing
to pay for professional work that was not easy to do and hence costs a lot of money."

Tom Hart is an arrogant jack-ass --- this is why Testra was never able to keep any
employees and hence was never able to grow beyond being a small rinky-dink operation.
I am not to blame for Testra remaining small for a quarter of a century --- I wrote MFX,
when nobody else at Testra knew how to do out-of-ordering of instructions which is
required for a VLIW processor --- if I had not gotten MFX to work, Testra would have
likely gone out of business in 1995, but nobody at Testra thanked me for pulling
their bacon out of the fire and instead I got only scorn for being a mere programmer.