Commercial in confidence. Trade secret.
All Intellectual Property Rights reserved. 27-12-21.

My apologies for not posting this at Christmas.

I confess, I don't really know FPGA, except that you are using look up table entries to represent results tied to some custom circuitry for performance and some fabric stitching (is that right?). I've been meaning to dive into learning it for years, but spiralling health got in the way.

But, at times, I wonder how you could make something like FPGA, but at home, or better, in factory. Decades back, I had an idea to do a simple printable read only memory, using a grid of lines and pass the current through at intersections or block it for 1's and zeros. This could be made with semi permanent writable memory techniques too. Now, I wonder if I should use my casting idea, from 41+ years ago, where you send out the address, everybody hears it, and the right one sends back the value it has. So, suitable for look up tables, but the same could be used for circuits.

But, what about using optical effects to do this storage array. I've spent some time thinking about different ways to do this, but on a simple level, there is a way I was looking at years ago for a simplistic optical circuit.. It maybe of little performance (in the classical computing sense), but is meant for simplified low cost situations. But, if combined it with the casting idea, it makes for a simple architecture.

Now. Let's say, that you use the above grid with casting. Your circuit board has panels of the grid stuck on it, or the board surface is printed. Now, with the optical, the board itself can be made to contain the circuit elements, printed in optically. Casting functions by flashing coded light through the board and the element responds at the speed of light. Now, when I model the light return time on these sorts of things, it doesn't seem impressive. Say the path is 10 cm return, and you are using a simple interference pattern for values, that takes roughly 3 billionth a second plus. Which is ok speed. But, the value has to be processed, so it is the fastest speed possible. Most processing is predetermined input and outputs. Even if the inputs are of random events that turn up, the processing is not, so the outcome for each is determined Even if the dataset is dynamic, sub parts of the processing of the new dataset remain deterministic, so sub parts repeatedly used maybe reused. If the math itself has to fundamentally change, then that further breaks down performance, requiring a reload of newly generated values for the new maths. But, deciding such maths are a conditional test problem, of the ranges, types and flow of data, so able to be accommodated and worked out. Even without a new range of values for new maths, there is still performance to be had, as maths still breaks down to basic structures. Such as + - x / etc.

I've actually spent significant time in the past, trying to design and model such things, and had advanced designs well past what I am talking about here. But, here, we see a minor pulse of light returns a signal, and we are still using low energy, and I could probably harvest most of the unused photons, further reducing the energy.

There are a number of designs I am avoiding here, that I had to really struggle with, due to not being able to see the deep overall picture easily, because of health issue. This design bit here, however, is adequate to get far, but strays a bit close to some other technological designs I am reserving. When you look at it, you are getting close to 3D stacked storage arrays of values, which can be printed as part of the circuit board. They are the map, the circuit board substrate of vales, is the map.

3D printing

Though 3D printing methodology lacks the resolution of a top of the line fab these days, we could look at dealing with micron and sub micron ranges in the visible light spectrum, and interference patterns thereof, some day. A 10cm by 5cm by 2mm circuit board, offers 100,000 x 50,000 X 2,000 opportunities of spots for values. That's 10 trillion options for values, without overlap. I've looked into 3D printing methods for chemical (chemically constructing a item/feature) to molecular printing, to atomic level etc printing. Volumetric storage materials have long since been developed. This is close to do it at home territory, once worked out.

If the return path is 1cm, then that's 30 billionths of a second and 200 billion potential spots for values in a square (the circle being lower). The good thing is, that values closer to the the broadcast have a closer path, returning values faster. Within 1mm, you are looking at 300 billionth of a second (up to 100 times faster than a high end mobile core, except it seldom works that way, but on the other hand many units of work can also be replaced by look up values, making it hard to compare the two types of system, but hopefully with this averaging faster than 100 times). A 1mm cube is 1 billion values. Why do we need conventional silicon chips? This is related to work I was thinking of nearly two decades back, if not longer.

In a potential future high end fabrication process, the storage density of a single bit approaches 1/10 of a nanometre, but that is likely to be in a single layer, or reduced layers. Optically, that gets tricky, hence the reduction of density of layers along at least one axis. In the meantime, optical techniques are now at 5 nm. In reality, pattern techniques, are still limited by the packing density of atoms, as the basic minimum unit that can represent a bit with some stability. However, there are modifications to atoms to increase data density, but as far as sensing those optically, those things are beyond my immediate knowledge, but I have a vague idea, they might be possible. However, I'm currently thinking of ways to align all sub atomic spins, so there is increased density again. However, the degree of stability of all these techniques, will undoubtedly limit the size that is usable, unless one can force stability, which I am thinking about.

I reserve all intellectual property (IP) rights 27-12-21. Which, any honest person knows, means they can't patent original work revealed so far, without my, or other original originator's, agreement, not that it implies they can't use it, if it's not patented (though, it also does not imply a licence of use before the period to apply for patent expires). My worry is IP thieves, taking and locking up base (potentially public) IP, stopping use by originators, and independent development and use, without agreement with originators. Here, it becomes free once the last period to apply for right, and patent, expires. In the meantime, it doesn't stop people from developing and patenting further IP beyond this base (You will notice, I have left a number of base mechanisms to achieve effects out. Allowing competitive development of those mechanisms, beyond what is stated here). I'm aware that some will have issue with this interpretation. But, a big sponsor, and control, makes things happen faster.

You notice, manufacturers are no longer talking about advanced things here.

On Sunday, December 26, 2021 at 11:12:39 AM UTC-5, Wayne morellini wrote:
> Commercial in confidence. Trade secret.
> All Intellectual Property Rights reserved. 27-12-21.

Lol! This has got to be one of the funniest things I've ever seen posted to this group!!!

> My apologies for not posting this at Christmas.
>
> I confess, I don't really know FPGA, except that you are using look up table entries to represent results tied to some custom circuitry for performance and some fabric stitching (is that right?). I've been meaning to dive into learning it for years, but spiralling health got in the way.

What??? What you call lookup tables are otherwise referred to as RAM. Yes, FPGAs typically use a small bit of RAM to implement lookup tables for logic. If you read an introductory text on logic design they will almost certainly teach Karnaugh maps which are tables specifying the output for each possible combination of inputs. This can be directly implemented in hardware by a small block of RAM.

I'm not sure what you are saying about custom circuitry, but the logic that is implemented is specified by the designer.

> But, at times, I wonder how you could make something like FPGA, but at home, or better, in factory. Decades back, I had an idea to do a simple printable read only memory, using a grid of lines and pass the current through at intersections or block it for 1's and zeros. This could be made with semi permanent writable memory techniques too. Now, I wonder if I should use my casting idea, from 41+ years ago, where you send out the address, everybody hears it, and the right one sends back the value it has. So, suitable for look up tables, but the same could be used for circuits.

But that's not a circuit. That's an architecture. A circuit would have the details required to implement it. Your idea might be useful if implemented on a large network (and is the basis for many such networks), but would not be useful in a chip to implement RAM. RAM typically consists of a selection matrix with 1 of N lines activated to read out every bit in the row. This M bit wide word then is fed into multiplexers to select the 1 of M bits to be presented at the output. This can be done in parallel to enable reading many bits at a time.

The details of this depends on the type of RAM and the specific implementation.

> But, what about using optical effects to do this storage array. I've spent some time thinking about different ways to do this, but on a simple level, there is a way I was looking at years ago for a simplistic optical circuit. It maybe of little performance (in the classical computing sense), but is meant for simplified low cost situations. But, if combined it with the casting idea, it makes for a simple architecture.

There are many people working on optical memory. I'm not sure about the casting idea. The wiring alone would make the casting idea inefficient and very large.

> Now. Let's say, that you use the above grid with casting. Your circuit board has panels of the grid stuck on it, or the board surface is printed. Now, with the optical, the board itself can be made to contain the circuit elements, printed in optically. Casting functions by flashing coded light through the board and the element responds at the speed of light. Now, when I model the light return time on these sorts of things, it doesn't seem impressive. Say the path is 10 cm return, and you are using a simple interference pattern for values, that takes roughly 3 billionth a second plus. Which is ok speed. But, the value has to be processed, so it is the fastest speed possible. Most processing is predetermined input and outputs. Even if the inputs are of random events that turn up, the processing is not, so the outcome for each is determined Even if the dataset is dynamic, sub parts of the processing of the new dataset remain deterministic, so sub parts repeatedly used maybe reused. If the math itself has to fundamentally change, then that further breaks down performance, requiring a reload of newly generated values for the new maths. But, deciding such maths are a conditional test problem, of the ranges, types and flow of data, so able to be accommodated and worked out. Even without a new range of values for new maths, there is still performance to be had, as maths still breaks down to basic structures. Such as + - x / etc.

I think you should work on this. Take some classes in logic design, semiconductor processing, system design. Then you can build this device for us and the greater Forth world.

> I've actually spent significant time in the past, trying to design and model such things, and had advanced designs well past what I am talking about here. But, here, we see a minor pulse of light returns a signal, and we are still using low energy, and I could probably harvest most of the unused photons, further reducing the energy.
>
> There are a number of designs I am avoiding here, that I had to really struggle with, due to not being able to see the deep overall picture easily, because of health issue. This design bit here, however, is adequate to get far, but strays a bit close to some other technological designs I am reserving. When you look at it, you are getting close to 3D stacked storage arrays of values, which can be printed as part of the circuit board. They are the map, the circuit board substrate of vales, is the map.
>
>
> 3D printing
>
> Though 3D printing methodology lacks the resolution of a top of the line fab these days, we could look at dealing with micron and sub micron ranges in the visible light spectrum, and interference patterns thereof, some day. A 10cm by 5cm by 2mm circuit board, offers 100,000 x 50,000 X 2,000 opportunities of spots for values. That's 10 trillion options for values, without overlap. I've looked into 3D printing methods for chemical (chemically constructing a item/feature) to molecular printing, to atomic level etc printing. Volumetric storage materials have long since been developed. This is close to do it at home territory, once worked out.
>
> If the return path is 1cm, then that's 30 billionths of a second and 200 billion potential spots for values in a square (the circle being lower). The good thing is, that values closer to the the broadcast have a closer path, returning values faster. Within 1mm, you are looking at 300 billionth of a second (up to 100 times faster than a high end mobile core, except it seldom works that way, but on the other hand many units of work can also be replaced by look up values, making it hard to compare the two types of system, but hopefully with this averaging faster than 100 times). A 1mm cube is 1 billion values. Why do we need conventional silicon chips? This is related to work I was thinking of nearly two decades back, if not longer.
>
> In a potential future high end fabrication process, the storage density of a single bit approaches 1/10 of a nanometre, but that is likely to be in a single layer, or reduced layers. Optically, that gets tricky, hence the reduction of density of layers along at least one axis. In the meantime, optical techniques are now at 5 nm. In reality, pattern techniques, are still limited by the packing density of atoms, as the basic minimum unit that can represent a bit with some stability. However, there are modifications to atoms to increase data density, but as far as sensing those optically, those things are beyond my immediate knowledge, but I have a vague idea, they might be possible. However, I'm currently thinking of ways to align all sub atomic spins, so there is increased density again. However, the degree of stability of all these techniques, will undoubtedly limit the size that is usable, unless one can force stability, which I am thinking about.
>
> I reserve all intellectual property (IP) rights 27-12-21. Which, any honest person knows, means they can't patent original work revealed so far, without my, or other original originator's, agreement, not that it implies they can't use it, if it's not patented (though, it also does not imply a licence of use before the period to apply for patent expires). My worry is IP thieves, taking and locking up base (potentially public) IP, stopping use by originators, and independent development and use, without agreement with originators. Here, it becomes free once the last period to apply for right, and patent, expires. In the meantime, it doesn't stop people from developing and patenting further IP beyond this base (You will notice, I have left a number of base mechanisms to achieve effects out. Allowing competitive development of those mechanisms, beyond what is stated here). I'm aware that some will have issue with this interpretation. But, a big sponsor, and control, makes things happen faster.
>
> You notice, manufacturers are no longer talking about advanced things here.

When did manufacturers talk about advanced things *here*?

BTW, you can't publicly publish ideas and also reserve "all" IP rights. You can copyright what you've written, but that is of no value in protecting the ideas. The only issue with patent is that now the information is in the public domain, but that doesn't mean you can now patent any of this. You essentially have no say in the matter at this point.

Doesn't matter. Nothing I read was patentable anyway.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

On Mon, 27 Dec 2021, 04:32 Rick C, <gnuarm.deletethisbit@gmail.com> wrote:
On Sunday, December 26, 2021 at 11:12:39 AM UTC-5, Wayne morellini wrote:
> Commercial in confidence. Trade secret.
> All Intellectual Property Rights reserved. 27-12-21.

Lol! This has got to be one of the funniest things I've ever seen posted to this group!!

Rick, proverbial neurotic like laughing and illogically going on at a logic level lower than the discussion, while also agreeing, (by the looks of it) but missing the point, is not a good first reply. Can it for a while, and give other people a chance to post please!

> My apologies for not posting this at Christmas.
>
> I confess, I don't really know FPGA, except that you are using look up table entries to represent results tied to some custom circuitry for performance and some fabric stitching (is that right?). I've been meaning to dive into learning it for years, but spiralling health got in the way.

What??? What you call lookup tables are otherwise referred to as RAM. Yes, FPGAs typically use a small bit of RAM to implement lookup tables for logic. If you read an introductory text on logic design they will almost certainly teach Karnaugh maps which are tables specifying the output for each possible combination of inputs. This can be directly implemented in hardware by a small block of RAM.

You mean, what I just described! Thank you..

I'm not sure what you are saying about custom circuitry, but the logic that is implemented is specified by the designer.

You already know this. ASIC features and ports to reduce the power consumption and Increase the performance of commonly used functions, as normal FPGA technology was slow and every hungry producing hear issues. Stop trying to show up to degrade.

> But, at times, I wonder how you could make something like FPGA, but at home, or better, in factory. Decades back, I had an idea to do a simple printable read only memory, using a grid of lines and pass the current through at intersections or block it for 1's and zeros. This could be made with semi permanent writable memory techniques too. Now, I wonder if I should use my casting idea, from 41+ years ago, where you send out the address, everybody hears it, and the right one sends back the value it has. So, suitable for look up tables, but the same could be used for circuits.

But that's not a circuit. That's an architecture. A circuit would have the details required to implement it. Your idea might be useful if implemented on a large network (and is the basis for many such networks), but would not be useful in a chip to implement RAM. RAM typically consists of a selection matrix with 1 of N lines activated to read out every bit in the row. This M bit wide word then is fed into multiplexers to select the 1 of M bits to be presented at the output. This can be done in parallel to enable reading many bits at a time.

Thanks for agreeing again. Good to know we both seem to know these basic principles of dram that don't need to be actually repeated. However, I wasn't describing details of a circuit, but only said circuits could be implemented with it.

The details of this depends on the type of RAM and the specific implementation.

We are talking about simple arrays of ROM, with the possibility of making that into a re-writable memory. So, you sort of got that right, but you get so much wrong about the details of thought sometimes, it gets hard to keep up. I've got the kid next door constantly repeating the same part of a song on his hifi, so it's hard to read and hear something like that.

> But, what about using optical effects to do this storage array. I've spent some time thinking about different ways to do this, but on a simple level, there is a way I was looking at years ago for a simplistic optical circuit. It maybe of little performance (in the classical computing sense), but is meant for simplified low cost situations. But, if combined it with the casting idea, it makes for a simple architecture.

There are many people working on optical memory. I'm not sure about the casting idea. The wiring alone would make the casting idea inefficient and very large.

You are totally missing the structure of the thought again.

> Now. Let's say, that you use the above grid with casting. Your circuit board has panels of the grid stuck on it, or the board surface is printed. Now, with the optical, the board itself can be made to contain the circuit elements, printed in optically. Casting functions by flashing coded light through the board and the element responds at the speed of light. Now, when I model the light return time on these sorts of things, it doesn't seem impressive. Say the path is 10 cm return, and you are using a simple interference pattern for values, that takes roughly 3 billionth a second plus. Which is ok speed. But, the value has to be processed, so it is the fastest speed possible. Most processing is predetermined input and outputs. Even if the inputs are of random events that turn up, the processing is not, so the outcome for each is determined Even if the dataset is dynamic, sub parts of the processing of the new dataset remain deterministic, so sub parts repeatedly used maybe reused. If the math itself has to fundamentally change, then that further breaks down performance, requiring a reload of newly generated values for the new maths. But, deciding such maths are a conditional test problem, of the ranges, types and flow of data, so able to be accommodated and worked out. Even without a new range of values for new maths, there is still performance to be had, as maths still breaks down to basic structures. Such as + - x / etc.

I think you should work on this. Take some classes in logic design, semiconductor processing, system design. Then you can build this device for us and the greater Forth world.

Ok, so you fully agree it's a great idea, but want to subvert again? Why would I be sharing this for other's with relevant skills to work on it, or corporations that have budgets to pour money into developing something quickly, if I wanted to keep it to myself. Your logic about logic, doesn't work.

>> I've actually spent significant time in the past, trying to design and model such things, and had advanced designs well past what I am talking about here. But, here, we see a minor pulse of light returns a signal, and we are still using low energy, and I could probably harvest most of the unused photons, further reducing the energy.

>
> There are a number of designs I am avoiding here, that I had to really struggle with, due to not being able to see the deep overall picture easily, because of health issue. This design bit here, however, is adequate to get far, but strays a bit close to some other technological designs I am reserving. When you look at it, you are getting close to 3D stacked storage arrays of values, which can be printed as part of the circuit board. They are the map, the circuit board substrate of vales, is the map.
>
>
> 3D printing
>
> Though 3D printing methodology lacks the resolution of a top of the line fab these days, we could look at dealing with micron and sub micron ranges in the visible light spectrum, and interference patterns thereof, some day. A 10cm by 5cm by 2mm circuit board, offers 100,000 x 50,000 X 2,000 opportunities of spots for values. That's 10 trillion options for values, without overlap. I've looked into 3D printing methods for chemical (chemically constructing a item/feature) to molecular printing, to atomic level etc printing. Volumetric storage materials have long since been developed. This is close to do it at home territory, once worked out.
>
> If the return path is 1cm, then that's 30 billionths of a second and 200 billion potential spots for values in a square (the circle being lower). The good thing is, that values closer to the the broadcast have a closer path, returning values faster. Within 1mm, you are looking at 300 billionth of a second (up to 100 times faster than a high end mobile core, except it seldom works that way, but on the other hand many units of work can also be replaced by look up values, making it hard to compare the two types of system, but hopefully with this averaging faster than 100 times). A 1mm cube is 1 billion values. Why do we need conventional silicon chips? This is related to work I was thinking of nearly two decades back, if not longer.
>
> In a potential future high end fabrication process, the storage density of a single bit approaches 1/10 of a nanometre, but that is likely to be in a single layer, or reduced layers. Optically, that gets tricky, hence the reduction of density of layers along at least one axis. In the meantime, optical techniques are now at 5 nm. In reality, pattern techniques, are still limited by the packing density of atoms, as the basic minimum unit that can represent a bit with some stability. However, there are modifications to atoms to increase data density, but as far as sensing those optically, those things are beyond my immediate knowledge, but I have a vague idea, they might be possible. However, I'm currently thinking of ways to align all sub atomic spins, so there is increased density again. However, the degree of stability of all these techniques, will undoubtedly limit the size that is usable, unless one can force stability, which I am thinking about.
>
> I reserve all intellectual property (IP) rights 27-12-21. Which, any honest person knows, means they can't patent original work revealed so far, without my, or other original originator's, agreement, not that it implies they can't use it, if it's not patented (though, it also does not imply a licence of use before the period to apply for patent expires). My worry is IP thieves, taking and locking up base (potentially public) IP, stopping use by originators, and independent development and use, without agreement with originators. Here, it becomes free once the last period to apply for right, and patent, expires. In the meantime, it doesn't stop people from developing and patenting further IP beyond this base (You will notice, I have left a number of base mechanisms to achieve effects out. Allowing competitive development of those mechanisms, beyond what is stated here). I'm aware that some will have issue with this interpretation. But, a big sponsor, and control, makes things happen faster.
>
> You notice, manufacturers are no longer talking about advanced things here.

On Monday, 27 December 2021 at 03:15:01 UTC, Wayne morellini wrote:
> On Mon, 27 Dec 2021, 04:32 Rick C, <gnuarm.del...@gmail.com> wrote:
> On Sunday, December 26, 2021 at 11:12:39 AM UTC-5, Wayne morellini wrote:
> > Commercial in confidence. Trade secret.
> > All Intellectual Property Rights reserved. 27-12-21.
>
> Lol! This has got to be one of the funniest things I've ever seen posted to this group!!
> Rick, proverbial neurotic like laughing and illogically going on at a logic level lower than the discussion, while also agreeing, (by the looks of it) but missing the point, is not a good first reply. Can it for a while, and give other people a chance to post please!
> > My apologies for not posting this at Christmas.
> >
> > I confess, I don't really know FPGA, except that you are using look up table entries to represent results tied to some custom circuitry for performance and some fabric stitching (is that right?). I've been meaning to dive into learning it for years, but spiralling health got in the way.
>
> What??? What you call lookup tables are otherwise referred to as RAM. Yes, FPGAs typically use a small bit of RAM to implement lookup tables for logic. If you read an introductory text on logic design they will almost certainly teach Karnaugh maps which are tables specifying the output for each possible combination of inputs. This can be directly implemented in hardware by a small block of RAM.
> You mean, what I just described! Thank you..
> I'm not sure what you are saying about custom circuitry, but the logic that is implemented is specified by the designer.
> You already know this. ASIC features and ports to reduce the power consumption and Increase the performance of commonly used functions, as normal FPGA technology was slow and every hungry producing hear issues. Stop trying to show up to degrade.
> > But, at times, I wonder how you could make something like FPGA, but at home, or better, in factory. Decades back, I had an idea to do a simple printable read only memory, using a grid of lines and pass the current through at intersections or block it for 1's and zeros. This could be made with semi permanent writable memory techniques too. Now, I wonder if I should use my casting idea, from 41+ years ago, where you send out the address, everybody hears it, and the right one sends back the value it has. So, suitable for look up tables, but the same could be used for circuits.
>
> But that's not a circuit. That's an architecture. A circuit would have the details required to implement it. Your idea might be useful if implemented on a large network (and is the basis for many such networks), but would not be useful in a chip to implement RAM. RAM typically consists of a selection matrix with 1 of N lines activated to read out every bit in the row. This M bit wide word then is fed into multiplexers to select the 1 of M bits to be presented at the output. This can be done in parallel to enable reading many bits at a time.
> Thanks for agreeing again. Good to know we both seem to know these basic principles of dram that don't need to be actually repeated. However, I wasn't describing details of a circuit, but only said circuits could be implemented with it.
> The details of this depends on the type of RAM and the specific implementation.
> We are talking about simple arrays of ROM, with the possibility of making that into a re-writable memory. So, you sort of got that right, but you get so much wrong about the details of thought sometimes, it gets hard to keep up. I've got the kid next door constantly repeating the same part of a song on his hifi, so it's hard to read and hear something like that.
> > But, what about using optical effects to do this storage array. I've spent some time thinking about different ways to do this, but on a simple level, there is a way I was looking at years ago for a simplistic optical circuit. It maybe of little performance (in the classical computing sense), but is meant for simplified low cost situations. But, if combined it with the casting idea, it makes for a simple architecture.
>
> There are many people working on optical memory. I'm not sure about the casting idea. The wiring alone would make the casting idea inefficient and very large.
> You are totally missing the structure of the thought again.
> > Now. Let's say, that you use the above grid with casting. Your circuit board has panels of the grid stuck on it, or the board surface is printed. Now, with the optical, the board itself can be made to contain the circuit elements, printed in optically. Casting functions by flashing coded light through the board and the element responds at the speed of light. Now, when I model the light return time on these sorts of things, it doesn't seem impressive. Say the path is 10 cm return, and you are using a simple interference pattern for values, that takes roughly 3 billionth a second plus. Which is ok speed. But, the value has to be processed, so it is the fastest speed possible. Most processing is predetermined input and outputs. Even if the inputs are of random events that turn up, the processing is not, so the outcome for each is determined Even if the dataset is dynamic, sub parts of the processing of the new dataset remain deterministic, so sub parts repeatedly used maybe reused. If the math itself has to fundamentally change, then that further breaks down performance, requiring a reload of newly generated values for the new maths. But, deciding such maths are a conditional test problem, of the ranges, types and flow of data, so able to be accommodated and worked out. Even without a new range of values for new maths, there is still performance to be had, as maths still breaks down to basic structures. Such as + - x / etc.
>
> I think you should work on this. Take some classes in logic design, semiconductor processing, system design. Then you can build this device for us and the greater Forth world.
> Ok, so you fully agree it's a great idea, but want to subvert again? Why would I be sharing this for other's with relevant skills to work on it, or corporations that have budgets to pour money into developing something quickly, if I wanted to keep it to myself. Your logic about logic, doesn't work..
> >> I've actually spent significant time in the past, trying to design and model such things, and had advanced designs well past what I am talking about here. But, here, we see a minor pulse of light returns a signal, and we are still using low energy, and I could probably harvest most of the unused photons, further reducing the energy.
>
> >
> > There are a number of designs I am avoiding here, that I had to really struggle with, due to not being able to see the deep overall picture easily, because of health issue. This design bit here, however, is adequate to get far, but strays a bit close to some other technological designs I am reserving. When you look at it, you are getting close to 3D stacked storage arrays of values, which can be printed as part of the circuit board. They are the map, the circuit board substrate of vales, is the map.
> >
> >
> > 3D printing
> >
> > Though 3D printing methodology lacks the resolution of a top of the line fab these days, we could look at dealing with micron and sub micron ranges in the visible light spectrum, and interference patterns thereof, some day. A 10cm by 5cm by 2mm circuit board, offers 100,000 x 50,000 X 2,000 opportunities of spots for values. That's 10 trillion options for values, without overlap. I've looked into 3D printing methods for chemical (chemically constructing a item/feature) to molecular printing, to atomic level etc printing. Volumetric storage materials have long since been developed. This is close to do it at home territory, once worked out.
> >
> > If the return path is 1cm, then that's 30 billionths of a second and 200 billion potential spots for values in a square (the circle being lower). The good thing is, that values closer to the the broadcast have a closer path, returning values faster. Within 1mm, you are looking at 300 billionth of a second (up to 100 times faster than a high end mobile core, except it seldom works that way, but on the other hand many units of work can also be replaced by look up values, making it hard to compare the two types of system, but hopefully with this averaging faster than 100 times). A 1mm cube is 1 billion values. Why do we need conventional silicon chips? This is related to work I was thinking of nearly two decades back, if not longer.
> >
> > In a potential future high end fabrication process, the storage density of a single bit approaches 1/10 of a nanometre, but that is likely to be in a single layer, or reduced layers. Optically, that gets tricky, hence the reduction of density of layers along at least one axis. In the meantime, optical techniques are now at 5 nm. In reality, pattern techniques, are still limited by the packing density of atoms, as the basic minimum unit that can represent a bit with some stability. However, there are modifications to atoms to increase data density, but as far as sensing those optically, those things are beyond my immediate knowledge, but I have a vague idea, they might be possible. However, I'm currently thinking of ways to align all sub atomic spins, so there is increased density again. However, the degree of stability of all these techniques, will undoubtedly limit the size that is usable, unless one can force stability, which I am thinking about.
> >
> > I reserve all intellectual property (IP) rights 27-12-21. Which, any honest person knows, means they can't patent original work revealed so far, without my, or other original originator's, agreement, not that it implies they can't use it, if it's not patented (though, it also does not imply a licence of use before the period to apply for patent expires). My worry is IP thieves, taking and locking up base (potentially public) IP, stopping use by originators, and independent development and use, without agreement with originators. Here, it becomes free once the last period to apply for right, and patent, expires. In the meantime, it doesn't stop people from developing and patenting further IP beyond this base (You will notice, I have left a number of base mechanisms to achieve effects out. Allowing competitive development of those mechanisms, beyond what is stated here). I'm aware that some will have issue with this interpretation. But, a big sponsor, and control, makes things happen faster.
> >
> > You notice, manufacturers are no longer talking about advanced things here.
>
> When did manufacturers talk about advanced things *here*?
> GA. Seaforth, occasionally chimed in. Employees of J.Fox, ITV, and C.H. Ting with Mup20. I forget if shboom, Novix or silicon composers contributed at all?
> BTW, you can't publicly publish ideas and also reserve "all" IP rights. You can copyright what you've written, but that is of no value in protecting the ideas. The only issue with patent is that now the information is in the public domain, but that doesn't mean you can now patent any of this. You essentially have no say in the matter at this point.
> In the US there is a period after publication where you can still patent, unless that's been reformed. However, there has been a practice of patent trolls, to patent what they can get out of prior art/public information, due to a deficency in the US patent system, where public disclosure was only through certain means, where this forum might possibly fall outside of, or not be looked at over time, and the department would not do sufficient research to find public disclosure in all areas anyway. It eventually reformed and boiled down to, effectively, an honorary system of self disclosure, that many with criminal tendacies, didn't do. But, my failing knowledge of the patent system is decades old. I did notice that inventor associations were trying to get some changes, that I did not regard as entirely fair, but was too sick to keep up with by then.
>
> However, here I am claiming reservation of any remaining rights as a defence against such practices above. Even if it wasn't picked up as public disclosure, I have done it on three other basises as well, that might invalidate any autonomous claim. Challenging an illegal patent is very expensive, so clearer basises of no right to patent elements of the patent in the first place, is something the court, or department, could choose to use, otherwise, they are boiler plate clauses (look it up) until it is supported, unless there are other patent jurisdictions who will choose to support it.
>
> Intellectual Property Rights go beyond the patent systems, and include Kudos, which is a recognised thing in Japan. I notice, some organisations, don't seem to even recognise kudos, even though offered free use, but seem to want to retain the option to incorporate ownership of other's fee contributions without permission, instead of letting them remain free and agreeing to leave them out of patents instead, so others can also use them.
>
> However, you probably aren't aware of mechanisms of court law. So, you can argue something, and the court agree, and continue to agree in higher courts, to the top relevant court, and it becomes court law proper. So, I can lay out that such and such is the case, and the court can assess that argument in any case.
> Doesn't matter. Nothing I read was patentable anyway.
> Nonsense, you were just pestering as usual, just stop wasting time. This uncalled for, trolling like behaviour, of wrongly trying to negate correct things, is not constructive. Can somebody insert Rick's last name, I forget it? Anonymity is a privelage to do right, instead of wrong. I noticed, after last time, you were suddenly acting conservatively too. Also, one should reflect about their own behaviour before calling others a strange little fellow, or whatever I saw somebody being called before.
>
> Guys, time to stop wrecking things. Thirty years ago, it was constructive here. It was "The last of the summer wine" (search it).

On Monday, December 27, 2021 at 7:03:15 PM UTC+10, jpit...@gmail.com wrote:
> On Monday, 27 December 2021 at 03:15:01 UTC, Wayne morellini wrote:
> > On Mon, 27 Dec 2021, 04:32 Rick C, <gnuarm.del...@gmail.com> wrote:
> > On Sunday, December 26, 2021 at 11:12:39 AM UTC-5, Wayne morellini wrote:
> > > Commercial in confidence. Trade secret.
> > > All Intellectual Property Rights reserved. 27-12-21.
> >

Sorry for the delay. What was the point of them writing that article? They didn't even name what sort of NPU they were talking about. Is it network processing unit? It doesn't seem to be neural processing unit.

Anyway, their close block integration, via basically the same fashion as what is done in FPGA custom units (the fabric logic and look up tables being the standard parts, the extras being the part that adds custom acceleration). It's rather like saying one car is superior to a truck, because it has wheels, even though both do. But further, adding a processor to an FPGA, or the other way about, has long been known to be beneficial (which, ironically, misc had a chance in). So, apart from making out they have a bit better CPU/MCU configuration, is there much of a point. An FPGA could be decked out to compete similarly, except the energy consumption. So, it becomes: is it more suitable to a software solution, or a fpga solution, and then pick one. Where as, what I'm proposing is many times faster and likely lower energy, and done without a chip manufacturer and lots of licensing. To get it to do everything the best, requires maybe a big factory and investment, but to do normal low end things, it could be done at home.

Another aspect of energy requirement (I have more mechanisms and plans I proposed over the years), ultra short photonic bursts, reduce energy consumption. You still require enough energy to produce a return result along the data path, which is little. So, you are now, maybe (I haven't calculated it) comparing to the leakage of an large idle chip, maybe even including the section returning the result. So, this is many times better than both solutions in the document. The only issue is, the large datasets, to process every result. With my own new architecture proposal (not this one), I was going to announce, that memory conservation no longer made the sense it did years ago, as now memory isn't a problem. When memory has no current draw, except to access it, energy consumption no longer is an issue either. So, I was drawing up in my head a post forth architecture, which MQDCA, affectively, replaces anyway. But a last performance increase for silicon, or bismuth. It's a elaborate architecture.

With photonic datasets, the datasets can be very large, at, effectively, zero maintenance energies over the short term. As most data in the execution realm, is static, as it is a mapping of how a section of processing responds to different input, which remains true, unless you change the formular, but if it did change then many subunit components of routines would also remain true. Resulting in much data being static read only, in the execution domain. In the working data and storage domains, normal memory can be used, but optical long term storage can also come into it, which can displace caching, as write speed becomes an issue, rather than read speed. If only we could capture photons and maintain them. Photons are captured in the energy levels of atoms through electrons, aren't they. So, to capture and stabilise atoms and electrons, would effectively substitute (I've got actual mechanisms in mind over the years for different things, which can apply here). The problem is preventing spontaneous emission. But, backing off of the precision and increasing the stabilising factors, a certain data density night be possible, with a near light speed addressing of dynamic data, but I'm getting too far ahead. Use of printable magnetic memory is probably preferable. A broadcast light addressability of a memory location is possible. Maybe by combining a reactive layer to the memory cell layer, which reacts to broadcast and to orientation of the magnetic domain. This allows fast read and possibly short pipelined like write mechanisms, allowing multiple other memory operations as a memory write continues. This means that signalling needs valid and invalid signals, to signal operation successful, or write in progress or failed. If just using interference pattern as storage instead, the same strategy can be used, except writes can be a lot slower, but writing out the results of a segment of data, and then letting that settle into becoming formal storage data, is possible. We already put up with barbaric behaviour of various dram and flash block schemes. High speed pattern write schemes, are areas which would need investment in high precision development.

On Wednesday, December 29, 2021 at 4:45:44 PM UTC-6, Wayne morellini wrote:
> On Monday, December 27, 2021 at 7:03:15 PM UTC+10, jpit...@gmail.com wrote:
> > On Monday, 27 December 2021 at 03:15:01 UTC, Wayne morellini wrote:
> > > On Mon, 27 Dec 2021, 04:32 Rick C, <gnuarm.del...@gmail.com> wrote:
> > > On Sunday, December 26, 2021 at 11:12:39 AM UTC-5, Wayne morellini wrote:
> > > > Commercial in confidence. Trade secret.
> > > > All Intellectual Property Rights reserved. 27-12-21.
> > >
> Sorry for the delay. What was the point of them writing that article? They didn't even name what sort of NPU they were talking about. Is it network processing unit? It doesn't seem to be neural processing unit.
>
> Anyway, their close block integration, via basically the same fashion as what is done in FPGA custom units (the fabric logic and look up tables being the standard parts, the extras being the part that adds custom acceleration). It's rather like saying one car is superior to a truck, because it has wheels, even though both do. But further, adding a processor to an FPGA, or the other way about, has long been known to be beneficial (which, ironically, misc had a chance in). So, apart from making out they have a bit better CPU/MCU configuration, is there much of a point. An FPGA could be decked out to compete similarly, except the energy consumption. So, it becomes: is it more suitable to a software solution, or a fpga solution, and then pick one. Where as, what I'm proposing is many times faster and likely lower energy, and done without a chip manufacturer and lots of licensing. To get it to do everything the best, requires maybe a big factory and investment, but to do normal low end things, it could be done at home.
>
> Another aspect of energy requirement (I have more mechanisms and plans I proposed over the years), ultra short photonic bursts, reduce energy consumption. You still require enough energy to produce a return result along the data path, which is little. So, you are now, maybe (I haven't calculated it) comparing to the leakage of an large idle chip, maybe even including the section returning the result. So, this is many times better than both solutions in the document. The only issue is, the large datasets, to process every result. With my own new architecture proposal (not this one), I was going to announce, that memory conservation no longer made the sense it did years ago, as now memory isn't a problem. When memory has no current draw, except to access it, energy consumption no longer is an issue either. So, I was drawing up in my head a post forth architecture, which MQDCA, affectively, replaces anyway. But a last performance increase for silicon, or bismuth.. It's a elaborate architecture.
>
> With photonic datasets, the datasets can be very large, at, effectively, zero maintenance energies over the short term. As most data in the execution realm, is static, as it is a mapping of how a section of processing responds to different input, which remains true, unless you change the formular, but if it did change then many subunit components of routines would also remain true. Resulting in much data being static read only, in the execution domain. In the working data and storage domains, normal memory can be used, but optical long term storage can also come into it, which can displace caching, as write speed becomes an issue, rather than read speed. If only we could capture photons and maintain them. Photons are captured in the energy levels of atoms through electrons, aren't they. So, to capture and stabilise atoms and electrons, would effectively substitute (I've got actual mechanisms in mind over the years for different things, which can apply here). The problem is preventing spontaneous emission. But, backing off of the precision and increasing the stabilising factors, a certain data density night be possible, with a near light speed addressing of dynamic data, but I'm getting too far ahead. Use of printable magnetic memory is probably preferable. A broadcast light addressability of a memory location is possible. Maybe by combining a reactive layer to the memory cell layer, which reacts to broadcast and to orientation of the magnetic domain. This allows fast read and possibly short pipelined like write mechanisms, allowing multiple other memory operations as a memory write continues. This means that signalling needs valid and invalid signals, to signal operation successful, or write in progress or failed. If just using interference pattern as storage instead, the same strategy can be used, except writes can be a lot slower, but writing out the results of a segment of data, and then letting that settle into becoming formal storage data, is possible. We already put up with barbaric behaviour of various dram and flash block schemes. High speed pattern write schemes, are areas which would need investment in high precision development.

My Nonsense Processing Unit blew a fuse, processing will resume April 1.

On Wednesday, December 29, 2021 at 7:38:31 PM UTC-5, James Brakefield wrote:
> On Wednesday, December 29, 2021 at 4:45:44 PM UTC-6, Wayne morellini wrote:
> > On Monday, December 27, 2021 at 7:03:15 PM UTC+10, jpit...@gmail.com wrote:
> > > On Monday, 27 December 2021 at 03:15:01 UTC, Wayne morellini wrote:
> > > > On Mon, 27 Dec 2021, 04:32 Rick C, <gnuarm.del...@gmail.com> wrote:
> > > > On Sunday, December 26, 2021 at 11:12:39 AM UTC-5, Wayne morellini wrote:
> > > > > Commercial in confidence. Trade secret.
> > > > > All Intellectual Property Rights reserved. 27-12-21.
> > > >
> > Sorry for the delay. What was the point of them writing that article? They didn't even name what sort of NPU they were talking about. Is it network processing unit? It doesn't seem to be neural processing unit.
> >
> > Anyway, their close block integration, via basically the same fashion as what is done in FPGA custom units (the fabric logic and look up tables being the standard parts, the extras being the part that adds custom acceleration). It's rather like saying one car is superior to a truck, because it has wheels, even though both do. But further, adding a processor to an FPGA, or the other way about, has long been known to be beneficial (which, ironically, misc had a chance in). So, apart from making out they have a bit better CPU/MCU configuration, is there much of a point. An FPGA could be decked out to compete similarly, except the energy consumption. So, it becomes: is it more suitable to a software solution, or a fpga solution, and then pick one. Where as, what I'm proposing is many times faster and likely lower energy, and done without a chip manufacturer and lots of licensing. To get it to do everything the best, requires maybe a big factory and investment, but to do normal low end things, it could be done at home.
> >
> > Another aspect of energy requirement (I have more mechanisms and plans I proposed over the years), ultra short photonic bursts, reduce energy consumption. You still require enough energy to produce a return result along the data path, which is little. So, you are now, maybe (I haven't calculated it) comparing to the leakage of an large idle chip, maybe even including the section returning the result. So, this is many times better than both solutions in the document. The only issue is, the large datasets, to process every result. With my own new architecture proposal (not this one), I was going to announce, that memory conservation no longer made the sense it did years ago, as now memory isn't a problem. When memory has no current draw, except to access it, energy consumption no longer is an issue either. So, I was drawing up in my head a post forth architecture, which MQDCA, affectively, replaces anyway. But a last performance increase for silicon, or bismuth. It's a elaborate architecture.
> >
> > With photonic datasets, the datasets can be very large, at, effectively, zero maintenance energies over the short term. As most data in the execution realm, is static, as it is a mapping of how a section of processing responds to different input, which remains true, unless you change the formular, but if it did change then many subunit components of routines would also remain true. Resulting in much data being static read only, in the execution domain. In the working data and storage domains, normal memory can be used, but optical long term storage can also come into it, which can displace caching, as write speed becomes an issue, rather than read speed. If only we could capture photons and maintain them. Photons are captured in the energy levels of atoms through electrons, aren't they. So, to capture and stabilise atoms and electrons, would effectively substitute (I've got actual mechanisms in mind over the years for different things, which can apply here).. The problem is preventing spontaneous emission. But, backing off of the precision and increasing the stabilising factors, a certain data density night be possible, with a near light speed addressing of dynamic data, but I'm getting too far ahead. Use of printable magnetic memory is probably preferable. A broadcast light addressability of a memory location is possible. Maybe by combining a reactive layer to the memory cell layer, which reacts to broadcast and to orientation of the magnetic domain. This allows fast read and possibly short pipelined like write mechanisms, allowing multiple other memory operations as a memory write continues. This means that signalling needs valid and invalid signals, to signal operation successful, or write in progress or failed. If just using interference pattern as storage instead, the same strategy can be used, except writes can be a lot slower, but writing out the results of a segment of data, and then letting that settle into becoming formal storage data, is possible. We already put up with barbaric behaviour of various dram and flash block schemes. High speed pattern write schemes, are areas which would need investment in high precision development.
> My Nonsense Processing Unit blew a fuse, processing will resume April 1.

This "white paper" is really just an advertising tool. Their goal is to explain all the disadvantages of FPGAs even to the point of inventing some that do not exist. They don't do much promotion of the Network Processor they sell, but it is clearly mentioned with a photograph and part number. It appears the NPU is just another name for a RISC CPU card.

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209

On Thursday, December 30, 2021 at 10:38:31 AM UTC+10, James Brakefield wrote:
> On Wednesday, December 29, 2021 at 4:45:44 PM UTC-6, Wayne morellini wrote:

> My Nonsense Processing Unit blew a fuse, processing will resume April 1.

Thanks James. That will really help a lot. Pitty you have issues figuring out reality. See you in April!

On Thursday, December 30, 2021 at 11:49:07 PM UTC+10, gnuarm.del...@gmail.com wrote:
> On Wednesday, December 29, 2021 at 7:38:31 PM UTC-5, James Brakefield wrote:

> This "white paper" is really just an advertising tool. Their goal is to explain all the disadvantages of FPGAs even to the point of inventing some that do not exist. They don't do much promotion of the Network Processor they sell, but it is clearly mentioned with a photograph and part number. It appears the NPU is just another name for a RISC CPU card.

Thanks for that Rick. I had trouble reading that night.

>
> --
>
> Rick C.
>
> + Get 1,000 miles of free Supercharging
> + Tesla referral code - https://ts.la/richard11209

On Monday, December 27, 2021 at 2:12:39 AM UTC+10, Wayne morellini wrote:
> Commercial in confidence. Trade secret.
> All Intellectual Property Rights reserved. 27-12-21.

Thinking about this again. Their is opportunity for misc, as the problem has been performance and energy consumption. A little optical chip connected to a memory could given enough performance for most projects. If only motors had simple optical interfaces. But Intel hasn't released their optical interfaces on consumer equipment.

On Monday, December 27, 2021 at 2:12:39 AM UTC+10, Wayne morellini wrote:
> Commercial in confidence. Trade secret.
> All Intellectual Property Rights reserved. 27-12-21.
>
> My apologies for not posting this at Christmas.
>
> I confess, I don't really know FPGA, except that you are using look up table entries to represent results tied to some custom circuitry for performance and some fabric stitching (is that right?). I've been meaning to dive into learning it for years, but spiralling health got in the way.
>
> But, at times, I wonder how you could make something like FPGA, but at home, or better, in factory. Decades back, I had an idea to do a simple printable read only memory, using a grid of lines and pass the current through at intersections or block it for 1's and zeros. This could be made with semi permanent writable memory techniques too. Now, I wonder if I should use my casting idea, from 41+ years ago, where you send out the address, everybody hears it, and the right one sends back the value it has. So, suitable for look up tables, but the same could be used for circuits.
>
> But, what about using optical effects to do this storage array. I've spent some time thinking about different ways to do this, but on a simple level, there is a way I was looking at years ago for a simplistic optical circuit. It maybe of little performance (in the classical computing sense), but is meant for simplified low cost situations. But, if combined it with the casting idea, it makes for a simple architecture.
>
> Now. Let's say, that you use the above grid with casting. Your circuit board has panels of the grid stuck on it, or the board surface is printed. Now, with the optical, the board itself can be made to contain the circuit elements, printed in optically. Casting functions by flashing coded light through the board and the element responds at the speed of light. Now, when I model the light return time on these sorts of things, it doesn't seem impressive. Say the path is 10 cm return, and you are using a simple interference pattern for values, that takes roughly 3 billionth a second plus. Which is ok speed. But, the value has to be processed, so it is the fastest speed possible. Most processing is predetermined input and outputs. Even if the inputs are of random events that turn up, the processing is not, so the outcome for each is determined Even if the dataset is dynamic, sub parts of the processing of the new dataset remain deterministic, so sub parts repeatedly used maybe reused. If the math itself has to fundamentally change, then that further breaks down performance, requiring a reload of newly generated values for the new maths. But, deciding such maths are a conditional test problem, of the ranges, types and flow of data, so able to be accommodated and worked out. Even without a new range of values for new maths, there is still performance to be had, as maths still breaks down to basic structures. Such as + - x / etc.
>
> I've actually spent significant time in the past, trying to design and model such things, and had advanced designs well past what I am talking about here. But, here, we see a minor pulse of light returns a signal, and we are still using low energy, and I could probably harvest most of the unused photons, further reducing the energy.
>
> There are a number of designs I am avoiding here, that I had to really struggle with, due to not being able to see the deep overall picture easily, because of health issue. This design bit here, however, is adequate to get far, but strays a bit close to some other technological designs I am reserving. When you look at it, you are getting close to 3D stacked storage arrays of values, which can be printed as part of the circuit board. They are the map, the circuit board substrate of vales, is the map.
>
>
> 3D printing
>
> Though 3D printing methodology lacks the resolution of a top of the line fab these days, we could look at dealing with micron and sub micron ranges in the visible light spectrum, and interference patterns thereof, some day. A 10cm by 5cm by 2mm circuit board, offers 100,000 x 50,000 X 2,000 opportunities of spots for values. That's 10 trillion options for values, without overlap. I've looked into 3D printing methods for chemical (chemically constructing a item/feature) to molecular printing, to atomic level etc printing. Volumetric storage materials have long since been developed. This is close to do it at home territory, once worked out.
>
> If the return path is 1cm, then that's 30 billionths of a second and 200 billion potential spots for values in a square (the circle being lower). The good thing is, that values closer to the the broadcast have a closer path, returning values faster. Within 1mm, you are looking at 300 billionth of a second (up to 100 times faster than a high end mobile core, except it seldom works that way, but on the other hand many units of work can also be replaced by look up values, making it hard to compare the two types of system, but hopefully with this averaging faster than 100 times). A 1mm cube is 1 billion values. Why do we need conventional silicon chips? This is related to work I was thinking of nearly two decades back, if not longer.
>
> In a potential future high end fabrication process, the storage density of a single bit approaches 1/10 of a nanometre, but that is likely to be in a single layer, or reduced layers. Optically, that gets tricky, hence the reduction of density of layers along at least one axis. In the meantime, optical techniques are now at 5 nm. In reality, pattern techniques, are still limited by the packing density of atoms, as the basic minimum unit that can represent a bit with some stability. However, there are modifications to atoms to increase data density, but as far as sensing those optically, those things are beyond my immediate knowledge, but I have a vague idea, they might be possible. However, I'm currently thinking of ways to align all sub atomic spins, so there is increased density again. However, the degree of stability of all these techniques, will undoubtedly limit the size that is usable, unless one can force stability, which I am thinking about.
>
> I reserve all intellectual property (IP) rights 27-12-21. Which, any honest person knows, means they can't patent original work revealed so far, without my, or other original originator's, agreement, not that it implies they can't use it, if it's not patented (though, it also does not imply a licence of use before the period to apply for patent expires). My worry is IP thieves, taking and locking up base (potentially public) IP, stopping use by originators, and independent development and use, without agreement with originators. Here, it becomes free once the last period to apply for right, and patent, expires. In the meantime, it doesn't stop people from developing and patenting further IP beyond this base (You will notice, I have left a number of base mechanisms to achieve effects out. Allowing competitive development of those mechanisms, beyond what is stated here). I'm aware that some will have issue with this interpretation. But, a big sponsor, and control, makes things happen faster.
>
> You notice, manufacturers are no longer talking about advanced things here.

Discussing this again, under the same previous outlined protections mentioned in this thread. The addressability through broadcasting, is only a convenient and simple potential giveaway here, to get thing to work. Speed of individual random addressability of points is the issue in photonics. Photonics is usually slow, requiring scanning to get speed, rather than memory like point to point speed. I already came up with a mechanism for this a while back, but that's not up here. This is only the easier to do version, rather than the stuff I was aiming at, which is a number of levels deeper. I abandoned those in turn for a better technology. There are a few better technologies than the straight up photonics domain. Some of the issues you get with these things in network fragility and alignment issues. The global broadcast addressing means the unit can tolerate more warping before storage will not respond, where an direct addressing scheme could easily miss it's target with little warping, meaning thermal expansion could do it. There are ways around this for direct addressing schemes, but usually greatly increasing complexity to get the greater protection. For example, a purely photonic switch circuit (like with a regular transistor circuit) can be much more reliable, but require much more complexity, and require a certain level of mechanism, before it is truely fast. The issue is, we have electronic circuits at the moment, which could be made like photonic circuits, the issue is electrons and leakage. The signal passes around the wire at the speed of light, so to speak, but electrons pass very slowly through the wire, and their interactions produce a lot of issues. The independent movement of the signal over the wire, points to something deeper happening in the physics here, something which would be missed by many engineers and researchers. Exploiting that effect, that physics, is key, as that effect and physics is sticky and therefore guidable, unlike light. Not saying that light isn't sticky, just not in the ways we normally use it. If you can manipulate the effect more directly, rather than the electrons, you can break dependence on the electron's restrictions. It goes far deeper than this, but I shouldn't have mentioned that much. Anyways, a simple example of how to compensate for some warping in an direct addressable scheme, is top mounting of the photon emitter, above or below the plain. This deals with an amount of warping, and can be setup to deal with thermal expansion, but now the timing related travel distance between points increases, which is not such an issue considering the short turn around times, which is adequate for many applications, but it also greatly wastes space that could be used for storage, spending on configuration. If we say, made storage a 3D stack of storage (not a forth stack), the greater the stack depth the less the ratio of lost space above the plain is compared to the stack. These are the some explanations. I would adjoin the stack, address out and down, and use compensation for thermal issues, a hybrid of the two. However. In military applications, I imagine they would use above place technology for lower spec but more reliability, but broadcast for ultimate reliability, sacrificing some storage density, but for highest spec, the stack adjustable addressing hybrid, in highest performance applications, where they compensate for failure until they can't compensate any longer, a win or loose strategy. But, they would use broadcast or other type of processing for backup of the main unit failed. I would incorporate broadcast as well into the stack hybrid, even in a second direction, as an additional backup as well. In all this, shorter distance produces shorter response time. When a stack, or plain, looks like a longer response time, you situate your highest performance need code closest to the emitter. This is very much like caching. It's pointless disregarding things like caching, because that's how the performance limitations of the real world works.