On Friday, 28 January 2022 at 08:46:15 UTC, Paul Rubin wrote:
> Jurgen Pitaske <jpit...@gmail.com> writes:
> >> OKCAD seems roughly comparable to other stuff that has been around since
> >> the 1980s.
> >
> > For example which product / solution? And what were the results
> > achieved?
> For example the Berkeley tools: Caesar, its successor Magic, Spice, and
> so on. Spice is still in use and important. I wrote that Magic had
> long been superseded by HDL's, but now see that it is still around:
>
> http://opencircuitdesign.com/magic/
>
> I have no idea if anyone uses Magic now, but lots of chips were designed
> with it back in the day.

Thank you very much for this link,
and there is a lot of documentation
http://opencircuitdesign.com/magic/
updated last January

On Wednesday, January 26, 2022 at 9:11:30 PM UTC+10, jpit...@gmail.com wrote:
> On Wednesday, 26 January 2022 at 10:09:31 UTC, Paul Rubin wrote:
> > Wayne morellini <waynemo...@gmail.com> writes:
...
> This whole MISC16 project started in CPLD at the time, 25 years ago,
> AND WAS RUNNING FORTH THEN
> and is now in FPGA on github running an adapted eForth.
> Thanks to Steve.
> I was in ASIC at the time, and just want to find out if there is a way to get it into ASIC,
> and what the performance would be now
> and what the cost would be.
> i MIGHT FIND A SPARE CORNER ON AN MPW FOR THESE 2500 GATES ...
> No real BUSINESS requirement, as the FPGA is there now and flexible to mess around with if wanted.
>
> There was an ASIC already at the time, using a modified design, manufactured at AMS in Austria as a student's final project.

So, what was the speed and energy that the CPLD was able to achieve, and where do I find information about misc16?

Thanks.

On Friday, 28 January 2022 at 14:32:37 UTC, Wayne morellini wrote:
> On Wednesday, January 26, 2022 at 9:11:30 PM UTC+10, jpit...@gmail.com wrote:
> > On Wednesday, 26 January 2022 at 10:09:31 UTC, Paul Rubin wrote:
> > > Wayne morellini <waynemo...@gmail.com> writes:
> ..
> > This whole MISC16 project started in CPLD at the time, 25 years ago,
> > AND WAS RUNNING FORTH THEN
> > and is now in FPGA on github running an adapted eForth.
> > Thanks to Steve.
> > I was in ASIC at the time, and just want to find out if there is a way to get it into ASIC,
> > and what the performance would be now
> > and what the cost would be.
> > i MIGHT FIND A SPARE CORNER ON AN MPW FOR THESE 2500 GATES ...
> > No real BUSINESS requirement, as the FPGA is there now and flexible to mess around with if wanted.
> >
> > There was an ASIC already at the time, using a modified design, manufactured at AMS in Austria as a student's final project.

> So, what was the speed and energy that the CPLD was able to achieve, and where do I find information about misc16?
>
> Thanks.

I was not involved in the ASIC as it was done at FH Nuremberg,
so I assume nobody is available anymore to answer this.
25 years is a long time ...
I had moved on,
heard about the ASIC surprise about 5 years ago.

Some part I have translated from a documentation, which was a surprise to me

[1] The meaning of these values becomes particularly clear
when this instruction is compared with the corresponding MOVE.W(An)+,Dn instruction of the Motorola MC68000 microprocessor,
which requires 8 clock cycles with the same 16-bit data bus,
or of the MC68008, which takes 16 clocks on an 8-bit data bus.
It is noteworthy that an ADDC ((SP)), DR2 instruction, coded as 82H,A3H, is also executed in the same time or number of cycles.
This command adds the operands addressed indirectly via the stack pointer to the contents of data register DR1,
taking the carry flag into account,
and stores the result in data register DR2 (see Table 1).
The corresponding instruction of the MC68000 ADD (An),+,Dn needs 8 cycles, and that of the MC6008 16 cycles.

The link to the current implementation of MISC16 is at
https://github.com/Steve-Teal/eforth-misc16
so you can do your own.

On Friday, 28 January 2022 at 16:09:28 UTC, Jurgen Pitaske wrote:
> On Friday, 28 January 2022 at 14:32:37 UTC, Wayne morellini wrote:
> > On Wednesday, January 26, 2022 at 9:11:30 PM UTC+10, jpit...@gmail.com wrote:
> > > On Wednesday, 26 January 2022 at 10:09:31 UTC, Paul Rubin wrote:
> > > > Wayne morellini <waynemo...@gmail.com> writes:
> > ..
> > > This whole MISC16 project started in CPLD at the time, 25 years ago,
> > > AND WAS RUNNING FORTH THEN
> > > and is now in FPGA on github running an adapted eForth.
> > > Thanks to Steve.
> > > I was in ASIC at the time, and just want to find out if there is a way to get it into ASIC,
> > > and what the performance would be now
> > > and what the cost would be.
> > > i MIGHT FIND A SPARE CORNER ON AN MPW FOR THESE 2500 GATES ...
> > > No real BUSINESS requirement, as the FPGA is there now and flexible to mess around with if wanted.
> > >
> > > There was an ASIC already at the time, using a modified design, manufactured at AMS in Austria as a student's final project.
>
> > So, what was the speed and energy that the CPLD was able to achieve, and where do I find information about misc16?
> >
> > Thanks.
> I was not involved in the ASIC as it was done at FH Nuremberg,
> so I assume nobody is available anymore to answer this.
> 25 years is a long time ...
> I had moved on,
> heard about the ASIC surprise about 5 years ago.
>
> Some part I have translated from a documentation, which was a surprise to me
>
> [1] The meaning of these values becomes particularly clear
> when this instruction is compared with the corresponding MOVE.W(An)+,Dn instruction of the Motorola MC68000 microprocessor,
> which requires 8 clock cycles with the same 16-bit data bus,
> or of the MC68008, which takes 16 clocks on an 8-bit data bus.
> It is noteworthy that an ADDC ((SP)), DR2 instruction, coded as 82H,A3H, is also executed in the same time or number of cycles.
> This command adds the operands addressed indirectly via the stack pointer to the contents of data register DR1,
> taking the carry flag into account,
> and stores the result in data register DR2 (see Table 1).
> The corresponding instruction of the MC68000 ADD (An),+,Dn needs 8 cycles, and that of the MC6008 16 cycles.
>
> The link to the current implementation of MISC16 is at
> https://github.com/Steve-Teal/eforth-misc16
> so you can do your own.

See as well here - including the usual CLF negativity
https://groups.google.com/g/comp.lang.forth/c/QJu7L6gSEwI

On Saturday, January 29, 2022 at 2:09:28 AM UTC+10, jpit...@gmail.com wrote:
> On Friday, 28 January 2022 at 14:32:37 UTC, Wayne morellini wrote:
> > On Wednesday, January 26, 2022 at 9:11:30 PM UTC+10, jpit...@gmail.com wrote:
> > > On Wednesday, 26 January 2022 at 10:09:31 UTC, Paul Rubin wrote:
> > > > Wayne morellini <waynemo...@gmail.com> writes:
> > ..
> > > This whole MISC16 project started in CPLD at the time, 25 years ago,
> > > AND WAS RUNNING FORTH THEN
> > > and is now in FPGA on github running an adapted eForth.
> > > Thanks to Steve.
> > > I was in ASIC at the time, and just want to find out if there is a way to get it into ASIC,
> > > and what the performance would be now
> > > and what the cost would be.
> > > i MIGHT FIND A SPARE CORNER ON AN MPW FOR THESE 2500 GATES ...
> > > No real BUSINESS requirement, as the FPGA is there now and flexible to mess around with if wanted.
> > >
> > > There was an ASIC already at the time, using a modified design, manufactured at AMS in Austria as a student's final project.
>
> > So, what was the speed and energy that the CPLD was able to achieve, and where do I find information about misc16?
> >
> > Thanks.
> I was not involved in the ASIC as it was done at FH Nuremberg,
> so I assume nobody is available anymore to answer this.
> 25 years is a long time ...
> I had moved on,
> heard about the ASIC surprise about 5 years ago.
>
> Some part I have translated from a documentation, which was a surprise to me
>
> [1] The meaning of these values becomes particularly clear
> when this instruction is compared with the corresponding MOVE.W(An)+,Dn instruction of the Motorola MC68000 microprocessor,
> which requires 8 clock cycles with the same 16-bit data bus,
> or of the MC68008, which takes 16 clocks on an 8-bit data bus.
> It is noteworthy that an ADDC ((SP)), DR2 instruction, coded as 82H,A3H, is also executed in the same time or number of cycles.
> This command adds the operands addressed indirectly via the stack pointer to the contents of data register DR1,
> taking the carry flag into account,
> and stores the result in data register DR2 (see Table 1).
> The corresponding instruction of the MC68000 ADD (An),+,Dn needs 8 cycles, and that of the MC6008 16 cycles.
>
> The link to the current implementation of MISC16 is at
> https://github.com/Steve-Teal/eforth-misc16
> so you can do your own.

I see (except how the 68000 relates to this) but am too tired to read through this (and Steve's lost the link to the original paper). I used memory functions on a hybrid approach for my 2 bit design proposal. It gets towards holding a cannon to your head relying on memory mapped functions eventually, but it's got its beauty. So, I thought you did a more reasonable version of Chuck's Misc. But you did mention 5 bit instructions. I must be missing something :) Time for bed.

I'm just drawing up unique graphics modes for a retro project I shouldn't do, but intend to ask it's community if they would like to do it. But, it's so just there, while everything else is just waiting. The idea was, that an zx80/zx81 could have been a superior game console system if released in 1977, with a few simple circuitry changes made to graphics, with colour and multi colour modes added, 64KB ram (like the 1977 Bally Astrocade, in comparison) and higher resolution graphics,not to forget sound, and a rehashed IO scheme. Basically just how much it could be pushed in the period from 1977-1981 (a bit of flexibility). This is just a what could have been done instead, like tribute thing, as a very small surprise portable modern console shrinkage of what the circuit would look like back then, using a number of unique techniques. Unfortunately, the vector graphics mode is proving to be a pain in the butt, as I couldn't get to write the the design up at the time (likely answering Rick) and hence forgot many things (and working at a low level now). I'm trying to do simple alternatives to sprites, while dealing with clashes. Unfortunately, I bit off a bit much which would have been good to resolve while the design was fresh in my mind. Its intended to be an z80 and some custom circuitry in a asuc or programmable logic, trying not to emulate anything (as certain people into these things don't like that). However, I was interested in doing others after, and maybe use misc for them. That's why I was looking at your processor.

We could then say, what would a misc system be like compared to the Atari 2600, other Atari's, Amiga/ST/Mega Drive (genesis). Am alternative to the Commodore 128, would be a commodore 64 integrated Vic-II chip with high res mode and 80 column text (even the Amstrad PCW's four green scale hires mode, was rather pleasing). Improved graphics technique and three+ banks of 64KB memory, with my bank window concept, in 1984. At least one bank is graphics processor mappable. The extensions are, maybe an extra bus for graphics, 16 sprites, higher resolution and more colour (320*200 8 bit or 640*200 4 bit, is 64,0000 bytes per buffer). The same architecture extended and a few simple extra graphic techniques. This would be a common platform for business and home, I'm two different cases, with more memory in the business model. Basically, non Dy much needed an Amiga or ST in business. The business range was not advanced enough, nor the home range, the Commodore Amiga saved them. Of you had designed an expandable common development target architecture, them the system could have expanded to 16 bit 6502 and 32 bit 6502, and really revised sales of PC's, vastly undercutting them and their graphics architecture (another potential upgrade). But, if you added misc to that, then, we could say, what could they have done instead of the Commodore Amiga, Atari ST, or Mega Drive (genesis) and use an arm like integrated circuit with simple graphics architecture, sound and IO. The Mega Drive would be a simpler target to compare too. It's unreal watching videos about the business development decisions made at all the top companies, that shook them out. It's obvious what thru should have done, and there were truckloads of golden opportunity moments that were rejected. Anyway, I had hoped to one day divert my attention to doing a misc type retro design with fancy graphics tech beyond the stuff here, that could have been done. This is an integrated chip design with all sorts of processing and graphics features able to be released in the 1970's, but as time goes by, expandable into a better and better, system during the 1980's. The design, suitable for MCU use today, not just a boutique product down memory lane. I understand now. Why they wanted Chuck to develop an 8 bit misc processor. For control purposes, with extended addressing, you can do quiet a lot. Anyway, enough of the trip down memory lane. But, there is potential for limited boutique products.

My apologies. I misread information. The earlier version of the Bally
Astrocade was not 64KB, it did get mass distributed till 1978, and I conserved memory with the graphic techniques, I didn't take into account, something we have long had an abundance of, timing. Hence why Commodore 64 uses 40 bytes per scan line, to give enough bandwidth for the processor. But, no undoable, with sprites, rather than hybrids to get the resolution at increased pixel depth, and rom graphics access off cartridge could be quicker too, and such static or limited animation graphics where common in content of the day. But, an extra graphics bus is not entirely out of the question as well.

On Friday, 28 January 2022 at 18:01:56 UTC, Wayne morellini wrote:
> On Saturday, January 29, 2022 at 2:09:28 AM UTC+10, jpit...@gmail.com wrote:
> > On Friday, 28 January 2022 at 14:32:37 UTC, Wayne morellini wrote:
> > > On Wednesday, January 26, 2022 at 9:11:30 PM UTC+10, jpit...@gmail.com wrote:
> > > > On Wednesday, 26 January 2022 at 10:09:31 UTC, Paul Rubin wrote:
> > > > > Wayne morellini <waynemo...@gmail.com> writes:
> > > ..
> > > > This whole MISC16 project started in CPLD at the time, 25 years ago,
> > > > AND WAS RUNNING FORTH THEN
> > > > and is now in FPGA on github running an adapted eForth.
> > > > Thanks to Steve.
> > > > I was in ASIC at the time, and just want to find out if there is a way to get it into ASIC,
> > > > and what the performance would be now
> > > > and what the cost would be.
> > > > i MIGHT FIND A SPARE CORNER ON AN MPW FOR THESE 2500 GATES ...
> > > > No real BUSINESS requirement, as the FPGA is there now and flexible to mess around with if wanted.
> > > >
> > > > There was an ASIC already at the time, using a modified design, manufactured at AMS in Austria as a student's final project.
> >
> > > So, what was the speed and energy that the CPLD was able to achieve, and where do I find information about misc16?
> > >
> > > Thanks.
> > I was not involved in the ASIC as it was done at FH Nuremberg,
> > so I assume nobody is available anymore to answer this.
> > 25 years is a long time ...
> > I had moved on,
> > heard about the ASIC surprise about 5 years ago.
> >
> > Some part I have translated from a documentation, which was a surprise to me
> >
> > [1] The meaning of these values becomes particularly clear
> > when this instruction is compared with the corresponding MOVE.W(An)+,Dn instruction of the Motorola MC68000 microprocessor,
> > which requires 8 clock cycles with the same 16-bit data bus,
> > or of the MC68008, which takes 16 clocks on an 8-bit data bus.
> > It is noteworthy that an ADDC ((SP)), DR2 instruction, coded as 82H,A3H, is also executed in the same time or number of cycles.
> > This command adds the operands addressed indirectly via the stack pointer to the contents of data register DR1,
> > taking the carry flag into account,
> > and stores the result in data register DR2 (see Table 1).
> > The corresponding instruction of the MC68000 ADD (An),+,Dn needs 8 cycles, and that of the MC6008 16 cycles.
> >
> > The link to the current implementation of MISC16 is at
> > https://github.com/Steve-Teal/eforth-misc16
> > so you can do your own.

> I see (except how the 68000 relates to this) but am too tired to read through this (and Steve's lost the link to the original paper). I used memory functions on a hybrid approach for my 2 bit design proposal. It gets towards holding a cannon to your head relying on memory mapped functions eventually, but it's got its beauty. So, I thought you did a more reasonable version of Chuck's Misc. But you did mention 5 bit instructions. I must be missing something :) Time for bed.
>
> I'm just drawing up unique graphics modes for a retro project I shouldn't do, but intend to ask it's community if they would like to do it. But, it's so just there, while everything else is just waiting. The idea was, that an zx80/zx81 could have been a superior game console system if released in 1977, with a few simple circuitry changes made to graphics, with colour and multi colour modes added, 64KB ram (like the 1977 Bally Astrocade, in comparison) and higher resolution graphics,not to forget sound, and a rehashed IO scheme. Basically just how much it could be pushed in the period from 1977-1981 (a bit of flexibility). This is just a what could have been done instead, like tribute thing, as a very small surprise portable modern console shrinkage of what the circuit would look like back then, using a number of unique techniques. Unfortunately, the vector graphics mode is proving to be a pain in the butt, as I couldn't get to write the the design up at the time (likely answering Rick) and hence forgot many things (and working at a low level now). I'm trying to do simple alternatives to sprites, while dealing with clashes. Unfortunately, I bit off a bit much which would have been good to resolve while the design was fresh in my mind. Its intended to be an z80 and some custom circuitry in a asuc or programmable logic, trying not to emulate anything (as certain people into these things don't like that).. However, I was interested in doing others after, and maybe use misc for them. That's why I was looking at your processor.
>
> We could then say, what would a misc system be like compared to the Atari 2600, other Atari's, Amiga/ST/Mega Drive (genesis). Am alternative to the Commodore 128, would be a commodore 64 integrated Vic-II chip with high res mode and 80 column text (even the Amstrad PCW's four green scale hires mode, was rather pleasing). Improved graphics technique and three+ banks of 64KB memory, with my bank window concept, in 1984. At least one bank is graphics processor mappable. The extensions are, maybe an extra bus for graphics, 16 sprites, higher resolution and more colour (320*200 8 bit or 640*200 4 bit, is 64,0000 bytes per buffer). The same architecture extended and a few simple extra graphic techniques. This would be a common platform for business and home, I'm two different cases, with more memory in the business model. Basically, non Dy much needed an Amiga or ST in business. The business range was not advanced enough, nor the home range, the Commodore Amiga saved them. Of you had designed an expandable common development target architecture, them the system could have expanded to 16 bit 6502 and 32 bit 6502, and really revised sales of PC's, vastly undercutting them and their graphics architecture (another potential upgrade). But, if you added misc to that, then, we could say, what could they have done instead of the Commodore Amiga, Atari ST, or Mega Drive (genesis) and use an arm like integrated circuit with simple graphics architecture, sound and IO. The Mega Drive would be a simpler target to compare too. It's unreal watching videos about the business development decisions made at all the top companies, that shook them out. It's obvious what thru should have done, and there were truckloads of golden opportunity moments that were rejected. Anyway, I had hoped to one day divert my attention to doing a misc type retro design with fancy graphics tech beyond the stuff here, that could have been done. This is an integrated chip design with all sorts of processing and graphics features able to be released in the 1970's, but as time goes by, expandable into a better and better, system during the 1980's. The design, suitable for MCU use today, not just a boutique product down memory lane. I understand now. Why they wanted Chuck to develop an 8 bit misc processor. For control purposes, with extended addressing, you can do quiet a lot. Anyway, enough of the trip down memory lane. But, there is potential for limited boutique products.

The link to github where you can find Steve's work:
https://github.com/Steve-Teal/eforth-misc16?fbclid=IwAR1lXH75fQtrtZQnqXxHI0ondFQuHcXUG6wa3G3V2XKNTVPWfhMiVzZcIzQ

The link to the starting article by Douglas Jones where the link to Steve's work has been added as well.
http://homepage.cs.uiowa.edu/~jones/arch/risc/

On Sunday, January 30, 2022 at 6:53:46 PM UTC+10, jpit...@gmail.com wrote:
> On Friday, 28 January 2022 at 18:01:56 UTC, Wayne morellini wrote:
> > On Saturday, January 29, 2022 at 2:09:28 AM UTC+10, jpit...@gmail.com wrote:
> > > On Friday, 28 January 2022 at 14:32:37 UTC, Wayne morellini wrote:
> > > > On Wednesday, January 26, 2022 at 9:11:30 PM UTC+10, jpit...@gmail.com wrote:
> > > > > On Wednesday, 26 January 2022 at 10:09:31 UTC, Paul Rubin wrote:
> > > > > > Wayne morellini <waynemo...@gmail.com> writes:
> > > > ..
> > > > > This whole MISC16 project started in CPLD at the time, 25 years ago,
> > > > > AND WAS RUNNING FORTH THEN
> > > > > and is now in FPGA on github running an adapted eForth.
> > > > > Thanks to Steve.
> > > > > I was in ASIC at the time, and just want to find out if there is a way to get it into ASIC,
> > > > > and what the performance would be now
> > > > > and what the cost would be.
> > > > > i MIGHT FIND A SPARE CORNER ON AN MPW FOR THESE 2500 GATES ...
> > > > > No real BUSINESS requirement, as the FPGA is there now and flexible to mess around with if wanted.
> > > > >
> > > > > There was an ASIC already at the time, using a modified design, manufactured at AMS in Austria as a student's final project.
> > >
> > > > So, what was the speed and energy that the CPLD was able to achieve, and where do I find information about misc16?
> > > >
> > > > Thanks.
> > > I was not involved in the ASIC as it was done at FH Nuremberg,
> > > so I assume nobody is available anymore to answer this.
> > > 25 years is a long time ...
> > > I had moved on,
> > > heard about the ASIC surprise about 5 years ago.
> > >
> > > Some part I have translated from a documentation, which was a surprise to me
> > >
> > > [1] The meaning of these values becomes particularly clear
> > > when this instruction is compared with the corresponding MOVE.W(An)+,Dn instruction of the Motorola MC68000 microprocessor,
> > > which requires 8 clock cycles with the same 16-bit data bus,
> > > or of the MC68008, which takes 16 clocks on an 8-bit data bus.
> > > It is noteworthy that an ADDC ((SP)), DR2 instruction, coded as 82H,A3H, is also executed in the same time or number of cycles.
> > > This command adds the operands addressed indirectly via the stack pointer to the contents of data register DR1,
> > > taking the carry flag into account,
> > > and stores the result in data register DR2 (see Table 1).
> > > The corresponding instruction of the MC68000 ADD (An),+,Dn needs 8 cycles, and that of the MC6008 16 cycles.
> > >
> > > The link to the current implementation of MISC16 is at
> > > https://github.com/Steve-Teal/eforth-misc16
> > > so you can do your own.
>
> > I see (except how the 68000 relates to this) but am too tired to read through this (and Steve's lost the link to the original paper). I used memory functions on a hybrid approach for my 2 bit design proposal. It gets towards holding a cannon to your head relying on memory mapped functions eventually, but it's got its beauty. So, I thought you did a more reasonable version of Chuck's Misc. But you did mention 5 bit instructions. I must be missing something :) Time for bed.
> >
> > I'm just drawing up unique graphics modes for a retro project I shouldn't do, but intend to ask it's community if they would like to do it. But, it's so just there, while everything else is just waiting. The idea was, that an zx80/zx81 could have been a superior game console system if released in 1977, with a few simple circuitry changes made to graphics, with colour and multi colour modes added, 64KB ram (like the 1977 Bally Astrocade, in comparison) and higher resolution graphics,not to forget sound, and a rehashed IO scheme. Basically just how much it could be pushed in the period from 1977-1981 (a bit of flexibility). This is just a what could have been done instead, like tribute thing, as a very small surprise portable modern console shrinkage of what the circuit would look like back then, using a number of unique techniques. Unfortunately, the vector graphics mode is proving to be a pain in the butt, as I couldn't get to write the the design up at the time (likely answering Rick) and hence forgot many things (and working at a low level now). I'm trying to do simple alternatives to sprites, while dealing with clashes. Unfortunately, I bit off a bit much which would have been good to resolve while the design was fresh in my mind. Its intended to be an z80 and some custom circuitry in a asuc or programmable logic, trying not to emulate anything (as certain people into these things don't like that). However, I was interested in doing others after, and maybe use misc for them. That's why I was looking at your processor.
> >
> > We could then say, what would a misc system be like compared to the Atari 2600, other Atari's, Amiga/ST/Mega Drive (genesis). Am alternative to the Commodore 128, would be a commodore 64 integrated Vic-II chip with high res mode and 80 column text (even the Amstrad PCW's four green scale hires mode, was rather pleasing). Improved graphics technique and three+ banks of 64KB memory, with my bank window concept, in 1984. At least one bank is graphics processor mappable. The extensions are, maybe an extra bus for graphics, 16 sprites, higher resolution and more colour (320*200 8 bit or 640*200 4 bit, is 64,0000 bytes per buffer). The same architecture extended and a few simple extra graphic techniques. This would be a common platform for business and home, I'm two different cases, with more memory in the business model. Basically, non Dy much needed an Amiga or ST in business. The business range was not advanced enough, nor the home range, the Commodore Amiga saved them. Of you had designed an expandable common development target architecture, them the system could have expanded to 16 bit 6502 and 32 bit 6502, and really revised sales of PC's, vastly undercutting them and their graphics architecture (another potential upgrade). But, if you added misc to that, then, we could say, what could they have done instead of the Commodore Amiga, Atari ST, or Mega Drive (genesis) and use an arm like integrated circuit with simple graphics architecture, sound and IO. The Mega Drive would be a simpler target to compare too. It's unreal watching videos about the business development decisions made at all the top companies, that shook them out. It's obvious what thru should have done, and there were truckloads of golden opportunity moments that were rejected. Anyway, I had hoped to one day divert my attention to doing a misc type retro design with fancy graphics tech beyond the stuff here, that could have been done. This is an integrated chip design with all sorts of processing and graphics features able to be released in the 1970's, but as time goes by, expandable into a better and better, system during the 1980's. The design, suitable for MCU use today, not just a boutique product down memory lane. I understand now. Why they wanted Chuck to develop an 8 bit misc processor. For control purposes, with extended addressing, you can do quiet a lot. Anyway, enough of the trip down memory lane. But, there is potential for limited boutique products.
> The link to github where you can find Steve's work:
> https://github.com/Steve-Teal/eforth-misc16?fbclid=IwAR1lXH75fQtrtZQnqXxHI0ondFQuHcXUG6wa3G3V2XKNTVPWfhMiVzZcIzQ
>
> The link to the starting article by Douglas Jones where the link to Steve's work has been added as well.
> http://homepage.cs.uiowa.edu/~jones/arch/risc/

Thanks Jurgen, you're a gem!

On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:
> Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.

Syncing forth processor project threads.

On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:
> Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.

Sorry for the mispost before.

Syncing forth processor project threads.

On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:
> On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:
> > Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.
> Sorry for the mispost before.
> Syncing forth processor project threads.

Forth processor project

https://groups.google.com/g/comp.lang.forth/c/6adve-Z1ppU/m/ymmLagxEBwAJ

On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:
> On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:
> > On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:
> > > Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.
> > Sorry for the mispost before.
> > Syncing forth processor project threads.
> Forth processor project
>
> https://groups.google.com/g/comp.lang.forth/c/6adve-Z1ppU/m/ymmLagxEBwAJ

Well, people suggest FPGA'S, which are slow, power hungry and costly.

But, I'm more interested in something closer to a Sea of Gates Array. But, what about PLD and PLA to do a better mini forth processor than FPGA?

These things have a matrix which could be read like a read only memory. So, can a misc processor fit on one, and use the spare array points like a read only storage.

The other interesting thing I've noticed, is that there is no predefined matrix of gate product you can program to route a circuit, but there is a technology used in some FPGAs, which could enable that, by setting up resistance to define a current flow path. Allowing a programmable sea of gates product, and programmable memory, at higher performance lower energy, than FPGA's maybe. I can't remember the name of the technology. But, you should be able to design such a circuit with memresistor technology. There are potential ls there.

On Tuesday, September 13, 2022 at 8:42:18 PM UTC+10, Wayne morellini wrote:
> On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:
> > On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:
> > > On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:
> > > > Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.
> > > Sorry for the mispost before.
> > > Syncing forth processor project threads.
> > Forth processor project
> >
> > https://groups.google.com/g/comp.lang.forth/c/6adve-Z1ppU/m/ymmLagxEBwAJ

I still have not found a site which lists every fpga, or other programmable device, by performance, energy and size.

On Tuesday, September 13, 2022 at 6:42:18 AM UTC-4, Wayne morellini wrote:
> On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:
> > On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:
> > > On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:
> > > > Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.
> > > Sorry for the mispost before.
> > > Syncing forth processor project threads.
> > Forth processor project
> >
> > https://groups.google.com/g/comp.lang.forth/c/6adve-Z1ppU/m/ymmLagxEBwAJ
> Well, people suggest FPGA'S, which are slow, power hungry and costly.

People suggest FPGAs as design platforms for testing and evaluation of designs. But some people can't hear the voices of reason over their own screaming.

> But, I'm more interested in something closer to a Sea of Gates Array. But, what about PLD and PLA to do a better mini forth processor than FPGA?

Hmmm... I'll try to explain. PLD is a generic term that includes FPGA, but some people choose to use it for all devices that are not FPGAs. PLA has not been used for decades and no longer exist. It was an early form of PLD that died off quickly. There are numerous other terms that are either trademarks or simply not used or both. None of these terms are standardized other than FPGA (basic elements larger than a gate or FF) and CPLD (everything that's not an FPGA) which are used relatively consistently.

The devices that use smaller arrays of logic with more rigid interconnect are typically termed CPLD or SPLD. None of these are very suitable for what you are talking about doing. However, if Hugh were around, he would be quick to tell you the company he used to work for developed a stack processor on a CPLD with capability of executing multiple instructions per clock. A practical and useful feature when the instructions are so simple. With the large instruction word this is practical. Other designs which have a tiny opcode size may still have one instruction per word, or may combine multiple instructions into one instruction memory word, such as F18A, b16, etc.

To show you your bias against FPGAs is not based in reality, many CPLDs are actually organized internally as FPGAs. The CPLD nomenclature often is simply an indicator of the size of the device, rather than the architecture.

Check out some low power FPGAs and you may be surprised.

> These things have a matrix which could be read like a read only memory. So, can a misc processor fit on one, and use the spare array points like a read only storage.

Which PLD are you refering to? I'm not aware of any such PLD with logic that can be "read like a read only memory". Many PLDs include memory in several forms. Lattice is a company with a number of devices with internal RAM and Flash. Gowin is another.

> The other interesting thing I've noticed, is that there is no predefined matrix of gate product you can program to route a circuit, but there is a technology used in some FPGAs, which could enable that, by setting up resistance to define a current flow path. Allowing a programmable sea of gates product, and programmable memory, at higher performance lower energy, than FPGA's maybe. I can't remember the name of the technology. But, you should be able to design such a circuit with memresistor technology. There are potential ls there.

In ASICs, the gate interconnect is formed by a mask layer implementing metal interconnect. Sometimes they provide two layers for more flexibility. All PLDs have defined routing/interconnect and are programmed by either RAM which controls multiplexers or in some obsolete technologies, fuses, or in others, "anti-fuses".

No one is using memristor technology. I don't believe anyone has found an actual, practical application for memristors.

--

Rick C. (Lorem Ipsum)

---- Get 1,000 miles of free Supercharging
---- Tesla referral code - https://ts.la/richard11209

On Tuesday, September 13, 2022 at 6:45:38 AM UTC-4, Wayne morellini wrote:
> On Tuesday, September 13, 2022 at 8:42:18 PM UTC+10, Wayne morellini wrote:
> > On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:
> > > On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:
> > > > On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:
> > > > > Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.
> > > > Sorry for the mispost before.
> > > > Syncing forth processor project threads.
> > > Forth processor project
> > >
> > > https://groups.google.com/g/comp.lang.forth/c/6adve-Z1ppU/m/ymmLagxEBwAJ
> I still have not found a site which lists every fpga, or other programmable device, by performance, energy and size.

And you won't. There's no incentive for anyone to do that. Each manufacturer typically has a selection guide that provides basic info on each of their lines and devices. It helps if you know what you want.

--

Rick C. (Lorem Ipsum)

---+ Get 1,000 miles of free Supercharging
---+ Tesla referral code - https://ts.la/richard11209

On Wednesday, September 14, 2022 at 2:24:04 AM UTC+10, gnuarm.del...@gmail.com wrote:
> On Tuesday, September 13, 2022 at 6:45:38 AM UTC-4, Wayne morellini wrote:
> > On Tuesday, September 13, 2022 at 8:42:18 PM UTC+10, Wayne morellini wrote:
> > > On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:
> > > > On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:
> > > > > On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:
> > > > > > Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.
> > > > > Sorry for the mispost before.
> > > > > Syncing forth processor project threads.
> > > > Forth processor project
> > > >
> > > > https://groups.google.com/g/comp.lang.forth/c/6adve-Z1ppU/m/ymmLagxEBwAJ
> > I still have not found a site which lists every fpga, or other programmable device, by performance, energy and size.
> And you won't. There's no incentive for anyone to do that. Each manufacturer typically has a selection guide that provides basic info on each of their lines and devices. It helps if you know what you want.

Globalspecs

Lorem Ipsum

On Wednesday, September 14, 2022 at 2:22:54 AM UTC+10, gnuarm.del...@gmail.com wrote:
> On Tuesday, September 13, 2022 at 6:42:18 AM UTC-4, Wayne morellini wrote:
> > On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:
> > > On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:
> > > > On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:
...

Rick, than you for your generous straight forwards explanations and help below.

> Hmmm... I'll try to explain. PLD is a generic term that includes FPGA, but some people choose to use it for all devices that are not FPGAs. PLA has not been used for decades and no longer exist. It was an early form of PLD that died off quickly. There are numerous other terms that are either trademarks or simply not used or both. None of these terms are standardized other than FPGA (basic elements larger than a gate or FF) and CPLD (everything that's not an FPGA) which are used relatively consistently.

PAL and PLA use different technology architectures. I read one of these offers significance higher speed performance advantages over FPGA.

> The devices that use smaller arrays of logic with more rigid interconnect are typically termed CPLD or SPLD. None of these are very suitable for what you are talking about doing. However, if Hugh were around, he would be quick to tell you the company he used to work for developed a stack processor on a CPLD with capability of executing multiple instructions per

Yes, I think I remember, which was a sort of background thought here.

> clock. A practical and useful feature when the instructions are so simple.. With the large instruction word this is practical. Other designs which have a tiny opcode size may still have one instruction per word, or may combine multiple instructions into one instruction memory word, such as F18A, b16, etc.

Rigidity is not a problem, as you implement one design for use or sale, then there's GAL's, which were erasable.

The priority here, is if something on the level of b/p16 f18 like, can be fully implemented, at lower energy and higher speed then FPGA. My target energy envelope is really low for the performance. I'm not having success yet with an FPGA part anywhere near the target. No body has answered, these are the lowest energy FPGA's with enough gates for a single misc processor at significant performance, or simply, these are the lowest energy parts in the industry, so I can check if they have anything suitable in the range. I have found one or two low energy manufacturers but the are still 10-100 times too much energy.

I have done the figures for one of my lowest energy targets for year. But we are talking about <1 or 2mw. I would like to run something 168 hours on a 50-100mw battery, at either thousands of cycles to 10 million cycles, to hundreds of millions, to high speed, depending on the edition of the product from least capable up. This is also the sort of range to run parasitic power off of an RCA video plug for filter processing.

it's a matter of how long a piece of string being: as short as you can get and building implementation feature set up around that, as long as it comes under 1-2mw at at least 1000's of cycles, preferably at least 10 million.

> To show you your bias against FPGAs is not based in reality, many CPLDs are actually organized internally as FPGAs. The CPLD nomenclature often is simply an indicator of the size of the device, rather than the architecture.

I'm aware of some of these things. Apparently there are three or four technology architectures now, where regard only sea of gates implementations as true FPGA. None. Ones out of an array of simple programmable logic devices (the cpld version).

> Check out some low power FPGAs and you may be surprised.

Couldn't find one yet.

> > These things have a matrix which could be read like a read only memory. So, can a misc processor fit on one, and use the spare array points like a read only storage.
> Which PLD are you refering to? I'm not aware of any such PLD with logic that can be "read like a read only memory". Many PLDs include memory in several forms. Lattice is a company with a number of devices with internal RAM and Flash. Gowin is another.

PAL, PLA. I'm not saying they work the same way as common ROM does, but they use a matric for sum of products calculations, which could be something to explore.

> In ASICs, the gate interconnect is formed by a mask layer implementing metal interconnect. Sometimes they provide two layers for more flexibility. All PLDs have defined routing/interconnect and are programmed by either RAM which controls multiplexers or in some obsolete technologies, fuses, or in others, "anti-fuses".
>
> No one is using memristor technology. I don't believe anyone has found an actual, practical application for memristors.

Maybe my memory is failing me. I thought memresistor was available on low energy processor node at one of the top foundry companies. Anyway, efpga I think it was, used some sort of technology that I mentioned.
>
> --
>
> Rick C..
>
> ---- Get 1,000 miles of free Supercharging
> ---- Tesla referral code - https://ts.la/richard11209

Thank you

Wayne

On Wednesday, September 14, 2022 at 10:34:36 AM UTC+10, Wayne morellini wrote:
> On Wednesday, September 14, 2022 at 2:22:54 AM UTC+10, gnuarm.del...@gmail.com wrote:
> > On Tuesday, September 13, 2022 at 6:42:18 AM UTC-4, Wayne morellini wrote:
> > > On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:
> > > > On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:
> > > > > On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:
...
> Maybe my memory is failing me. I thought memresistor was available on low energy processor node at one of the top foundry companies. Anyway, efpga I think it was, used some sort of technology that I mentioned.

Sorry, I got that wrong Rick, that's embedded fpga. Common antifuses operate like that, but aren't reprogrammable.

https://en.m.wikipedia.org/wiki/Antifuse

It's says that they are still commonly used, and may offer some speed advantage.

Sorry, still recovering here. Hard to write.

Thanks

Wayne.

>
> >
> > --
> >
> > Rick C..
> >
> > ---- Get 1,000 miles of free Supercharging
> > ---- Tesla referral code - https://ts.la/richard11209
> Thank you
>
> Wayne

On Tuesday, September 13, 2022 at 5:45:38 AM UTC-5, Wayne morellini wrote:
> On Tuesday, September 13, 2022 at 8:42:18 PM UTC+10, Wayne morellini wrote:
> > On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:
> > > On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:
> > > > On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:
> > > > > Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.
> > > > Sorry for the mispost before.
> > > > Syncing forth processor project threads.
> > > Forth processor project
> > >
> > > https://groups.google.com/g/comp.lang.forth/c/6adve-Z1ppU/m/ymmLagxEBwAJ
> I still have not found a site which lists every fpga, or other programmable device, by performance, energy and size.

A partial list is at:
https://github.com/jimbrake/FPGA-parts-with-free-tools
A more extensive list is available.
Lists a mm dimension of smallest part.
Have not included any performance info other than fabrication node.
Generallly, you need to run your design through the vendor's tools to get a power estimate.
https://github.com/jimbrake/cpu_soft_cores gives some indication of performance.
The fastest devices generally use the latest fab node and cost more than slower parts.

On Tuesday, September 13, 2022 at 7:35:14 PM UTC-4, Wayne morellini wrote:
> On Wednesday, September 14, 2022 at 2:24:04 AM UTC+10, gnuarm.del...@gmail.com wrote:
> > On Tuesday, September 13, 2022 at 6:45:38 AM UTC-4, Wayne morellini wrote:
> > > On Tuesday, September 13, 2022 at 8:42:18 PM UTC+10, Wayne morellini wrote:
> > > > On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:
> > > > > On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:
> > > > > > On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:
> > > > > > > Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.
> > > > > > Sorry for the mispost before.
> > > > > > Syncing forth processor project threads.
> > > > > Forth processor project
> > > > >
> > > > > https://groups.google.com/g/comp.lang.forth/c/6adve-Z1ppU/m/ymmLagxEBwAJ
> > > I still have not found a site which lists every fpga, or other programmable device, by performance, energy and size.
> > And you won't. There's no incentive for anyone to do that. Each manufacturer typically has a selection guide that provides basic info on each of their lines and devices. It helps if you know what you want.
> Globalspecs
>
> Lorem Ipsum

So did they show you want you wanted?

I think not, because they only cover the products they are paid to advertise. LOL

--

Rick C. (Lorem Ipsum)

--+- Get 1,000 miles of free Supercharging
--+- Tesla referral code - https://ts.la/richard11209

On Tuesday, September 13, 2022 at 8:34:36 PM UTC-4, Wayne morellini wrote:
> On Wednesday, September 14, 2022 at 2:22:54 AM UTC+10, gnuarm.del...@gmail.com wrote:
> > On Tuesday, September 13, 2022 at 6:42:18 AM UTC-4, Wayne morellini wrote:
> > > On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:
> > > > On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:
> > > > > On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:
> ..
>
> Rick, than you for your generous straight forwards explanations and help below.
> > Hmmm... I'll try to explain. PLD is a generic term that includes FPGA, but some people choose to use it for all devices that are not FPGAs. PLA has not been used for decades and no longer exist. It was an early form of PLD that died off quickly. There are numerous other terms that are either trademarks or simply not used or both. None of these terms are standardized other than FPGA (basic elements larger than a gate or FF) and CPLD (everything that's not an FPGA) which are used relatively consistently.
> PAL and PLA use different technology architectures. I read one of these offers significance higher speed performance advantages over FPGA.

Perhaps I did not explain it clearly. PAL IS A TRADEMARK, NOT A TECHNOLOGY.. NO ONE MAKES PLAs OF ANY VALUE IF AT ALL.

> > The devices that use smaller arrays of logic with more rigid interconnect are typically termed CPLD or SPLD. None of these are very suitable for what you are talking about doing. However, if Hugh were around, he would be quick to tell you the company he used to work for developed a stack processor on a CPLD with capability of executing multiple instructions per
> Yes, I think I remember, which was a sort of background thought here.
> > clock. A practical and useful feature when the instructions are so simple. With the large instruction word this is practical. Other designs which have a tiny opcode size may still have one instruction per word, or may combine multiple instructions into one instruction memory word, such as F18A, b16, etc.
> Rigidity is not a problem, as you implement one design for use or sale, then there's GAL's, which were erasable.

Again, GAL is a trademark, not a technology. In general, GAL was a 24 pin 22V10. The part number means it had 22 I/Os, of which 10 could be outputs. Not very high complexity, SPLD.

> The priority here, is if something on the level of b/p16 f18 like, can be fully implemented, at lower energy and higher speed then FPGA.

We've had this discussion before. I believe you are putting the cart before the horse by focusing on silicon implementation before the architecture. I would hash out a design in an FPGA to get it working. Then worry about minimizing power consumption by using an ASIC.

But it doesn't matter. I've explained the reasons before.

> My target energy envelope is really low for the performance. I'm not having success yet with an FPGA part anywhere near the target. No body has answered, these are the lowest energy FPGA's with enough gates for a single misc processor at significant performance, or simply, these are the lowest energy parts in the industry, so I can check if they have anything suitable in the range. I have found one or two low energy manufacturers but the are still 10-100 times too much energy.

I don't recall you ever specifying a target power level.

> I have done the figures for one of my lowest energy targets for year. But we are talking about <1 or 2mw. I would like to run something 168 hours on a 50-100mw battery, at either thousands of cycles to 10 million cycles, to hundreds of millions, to high speed, depending on the edition of the product from least capable up. This is also the sort of range to run parasitic power off of an RCA video plug for filter processing.

You say 1 or 2 mW, but you don't give a performance figure. When you say "cycles", what is that? It's not MIPS, it's not MHz. What is it?

> it's a matter of how long a piece of string being: as short as you can get and building implementation feature set up around that, as long as it comes under 1-2mw at at least 1000's of cycles, preferably at least 10 million..
> > To show you your bias against FPGAs is not based in reality, many CPLDs are actually organized internally as FPGAs. The CPLD nomenclature often is simply an indicator of the size of the device, rather than the architecture.
> I'm aware of some of these things. Apparently there are three or four technology architectures now, where regard only sea of gates implementations as true FPGA. None. Ones out of an array of simple programmable logic devices (the cpld version).
> > Check out some low power FPGAs and you may be surprised.
> Couldn't find one yet.

Where have you looked?

> > > These things have a matrix which could be read like a read only memory. So, can a misc processor fit on one, and use the spare array points like a read only storage.
> > Which PLD are you refering to? I'm not aware of any such PLD with logic that can be "read like a read only memory". Many PLDs include memory in several forms. Lattice is a company with a number of devices with internal RAM and Flash. Gowin is another.
> PAL, PLA. I'm not saying they work the same way as common ROM does, but they use a matric for sum of products calculations, which could be something to explore.

The "matrix" is a set of interconnects feeding AND gates and connecting the AND gate outputs which are hardwired to the OR gates. There's no memory of any type you can use.

> > In ASICs, the gate interconnect is formed by a mask layer implementing metal interconnect. Sometimes they provide two layers for more flexibility. All PLDs have defined routing/interconnect and are programmed by either RAM which controls multiplexers or in some obsolete technologies, fuses, or in others, "anti-fuses".
> >
> > No one is using memristor technology. I don't believe anyone has found an actual, practical application for memristors.
> Maybe my memory is failing me. I thought memresistor was available on low energy processor node at one of the top foundry companies. Anyway, efpga I think it was, used some sort of technology that I mentioned.

If so, please educate me. No, I don't care, because I'm not designing any ASICs.

--

Rick C. (Lorem Ipsum)

--++ Get 1,000 miles of free Supercharging
--++ Tesla referral code - https://ts.la/richard11209

On Tuesday, September 13, 2022 at 9:11:14 PM UTC-4, James Brakefield wrote:
> On Tuesday, September 13, 2022 at 5:45:38 AM UTC-5, Wayne morellini wrote:
> > On Tuesday, September 13, 2022 at 8:42:18 PM UTC+10, Wayne morellini wrote:
> > > On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:
> > > > On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:
> > > > > On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:
> > > > > > Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.
> > > > > Sorry for the mispost before.
> > > > > Syncing forth processor project threads.
> > > > Forth processor project
> > > >
> > > > https://groups.google.com/g/comp.lang.forth/c/6adve-Z1ppU/m/ymmLagxEBwAJ
> > I still have not found a site which lists every fpga, or other programmable device, by performance, energy and size.
> A partial list is at:
> https://github.com/jimbrake/FPGA-parts-with-free-tools
> A more extensive list is available.
> Lists a mm dimension of smallest part.
> Have not included any performance info other than fabrication node.
> Generallly, you need to run your design through the vendor's tools to get a power estimate.
> https://github.com/jimbrake/cpu_soft_cores gives some indication of performance.
> The fastest devices generally use the latest fab node and cost more than slower parts.

The only low power FPGAs I know of are CoolRunner II from Xilinx which are really CPLDs and can get very pricey, ice40 from Lattice and parts from Gowin.

I don't recall details on the Gowin parts, but the Lattice parts have ~100 uA static current and a low ramp of dynamic power.

The CoolRunner II parts aren't very useful for more complex designs because they are CPLDs and the die size increases rapidly with the number of elements, meaning high $$$.

--

Rick C. (Lorem Ipsum)

-+-- Get 1,000 miles of free Supercharging
-+-- Tesla referral code - https://ts.la/richard11209

On Wednesday, September 14, 2022 at 11:30:33 AM UTC+10, gnuarm.del...@gmail..com wrote:
> On Tuesday, September 13, 2022 at 7:35:14 PM UTC-4, Wayne morellini wrote:
> > On Wednesday, September 14, 2022 at 2:24:04 AM UTC+10, gnuarm.del...@gmail.com wrote:
> > > On Tuesday, September 13, 2022 at 6:45:38 AM UTC-4, Wayne morellini wrote:
> > > > On Tuesday, September 13, 2022 at 8:42:18 PM UTC+10, Wayne morellini wrote:
> > > > > On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:
> > > > > > On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:
> > > > > > > On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:
> > > > > > > > Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.
> > > > > > > Sorry for the mispost before.
> > > > > > > Syncing forth processor project threads.
> > > > > > Forth processor project
> > > > > >
> > > > > > https://groups.google.com/g/comp.lang.forth/c/6adve-Z1ppU/m/ymmLagxEBwAJ
> > > > I still have not found a site which lists every fpga, or other programmable device, by performance, energy and size.
> > > And you won't. There's no incentive for anyone to do that. Each manufacturer typically has a selection guide that provides basic info on each of their lines and devices. It helps if you know what you want.
> > Globalspecs
> >
> > Lorem Ipsum
> So did they show you want you wanted?
>
> I think not, because they only cover the products they are paid to advertise. LOL
> --
>
> Rick C. (Lorem Ipsum)
> --+- Get 1,000 miles of free Supercharging
> --+- Tesla referral code - https://ts.la/richard11209

I saw it last night after, but have to get to sign up. The thing is, that I've know about parts lists and book before. So, there might be that there is an FPGA list. Specialist sites tend to do that, like specific technology information and news sites. That's an idea I haven't thought about.

On Wednesday, September 14, 2022 at 11:50:53 AM UTC+10, gnuarm.del...@gmail..com wrote:
> On Tuesday, September 13, 2022 at 8:34:36 PM UTC-4, Wayne morellini wrote:
> > On Wednesday, September 14, 2022 at 2:22:54 AM UTC+10, gnuarm.del...@gmail.com wrote:
> > > On Tuesday, September 13, 2022 at 6:42:18 AM UTC-4, Wayne morellini wrote:
> > > > On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:
> > > > > On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:
> > > > > > On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:
> > ..
> >
> > Rick, than you for your generous straight forwards explanations and help below.
> > > Hmmm... I'll try to explain. PLD is a generic term that includes FPGA, but some people choose to use it for all devices that are not FPGAs. PLA has not been used for decades and no longer exist. It was an early form of PLD that died off quickly. There are numerous other terms that are either trademarks or simply not used or both. None of these terms are standardized other than FPGA (basic elements larger than a gate or FF) and CPLD (everything that's not an FPGA) which are used relatively consistently.
> > PAL and PLA use different technology architectures. I read one of these offers significance higher speed performance advantages over FPGA.
> Perhaps I did not explain it clearly. PAL IS A TRADEMARK, NOT A TECHNOLOGY. NO ONE MAKES PLAs OF ANY VALUE IF AT ALL.

Now Rick, you don't have to get off key. You did say they hadn't been used for decades before,

Wikipedia describes PAL as fixed OR, programmable AND combination and PLA as programmable OR and AND, which slows it down, and looking around on line it is more expensive to make, but has higher density devices. I also see that PAL is said to be very common.

https://en.m.wikipedia.org/wiki/Programmable_logic_device

GAL.is a reprgammable version of PAL.

> > The priority here, is if something on the level of b/p16 f18 like, can be fully implemented, at lower energy and higher speed then FPGA.
> We've had this discussion before. I believe you are putting the cart before the horse by focusing on silicon implementation before the architecture. I would hash out a design in an FPGA to get it working. Then worry about minimizing power consumption by using an ASIC.

We have architectures worked out and tested already. Now, seeking right horse to pull it.

>
> But it doesn't matter. I've explained the reasons before.
> > My target energy envelope is really low for the performance. I'm not having success yet with an FPGA part anywhere near the target. No body has answered, these are the lowest energy FPGA's with enough gates for a single misc processor at significant performance, or simply, these are the lowest energy parts in the industry, so I can check if they have anything suitable in the range. I have found one or two low energy manufacturers but the are still 10-100 times too much energy.
> I don't recall you ever specifying a target power level.

Why do you think I'm looking for the lowest energy performance parts and then see which applications I have can fit? I asked very simple advice often, but usually never get answers.

> > I have done the figures for one of my lowest energy targets for year. But we are talking about <1 or 2mw. I would like to run something 168 hours on a 50-100mw battery, at either thousands of cycles to 10 million cycles, to hundreds of millions, to high speed, depending on the edition of the product from least capable up. This is also the sort of range to run parasitic power off of an RCA video plug for filter processing.
> You say 1 or 2 mW, but you don't give a performance figure. When you say "cycles", what is that? It's not MIPS, it's not MHz. What is it?

End cycles of course. In misc cycles and instructions are often the same, but in progress htammable logic that is not necessarily possible.

> > it's a matter of how long a piece of string being: as short as you can get and building implementation feature set up around that, as long as it comes under 1-2mw at at least 1000's of cycles, preferably at least 10 million.
> > > To show you your bias against FPGAs is not based in reality, many CPLDs are actually organized internally as FPGAs. The CPLD nomenclature often is simply an indicator of the size of the device, rather than the architecture.
> > I'm aware of some of these things. Apparently there are three or four technology architectures now, where regard only sea of gates implementations as true FPGA. None. Ones out of an array of simple programmable logic devices (the cpld version).
> > > Check out some low power FPGAs and you may be surprised.
> > Couldn't find one yet.
> Where have you looked?

With everything that is going on over here, but no real answers, done summaries to get an idea where to look, Wikipedia (ugh) magnetic computing related site, but those FPGA's appears to not have come out, and probably are not the best architecture. Don't have time with people siendimg a thousand times on other things than saying these are the things you are looking for over there. Instead of these are the things I want to say, look over here. The confidential commercial nature means I keep it to myself, and ask relevant questions, not that people not privileged to the commercial process have to question questions and dictate. I could come along and say a lot about people's projects and businesses, and be correct, but that's not my business, I'm not a potential customer or that they are destroying society, community or life, it's their business. If they ask questions, and I can give relevant beneficial answers, ok. If I have to spend more time on noise than I would wrecking my life trying to find answers on google. As it is I've had to do both. Where do I send the lawyers. People are asked answers to make life simpler than it could be, by community simpler consciousness (collective knowledge). :)

...
> The "matrix" is a set of interconnects feeding AND gates and connecting the AND gate outputs which are hardwired to the OR gates. There's no memory of any type you can use.

Deterministic results from deterministic inputs.

> > > No one is using memristor technology. I don't believe anyone has found an actual, practical application for memristors.
> > Maybe my memory is failing me. I thought memresistor was available on low energy processor node at one of the top foundry companies. Anyway, efpga I think it was, used some sort of technology that I mentioned.
> If so, please educate me. No, I don't care, because I'm not designing any ASICs.

I posted it before.

On Wednesday, September 14, 2022 at 11:55:54 AM UTC+10, gnuarm.del...@gmail..com wrote:
> On Tuesday, September 13, 2022 at 9:11:14 PM UTC-4, James Brakefield wrote:
> > On Tuesday, September 13, 2022 at 5:45:38 AM UTC-5, Wayne morellini wrote:
> > > On Tuesday, September 13, 2022 at 8:42:18 PM UTC+10, Wayne morellini wrote:
> > > > On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:
> > > > > On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:
> > > > > > On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:
> > > > > > > Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.
> > > > > > Sorry for the mispost before.
> > > > > > Syncing forth processor project threads.
> > > > > Forth processor project
> > > > >
> > > > > https://groups.google.com/g/comp.lang.forth/c/6adve-Z1ppU/m/ymmLagxEBwAJ
> > > I still have not found a site which lists every fpga, or other programmable device, by performance, energy and size.
> > A partial list is at:
> > https://github.com/jimbrake/FPGA-parts-with-free-tools
> > A more extensive list is available.
> > Lists a mm dimension of smallest part.
> > Have not included any performance info other than fabrication node.
> > Generallly, you need to run your design through the vendor's tools to get a power estimate.
> > https://github.com/jimbrake/cpu_soft_cores gives some indication of performance.
> > The fastest devices generally use the latest fab node and cost more than slower parts.
> The only low power FPGAs I know of are CoolRunner II from Xilinx which are really CPLDs and can get very pricey, ice40 from Lattice and parts from Gowin.
>
> I don't recall details on the Gowin parts, but the Lattice parts have ~100 uA static current and a low ramp of dynamic power.
>
> The CoolRunner II parts aren't very useful for more complex designs because they are CPLDs and the die size increases rapidly with the number of elements, meaning high $$$.
> --
>
> Rick C. (Lorem Ipsum)
> -+-- Get 1,000 miles of free Supercharging
> -+-- Tesla referral code - https://ts.la/richard11209

Thank you Rick.

Quicklogic anti-fuse, and this article talks about 20 µA .

https://www.renesas.com/tw/en/blogs/new-era-programmable-logic
https://www.renesas.com/tw/en/products/programmable-mixed-signal-asic-ip-products/forgefpga-low-density-fpgas#document

Though, how could you possibly tell the maximum performance of a full design from the site any current?

Thanks again Rick.