Concerning the video filter project.

Well, I spent some time trying to find a one or two pin serial native
speed ram memory standard, or flash with ram at similar performance.
But, so painfully close yet so far away. There is opportunity to have a
single pin request and full word return at over 2GB/s, but the embedded
space seems to be limited to frequencies like 133Mhz plus serially fed
in, which will be pretty slow to handle video. There is a hardware support
in i3c I think to have an on chip interface to read in and output data on
parallel, and transfer that over serial automatically, and tri bit interfacing.
But. It looks lr the I industry abandoned phase shift modulation of data
past 4 phase, I'm favour of differential line pairs. Being sick, I wasn't
aware of this. It's amazing at how fast they are pushing the data rate
now with that. When I was studying, anything 100Mhz was dicey, and
over 200mhz, was an issue. The latest physical layer for mobile
embedded is over 20Gb/s. But, this means that at low energy processor
speeds, you could have a two pin interface on the smallest chip, to
execute from memory, by serialising the transaction by overclocking just
the interface section, and hook up a number of other chips. With
phase/frequency shift keying, you could get 16 bits of shift, making
a single cycle parralel princess on a pin. All stuff perfect for the
embedded industry and low pin count.

I also looked up the 1 transistor parasitic dram technology, perfect for
Pseudo SRAM modules. But. It appears to have gone silent. It was
nearly as quick as sram, low energy, higher density, but had some cost.
Around the time, 2 transistor thyresistor ram was announced, and AMD
signed up a deal. Which is just as good. These memories might just
matter generally, but are good for the embedded space.

It turns out thyresistor is at TSMC on 32 and maybe 22nm processes.
That's good news.

I also found that Intel has an onboard serial bus standard. That could
have parts for video output. Ultra low cost is the issue here. Unless I
can keep costs closer to the dollar, it will be less desirable. A way to
pass the video signal through hardly touched, or read it, is another option.

On Tuesday, July 19, 2022 at 9:11:15 AM UTC+10, Wayne morellini wrote:
> Concerning the video filter project.
>
> Well, I spent some time trying to find a one or two pin serial native
> speed ram memory standard, or flash with ram at similar performance.
> But, so painfully close yet so far away. There is opportunity to have a
> single pin request and full word return at over 2GB/s, but the embedded
> space seems to be limited to frequencies like 133Mhz plus serially fed
> in, which will be pretty slow to handle video. There is a hardware support
> in i3c I think to have an on chip interface to read in and output data on
> parallel, and transfer that over serial automatically, and tri bit interfacing.
> But. It looks lr the I industry abandoned phase shift modulation of data
> past 4 phase, I'm favour of differential line pairs. Being sick, I wasn't
> aware of this. It's amazing at how fast they are pushing the data rate
> now with that. When I was studying, anything 100Mhz was dicey, and
> over 200mhz, was an issue. The latest physical layer for mobile
> embedded is over 20Gb/s. But, this means that at low energy processor
> speeds, you could have a two pin interface on the smallest chip, to
> execute from memory, by serialising the transaction by overclocking just
> the interface section, and hook up a number of other chips. With
> phase/frequency shift keying, you could get 16 bits of shift, making
> a single cycle parralel princess on a pin. All stuff perfect for the
> embedded industry and low pin count.
>
> I also looked up the 1 transistor parasitic dram technology, perfect for
> Pseudo SRAM modules. But. It appears to have gone silent. It was
> nearly as quick as sram, low energy, higher density, but had some cost.
> Around the time, 2 transistor thyresistor ram was announced, and AMD
> signed up a deal. Which is just as good. These memories might just
> matter generally, but are good for the embedded space.
>
> It turns out thyresistor is at TSMC on 32 and maybe 22nm processes.
> That's good news.
>
> I also found that Intel has an onboard serial bus standard. That could
> have parts for video output. Ultra low cost is the issue here. Unless I
> can keep costs closer to the dollar, it will be less desirable. A way to
> pass the video signal through hardly touched, or read it, is another option.

Syncing video filter project threads.

On Sunday, September 4, 2022 at 3:15:19 PM UTC+10, Wayne morellini wrote:
> On Tuesday, July 19, 2022 at 9:11:15 AM UTC+10, Wayne morellini wrote:
> > Concerning the video filter project.
> >
> > Well, I spent some time trying to find a one or two pin serial native
> > speed ram memory standard, or flash with ram at similar performance.
> > But, so painfully close yet so far away. There is opportunity to have a
> > single pin request and full word return at over 2GB/s, but the embedded
> > space seems to be limited to frequencies like 133Mhz plus serially fed
> > in, which will be pretty slow to handle video. There is a hardware support
> > in i3c I think to have an on chip interface to read in and output data on
> > parallel, and transfer that over serial automatically, and tri bit interfacing.
> > But. It looks lr the I industry abandoned phase shift modulation of data
> > past 4 phase, I'm favour of differential line pairs. Being sick, I wasn't
> > aware of this. It's amazing at how fast they are pushing the data rate
> > now with that. When I was studying, anything 100Mhz was dicey, and
> > over 200mhz, was an issue. The latest physical layer for mobile
> > embedded is over 20Gb/s. But, this means that at low energy processor
> > speeds, you could have a two pin interface on the smallest chip, to
> > execute from memory, by serialising the transaction by overclocking just
> > the interface section, and hook up a number of other chips. With
> > phase/frequency shift keying, you could get 16 bits of shift, making
> > a single cycle parralel princess on a pin. All stuff perfect for the
> > embedded industry and low pin count.
> >
> > I also looked up the 1 transistor parasitic dram technology, perfect for
> > Pseudo SRAM modules. But. It appears to have gone silent. It was
> > nearly as quick as sram, low energy, higher density, but had some cost.
> > Around the time, 2 transistor thyresistor ram was announced, and AMD
> > signed up a deal. Which is just as good. These memories might just
> > matter generally, but are good for the embedded space.
> >
> > It turns out thyresistor is at TSMC on 32 and maybe 22nm processes.
> > That's good news.
> >
> > I also found that Intel has an onboard serial bus standard. That could
> > have parts for video output. Ultra low cost is the issue here. Unless I
> > can keep costs closer to the dollar, it will be less desirable. A way to
> > pass the video signal through hardly touched, or read it, is another option.
> Syncing video filter project threads.

Video filter project

https://groups.google.com/g/comp.lang.forth/c/S-_qe2Kh6gk/m/6DH2cIxEBwAJ