In 2020 the noforth team (Albert Nijhof and Willem Ouwerkerk)
has made a 32 bit noforth for the risc-V .
Latest official version : mid 2021
Subject: Join the risc-V bandwagon!
X-Newsreader: trn 4.0-test77 (Sep 1, 2010)

I have now a DshangNezha STU board on my desk with a tinalinux
running right of the box. 64 bits 1 Ghz .5 Gbyte.

The first stage of porting ciforth succeed, the assembler source
gives no errors on cross assembling.

Riscv is in the long run to obliterate Intel AMD and ARM, because
it is royalty free, such that Chinese companies can no longer be
strong armed. The smaller ARM royalties has had already an impact.

The Orange pi came with a 1000 page manual of the Soc and
schematics. Nezha goes a step further. They supply the design
and gerber files such that you have your own boards manufactured.
I had no problem running tmanx (instrument control) on the
Orange pi, and turning on leds is much easier than with
Python.

What are you doing? Has gforth been checked out on rics V linux
boards?

Groetjes Albert
--
Don't praise the day before the evening. One swallow doesn't make
spring. You must not say "hey" before you have crossed the bridge.
Don't sell the hide of the bear until you shot it. Better one bird in
the hand than ten in the air. - the Wise from Antrim -

> Riscv is in the long run to obliterate Intel AMD and ARM, because
> it is royalty free, such that Chinese companies can no longer be
> strong armed. The smaller ARM royalties has had already an impact.

Competition is good. At the moment RISC V boards still are expensive
compared to ARM-based ones.

In article <19664fe2-596e-43bf-9d70-7ad207fb33edn@googlegroups.com>,
Zbig <zbigniew2011@gmail.com> wrote:
>> Riscv is in the long run to obliterate Intel AMD and ARM, because
>> it is royalty free, such that Chinese companies can no longer be
>> strong armed. The smaller ARM royalties has had already an impact.
>
>Competition is good. At the moment RISC V boards still are expensive
>compared to ARM-based ones.

The board I have costs 17 dollars plus shipping. 64 bit 1 Ghz.
Not an expensive hobby.

Groetjes Albert
--
Don't praise the day before the evening. One swallow doesn't make
spring. You must not say "hey" before you have crossed the bridge.
Don't sell the hide of the bear until you shot it. Better one bird in
the hand than ten in the air. - the Wise from Antrim -

On Wednesday, January 11, 2023 at 6:05:15 AM UTC-5, Zbig wrote:
> > Riscv is in the long run to obliterate Intel AMD and ARM, because
> > it is royalty free, such that Chinese companies can no longer be
> > strong armed. The smaller ARM royalties has had already an impact.
> Competition is good. At the moment RISC V boards still are expensive
> compared to ARM-based ones.

I read an article by Sam Falvo on trying to make machine Forth for
RISC V and the instruction set seemed to require a lot of
instructions per Forth primitive. Is that the "state of the art" for
"risc".

I am wondering how the Netherlands team found RISC V handled Forth?
Is the source available to be reviewed?

> The board I have costs 17 dollars plus shipping. 64 bit 1 Ghz.
> Not an expensive hobby.

Where it can be bought for 17 USD (+ shipping)?

Brian Fox <brian.fox@brianfox.ca> writes:
>I read an article by Sam Falvo on trying to make machine Forth for
>RISC V and the instruction set seemed to require a lot of
>instructions per Forth primitive. Is that the "state of the art" for
>"risc".

RISC-V and ARM A64 (aka Aarch64) are both RISCs in my book (they are
load/store architectures), but follow quite different design
philosophies.

ARM A64 has 32-bit wide instructions and puts as much functionality in
as fits and fits the basic RISC principles, sometimes crossing the
border. It does not try for minimal implementation, ARM has another
instruction set (T32/A32, the 32-bit ARM instruction set with Thumb2
compression) for that.

By contrast, RISC-V tends to keep instructions minimal, supports a
compressed extension (that supports common instructions in 16 bits in
addition to the 32-bit encoding for all instructions), allowing for
smaller minimal implementations; for more sophisticated
implementations, the idea is that the instruction decoder combines
instructions into more capable microinstructions (sometimes called
macroinstructions because they are actually larger than the
architectural instructions). But of course you don't see that on the
architectural level. E.g., here's gforth-fast's +:

RISC-V ARM A64 AMD64 RTL
ld a5,$8(s8) ldr x0, [x25,#0x8]! tmp = load(SP+8)
addi s10,s10,8 add x26, x26, #0x8 add r13,$08 IP = IP+8
addi s8,s8,8 add r15,$08 SP = SP+8
add s7,s7,a5 add x27, x0, x27 add r8,[r15] TOS = TOS+tmp
ld a4,$-8(s10) ldur x1, [x26,#-0x8] mov rcx,-$08[r13] tmp = load(IP-8)
jr a4 br x1 jmp ecx jmp tmp

RTL is "register-transfer language", a pseudocode for describing
instructions. I use Forth virtual machine register names here.

I rearranged the AMD64 instructions to match the order of the others;
originally the first and second AMD64 instructions were swapped.

Here A64 combines the first and third instruction of the RISC-V code
in its first instruction. We wrote it such that the last two
instructions can be separated from the others, otherwise the compiler
would probably have combined the second A64 instruction with the ldur
into one instruction.

As a non-RISC, AMD64 has load-and-op instructions, as demonstrated by
combining the first and fourth RISC-V instruction into the third AMD64
instruction. AMD64 also could combine the last two instructions into
one, but gcc has not done that after gcc-2.95 (there for IA-32).

- anton
--
M. Anton Ertl http://www.complang.tuwien.ac.at/anton/home.html
comp.lang.forth FAQs: http://www.complang.tuwien.ac.at/forth/faq/toc.html
New standard: https://forth-standard.org/
EuroForth 2022: https://euro.theforth.net

On Wednesday, January 11, 2023 at 12:50:50 PM UTC-5, Anton Ertl wrote:
> Brian Fox <bria...@brianfox.ca> writes:
> >I read an article by Sam Falvo on trying to make machine Forth for
> >RISC V and the instruction set seemed to require a lot of
> >instructions per Forth primitive. Is that the "state of the art" for
> >"risc".
> RISC-V and ARM A64 (aka Aarch64) are both RISCs in my book (they are
> load/store architectures), but follow quite different design
> philosophies.
>
> ARM A64 has 32-bit wide instructions and puts as much functionality in
> as fits and fits the basic RISC principles, sometimes crossing the
> border. It does not try for minimal implementation, ARM has another
> instruction set (T32/A32, the 32-bit ARM instruction set with Thumb2
> compression) for that.
>
> By contrast, RISC-V tends to keep instructions minimal, supports a
> compressed extension (that supports common instructions in 16 bits in
> addition to the 32-bit encoding for all instructions), allowing for
> smaller minimal implementations; for more sophisticated
> implementations, the idea is that the instruction decoder combines
> instructions into more capable microinstructions (sometimes called
> macroinstructions because they are actually larger than the
> architectural instructions). But of course you don't see that on the
> architectural level. E.g., here's gforth-fast's +:
>
> RISC-V ARM A64 AMD64 RTL
> ld a5,$8(s8) ldr x0, [x25,#0x8]! tmp = load(SP+8)
> addi s10,s10,8 add x26, x26, #0x8 add r13,$08 IP = IP+8
> addi s8,s8,8 add r15,$08 SP = SP+8
> add s7,s7,a5 add x27, x0, x27 add r8,[r15] TOS = TOS+tmp
> ld a4,$-8(s10) ldur x1, [x26,#-0x8] mov rcx,-$08[r13] tmp = load(IP-8)
> jr a4 br x1 jmp ecx jmp tmp
>
> RTL is "register-transfer language", a pseudocode for describing
> instructions. I use Forth virtual machine register names here.
>
> I rearranged the AMD64 instructions to match the order of the others;
> originally the first and second AMD64 instructions were swapped.
>
> Here A64 combines the first and third instruction of the RISC-V code
> in its first instruction. We wrote it such that the last two
> instructions can be separated from the others, otherwise the compiler
> would probably have combined the second A64 instruction with the ldur
> into one instruction.
>
> As a non-RISC, AMD64 has load-and-op instructions, as demonstrated by
> combining the first and fourth RISC-V instruction into the third AMD64
> instruction. AMD64 also could combine the last two instructions into
> one, but gcc has not done that after gcc-2.95 (there for IA-32).
>
> - anton
> --
> M. Anton Ertl http://www.complang.tuwien.ac.at/anton/home.html
> comp.lang.forth FAQs: http://www.complang.tuwien.ac.at/forth/faq/toc.html
> New standard: https://forth-standard.org/
> EuroForth 2022: https://euro.theforth.net

Thanks Anton.

On Wednesday, January 11, 2023 at 11:12:03 AM UTC+1, none albert wrote:
> In 2020 the noforth team (Albert Nijhof and Willem Ouwerkerk)
> has made a 32 bit noforth for the risc-V .
> Latest official version : mid 2021
> Subject: Join the risc-V bandwagon!
> X-Newsreader: trn 4.0-test77 (Sep 1, 2010)
>
> I have now a DshangNezha STU board on my desk with a tinalinux
> running right of the box. 64 bits 1 Ghz .5 Gbyte.

Please, be more specific. "DshangNezha STU board" is something even Google
can't find.
"Join the risc-V bandwagon" is a thread that is unknown.

I know AN and WO, but I didn't know they added stack instructions to RISC-V
(AFAIK that is really possible). Or did you mean they ported noforth to a
specific RISC-V board?

-marcel

On Wednesday, January 11, 2023 at 8:29:15 PM UTC+1, Marcel Hendrix wrote:
> On Wednesday, January 11, 2023 at 11:12:03 AM UTC+1, none albert wrote:
[..]
> > I have now a DshangNezha STU board on my desk with a tinalinux
> > running right of the box. 64 bits 1 Ghz .5 Gbyte.
> Please, be more specific. "DshangNezha STU board" is something even Google
> can't find.
> "Join the risc-V bandwagon" is a thread that is unknown.
[..]
Wait, you meant "Sipeed Nezha 64bit RISC-V Linux Sbc Board,
Allwinner D1@1.0GHz, 1Gbyte DDR3, support for Tina/Debian System?"
But that board is $133, with $13.72 transportation cost, no power supply.

-marcel

In article <a133f174-0bcd-4b6b-b422-a1e26fb1ed24n@googlegroups.com>,
Brian Fox <brian.fox@brianfox.ca> wrote:
>On Wednesday, January 11, 2023 at 6:05:15 AM UTC-5, Zbig wrote:
>> > Riscv is in the long run to obliterate Intel AMD and ARM, because
>> > it is royalty free, such that Chinese companies can no longer be
>> > strong armed. The smaller ARM royalties has had already an impact.
>> Competition is good. At the moment RISC V boards still are expensive
>> compared to ARM-based ones.
>
>I read an article by Sam Falvo on trying to make machine Forth for
>RISC V and the instruction set seemed to require a lot of
>instructions per Forth primitive. Is that the "state of the art" for
>"risc".
>
>I am wondering how the Netherlands team found RISC V handled Forth?
>Is the source available to be reviewed?
>

It can be found by googling "noforth riscv".
https://home.hccnet.nl/anij/nof/noforth.html
These sources are gpl-ed. The source can be cross compiled by
win32forth (newest version). I tried gforth (the authors didn't)
and that does not yet work.

The ciforth source will be available as soon as it runs. (gpl).
Then it will be a mature Forth, because the tests are comprehensive
and the documentation (pdf ps info and html) is generated automatically.
Additions to the library probably takes some more time, especially
regarding i/o.

It took a few days to transform the arm source to riscv.
As mentioned the assembler accepts it without syntax errors.

Groetjes Albert
--
Don't praise the day before the evening. One swallow doesn't make
spring. You must not say "hey" before you have crossed the bridge.
Don't sell the hide of the bear until you shot it. Better one bird in
the hand than ten in the air. - the Wise from Antrim -

On Wed, 11 Jan 2023 11:29:13 -0800 (PST)
Marcel Hendrix <mhx@iae.nl> wrote:

> Please, be more specific. "DshangNezha STU board" is something even Google
> can't find.

The provessr is an Allwinner part (Their ARM SOCs were/are common in cheap tablets):

Dongshan Nezha STU devkit features Allwinner D1 RISC-V SoM/SBC
https://www.cnx-software.com/2022/03/25/dongshan-nezha-stu-devkit-features-allwinner-d1-risc-v-som-sbc/

More RISC-V boards:
https://riscv.org/exchanges/boards/

Jan Coombs
--

In article <46db7bb8-fe84-466c-898a-4a1e93714559n@googlegroups.com>,
Marcel Hendrix <mhx@iae.nl> wrote:
>On Wednesday, January 11, 2023 at 8:29:15 PM UTC+1, Marcel Hendrix wrote:
>> On Wednesday, January 11, 2023 at 11:12:03 AM UTC+1, none albert wrote:
>[..]
>> > I have now a DshangNezha STU board on my desk with a tinalinux
>> > running right of the box. 64 bits 1 Ghz .5 Gbyte.
>> Please, be more specific. "DshangNezha STU board" is something even Google
>> can't find.
>> "Join the risc-V bandwagon" is a thread that is unknown.
>[..]
>Wait, you meant "Sipeed Nezha 64bit RISC-V Linux Sbc Board,
>Allwinner D1@1.0GHz, 1Gbyte DDR3, support for Tina/Debian System?"
>But that board is $133, with $13.72 transportation cost, no power supply.

This is aliexpress : sorry for the long url.
https://www.aliexpress.com/item/1005004250215625.html?spm=a2g0o.productlist.main.25.643a469eojjM3I&algo_pvid=a14f42de-1088-49d7-86ba-3be3daa9aa25&algo_exp_id=a14f42de-1088-49d7-86ba-3be3daa9aa25-12&pdp_ext_f=%7B%22sku_id%22%3A%2212000029831944775%22%7D&pdp_npi=2%40dis%21EUR%2116.83%2116.83%21%21%21%21%21%402100b69816711052077171985d074b%2112000029831944775%21sea&curPageLogUid=E96plc0zRmyq

The cheapest board is 13 dollar with 7 dollar shipping.

I ordered the same board with a docking station for 30 dollar at
https://www.analoglamb.com/
You find the board under linux boards, not riscv boards.
I could not find Holland in the order form, I sent an e-mail and
promptly an e-mail came back with an advise to look up "Netherlands".

I payed with my visa card.

>
>-marcel

Groetjes Albert
--
Don't praise the day before the evening. One swallow doesn't make
spring. You must not say "hey" before you have crossed the bridge.
Don't sell the hide of the bear until you shot it. Better one bird in
the hand than ten in the air. - the Wise from Antrim -

> The cheapest board is 13 dollar with 7 dollar shipping.

But if I'm correct one also needs that „DIY base board” too?
Both in set (+porto) are a bit more than 40 USD.
Still not that expensive, I agree, but not 13 USD anymore.

Meanwhile I also found on Amazon:
https://www.amazon.com/dp/B0BGM1KQXQ/?coliid=I1VEL7EIZI6SRT&colid=BZJLTTL0P92I&psc=1&ref_=lv_ov_lig_dp_it
But this one sells at rather „normal” (for RISC V) price, unfortunately.

anton@mips.complang.tuwien.ac.at (Anton Ertl) writes:
> RISC-V
> ld a5,$8(s8)
> addi s10,s10,8
> addi s8,s8,8
> add s7,s7,a5
> ld a4,$-8(s10)
> jr a4

It looks like you could get smaller code by choosing lower register
numbers, so that more of the instructions could use the compressed
encoding supported by almost all RISC-V chips.

Marcel Hendrix <mhx@iae.nl> writes:
>Wait, you meant "Sipeed Nezha 64bit RISC-V Linux Sbc Board,
>Allwinner D1@1.0GHz, 1Gbyte DDR3, support for Tina/Debian System?"
>But that board is $133, with $13.72 transportation cost, no power supply.

If you are in the market for this kind of money: We have a Starfive
Visionfive 1 with 8GB RAM and very slow SD-card access (even slightly
slower than using NFS, both at slightly above 20MB/s), but apart from
its sluggishness works flawlessly. Some time ago I saw the
announcement for the Visionfive 2, which supposedly has some of the
bugs fixed that led to sluggish workarounds on the Visionfive 1, and
the announcement has also been for a slightly lower price.

For Gforth the Visionfive 1 is quite a bit slower than the Odroid C2
(and I expect that it is also slower than the Raspi 3, but by a
smaller margin). The numbers below are times in seconds:

sieve bubble matrix fib fft release; CPU; gcc
0.519 0.555 0.483 0.797 0.729 20220226 (3 regs); 1GHz U74 Visionfive V1
0.350 0.390 0.240 0.470 0.280 20190124; Odroid C2 (1536MHz Cortex-A53)

- anton
--
M. Anton Ertl http://www.complang.tuwien.ac.at/anton/home.html
comp.lang.forth FAQs: http://www.complang.tuwien.ac.at/forth/faq/toc.html
New standard: https://forth-standard.org/
EuroForth 2022: https://euro.theforth.net

Paul Rubin <no.email@nospam.invalid> writes:
>anton@mips.complang.tuwien.ac.at (Anton Ertl) writes:
>> RISC-V
>> ld a5,$8(s8)
>> addi s10,s10,8
>> addi s8,s8,8
>> add s7,s7,a5
>> ld a4,$-8(s10)
>> jr a4
>
>It looks like you could get smaller code by choosing lower register
>numbers, so that more of the instructions could use the compressed
>encoding supported by almost all RISC-V chips.

Everything except the loads uses the compressed 16-bit encodings. If
gcc had chosen the right registers for both operands, (x8-x15 =
s0-s1,a0-a5), it could have compressed the first load to 16 bits. For
the second load we would have to get the offset into the range
(0..31)*8, which is possible, but would require changes to Gforth; and
gcc did not choose the right ip register to compress the second load
anyway.

Looking at the compressed load instructions, they have really funky
immediate encodings.

- anton
--
M. Anton Ertl http://www.complang.tuwien.ac.at/anton/home.html
comp.lang.forth FAQs: http://www.complang.tuwien.ac.at/forth/faq/toc.html
New standard: https://forth-standard.org/
EuroForth 2022: https://euro.theforth.net

In article <2023Jan12.080330@mips.complang.tuwien.ac.at>,
Anton Ertl <anton@mips.complang.tuwien.ac.at> wrote:
<SNIP>
>For Gforth the Visionfive 1 is quite a bit slower than the Odroid C2
>(and I expect that it is also slower than the Raspi 3, but by a
>smaller margin). The numbers below are times in seconds:
>
> sieve bubble matrix fib fft release; CPU; gcc
> 0.519 0.555 0.483 0.797 0.729 20220226 (3 regs); 1GHz U74 Visionfive V1
> 0.350 0.390 0.240 0.470 0.280 20190124; Odroid C2 (1536MHz Cortex-A53)

This is quite respectable. A program like tmanx runs excellently
on a 1 Mhz Pentium, so it will have not problems.

>- anton
--
Don't praise the day before the evening. One swallow doesn't make
spring. You must not say "hey" before you have crossed the bridge.
Don't sell the hide of the bear until you shot it. Better one bird in
the hand than ten in the air. - the Wise from Antrim -

Marcel Hendrix <mhx@iae.nl> writes:
> Please, be more specific. "DshangNezha STU board" is something even Google
> can't find.
> "Join the risc-V bandwagon" is a thread that is unknown.

It's "Dshang" "Nezha", not the two run together. For instance:

https://liliputing.com/nezha-is-a-99-single-board-pc-with-a-risc-v-processor/

I'm seeing prices more around USD $100 than $17, but we'll see.
It may have been discounted as it _is_ pretty modest in specs.

Andy Valencia
Home page: https://www.vsta.org/andy/
To contact me: https://www.vsta.org/contact/andy.html

On Friday, January 13, 2023 at 1:30:08 AM UTC+1, Andy Valencia wrote:
> Marcel Hendrix <m...@iae.nl> writes:
> > Please, be more specific. "DshangNezha STU board" is something even Google
> > can't find.
> > "Join the risc-V bandwagon" is a thread that is unknown.
> It's "Dshang" "Nezha", not the two run together. For instance:
>
> https://liliputing.com/nezha-is-a-99-single-board-pc-with-a-risc-v-processor/

Thanks Andy, I really couldn't find it, even with some text modification.

The review at that link is pretty level-headed.

-marcel

On Friday, January 13, 2023 at 12:30:08 AM UTC, Andy Valencia wrote:
> Marcel Hendrix <m...@iae.nl> writes:
> > Please, be more specific. "DshangNezha STU board" is something even Google
> > can't find.
> > "Join the risc-V bandwagon" is a thread that is unknown.
> It's "Dshang" "Nezha", not the two run together. For instance:
>
> https://liliputing.com/nezha-is-a-99-single-board-pc-with-a-risc-v-processor/
>
> I'm seeing prices more around USD $100 than $17, but we'll see.
> It may have been discounted as it _is_ pretty modest in specs.
>
> Andy Valencia
> Home page: https://www.vsta.org/andy/
> To contact me: https://www.vsta.org/contact/andy.html

Thanks for the link. From the photos, it is a clone of the
Sipeed Nezha 64bit RISC-V Linux SBC ?

On Fri, 13 Jan 2023 00:15:16 -0800 (PST)
JKN <jkn_gg@nicorp.f9.co.uk> wrote:

> On Friday, January 13, 2023 at 12:30:08 AM UTC, Andy Valencia wrote:
> > Marcel Hendrix <m...@iae.nl> writes:
> > > Please, be more specific. "DshangNezha STU board" is something even Google
> > > can't find.
> > > "Join the risc-V bandwagon" is a thread that is unknown.
> > It's "Dshang" "Nezha", not the two run together. For instance:
> >
> > https://liliputing.com/nezha-is-a-99-single-board-pc-with-a-risc-v-processor/
> >
> > I'm seeing prices more around USD $100 than $17, but we'll see.
> > It may have been discounted as it _is_ pretty modest in specs.
> >
> > Andy Valencia
> > Home page: https://www.vsta.org/andy/
> > To contact me: https://www.vsta.org/contact/andy.html
>
> Thanks for the link. From the photos, it is a clone of the
> Sipeed Nezha 64bit RISC-V Linux SBC ?
>

On Thu, 12 Jan 2023 16:28:34 -0800
Andy Valencia <vandys@vsta.org> wrote:

> I'm seeing prices more around USD $100 than $17, but we'll see.
> It may have been discounted as it _is_ pretty modest in specs.

Cheapest D1 board set I've seen (on eBay & AliExpress) is €28,40
SipEED Lichee RV Dock Reviews here:

https://hackaday.com/2022/01/06/new-part-day-the-risc-v-lichee-rv-module-and-dock/

https://liliputing.com/this-5-dock-turns-the-17-sipeed-lichee-rv-into-a-fully-functional-risc-v-computer/

No Ethernet, but has a companion mic array board.

Jan Coombs