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programming / alt.lang.asm / Boolean/logic gate operations/sec.

o Boolean/logic gate operations/sec.skybuck2000

Subject: Boolean/logic gate operations/sec.
From: skybuck2000
Newsgroups: alt.lang.asm
Date: Sat, 18 Dec 2021 18:12 UTC
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Subject: Boolean/logic gate operations/sec.
From: (skybuck2000)
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Here is a nice boolean/logic gate operation/sec challenge for you.

Your mission/the goal is to execute as many boolean/logic gate operations/sec as you possible can/your cpu can/or perhaps even your gpu.

The logic gates to be simulated are the main 6 ones:

and, or, xor, nand, nor, nxor.

Also any explanation as to way that performance is achieved would be appreciated.

For now my guess is that performance will be limited by:

1. Gigahertz
2. Number of cores.
3. Instructions per clock/ALUs/Hyper Threading.
4. Level 1, Level 2, Level 3 Caches.
5. Data/bandwidth rate to chip/cpu/gpu.

For now the assumption is that 1-bit boolean outcomes and thus also 2 bit inputs are what is needed.

So your gate code should look like:

2x 1-bit-input followed by a 1x 1-bit-output.

Gate execution pseudo code:

// load A from A index

// load B from B index

// execute gate: A, B, Operation, C

// save/store C to C index

^ This code is basic and assumes 1 bit registers, in reality processors have multi bit registers, 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, 256 bits and even 512 bits.

However the ALUs hooked up to them could be different, also other operators like ADD, MUL, DIV, SHL, SHR could be used to construct additional boolean logic/gate paths ?! Simulating the and, or, xor ???

I would also be interested in discussing your views on this and any predictions to which hardware will execute it the fastest ?!? Multi-core cpus ?! Or many core GPUS ?!?

Bye for now,

rocksolid light 0.7.2