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programming / comp.lang.asm.x86 / Re: FPU (x87) code debugging.

SubjectAuthor
* FPU (x87) code debugging.R.Wieser
+* Re: FPU (x87) code debugging.Frank Kotler
|`- Re: FPU (x87) code debugging.R.Wieser
+* Re: FPU (x87) code debugging.DJ Delorie
|`* Re: FPU (x87) code debugging.R.Wieser
| `- Re: FPU (x87) code debugging.wolfgang kern
+* Re: FPU (x87) code debugging.wolfgang kern
|`- Re: FPU (x87) code debugging.R.Wieser
`* Re: FPU (x87) code debugging.Robert
 `* Re: FPU (x87) code debugging.R.Wieser
  +* Re: FPU (x87) code debugging.Robert
  |`* Re: FPU (x87) code debugging.R.Wieser
  | +* Re: FPU (x87) code debugging.Robert Prins
  | |`- Re: FPU (x87) code debugging.R.Wieser
  | `* Re: FPU (x87) code debugging.Robert
  |  `* Re: FPU (x87) code debugging.R.Wieser
  |   `* Re: FPU (x87) code debugging.Robert
  |    `* Re: FPU (x87) code debugging.R.Wieser
  |     `* Re: FPU (x87) code debugging.Robert Redelmeier
  |      `* Re: FPU (x87) code debugging.R.Wieser
  |       `* Re: FPU (x87) code debugging.Robert Prins
  |        `* Re: FPU (x87) code debugging.R.Wieser
  |         `* Re: FPU (x87) code debugging.Kerr-Mudd, John
  |          +- Re: FPU (x87) code debugging.R.Wieser
  |          +* Re: FPU (x87) code debugging.Anton Ertl
  |          |`- Re: FPU (x87) code debugging.wolfgang kern
  |          `- Re: FPU (x87) code debugging.wolfgang kern
  `* Re: FPU (x87) code debugging.wolfgang kern
   +* Re: FPU (x87) code debugging.R.Wieser
   |+- Re: FPU (x87) code debugging.wolfgang kern
   |`- Re: FPU (x87) code debugging.wolfgang kern
   `* Re: FPU (x87) code debugging.wolfgang kern
    `* Re: FPU (x87) code debugging.R.Wieser
     +- Re: FPU (x87) code debugging.R.Wieser
     `* Re: FPU (x87) code debugging.wolfgang kern
      `- Re: FPU (x87) code debugging.R.Wieser

Pages:12
Subject: Re: FPU (x87) code debugging.
From: Robert
Newsgroups: comp.lang.asm.x86
Organization: Aioe.org NNTP Server
Date: Mon, 9 Aug 2021 13:08 UTC
References: 1 2 3 4 5 6 7
Path: i2pn2.org!i2pn.org!eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail
From: red...@nospicedham.ev1.net.invalid (Robert)
Newsgroups: comp.lang.asm.x86
Subject: Re: FPU (x87) code debugging.
Date: Mon, 9 Aug 2021 13:08:37 -0000 (UTC)
Organization: Aioe.org NNTP Server
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R.Wieser <address@nospicedham.not.available> wrote in part:
Robert,
Well, please make sure the pointer is correct

:-) And how do you propose that should be done ?    
It sounds like a great idea, but ...

Walk before you run, when in trouble, drop back.  Before trying
a potentially troublesome instruction like FXSAVE, use MOV.
Even hand-assemble from hex if those facilities are in doubt:

MOV EAX, "pointer"    ; to see if you can read loc
MOV "pointer", EAX    ; to see if you can write


(trash easily gets caught in the upper bits in mixed-mode)

Somewhere along the line I forgot to mention that I was programming in 32-bit
mode (under Win XP).  So, no mixed mode and no trash in the upper bits.

I don't think XP does 64, but the CPU might.  The upper-upper could
get trash.  ISTR needing to set something to get IN/OUT to work.


Ah, but circularity is achieved by masking, 8=0 when masked at 3bits.

Well ...  It /can/ be achieved that way, but only under
certain conditions (related to origin and size). :-)

Zero origin, power-of-two size.  Check on both.
Ever wonder why there are so many buffers this way?

The problem has been located though : I simply used the wrong R/M value
while hand-encoding the FXSAVE command (likely mixing up the 16 bit table
with the 32 bit one).   IOW, I was providing the target addres in a certain
register while the command expected it in another register/form.

Debugging with MOV test (hand-assembled) could have caught.

-- Robert




Subject: Re: FPU (x87) code debugging.
From: R.Wieser
Newsgroups: comp.lang.asm.x86
Organization: Aioe.org NNTP Server
Date: Mon, 9 Aug 2021 13:50 UTC
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From: addr...@nospicedham.not.available (R.Wieser)
Newsgroups: comp.lang.asm.x86
Subject: Re: FPU (x87) code debugging.
Date: Mon, 9 Aug 2021 15:50:18 +0200
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Robert

Well, please make sure the pointer is correct

:-) And how do you propose that should be done ?
It sounds like a great idea, but ...
....
use MOV.

How would that change anything ?    If the target for an FXSAVE is wrong
enough that it causes an exception, how /wouldn't/ that be in the same way
wrong for a MOV ?  (lets forget about alignment for a moment)

It would even be making the problem larger, as you would than need to pick a
REG value too - and wonder if it perhaps is having a negative influence on
the result.

FWI, I tried several R/M values, none of which wanted to work.   Bad luck I
guess.

In retrospect I should perhaps have tried loading all the common registers
with the same value and tried all R/M values until something worked.  On
success it would be a case of determining which register is the source, and
than look back at the instruction set to find a match - and from it figure
out what the/my mistake was.

Zero origin, power-of-two size.  Check on both.
Ever wonder why there are so many buffers this way?

No, never.  Really ... <whistle>

Debugging with MOV test (hand-assembled) could have caught.

I doubt it.  See above.

Regards,
Rudy Wieser




Subject: Re: FPU (x87) code debugging.
From: Robert Redelmeier
Newsgroups: comp.lang.asm.x86
Organization: Aioe.org NNTP Server
Date: Mon, 9 Aug 2021 14:56 UTC
References: 1 2 3 4 5 6 7 8 9
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From: red...@ev1.net.invalid (Robert Redelmeier)
Newsgroups: comp.lang.asm.x86
Subject: Re: FPU (x87) code debugging.
Date: Mon, 9 Aug 2021 14:56:52 -0000 (UTC)
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R.Wieser <address@nospicedham.not.available> wrote in part:
Robert
Well, please make sure the pointer is correct
:-) And how do you propose that should be done ?
It sounds like a great idea, but ...
use MOV.

How would that change anything ?  If the target for
an FXSAVE is wrong enough that it causes an exception,
how /wouldn't/ that be in the same way wrong for a MOV ?
(lets forget about alignment for a moment)

It is a purer memory test.  I thought there was question
of whether FXSAVE was available or supported on your CPU.
This checks opcode encoding too.

It would even be making the problem larger, as you would
than need to pick a REG value too - and wonder if it perhaps
is having a negative influence on the result.

All GP registers should be available at all times.

FWI, I tried several R/M values, none of which wanted
to work.  Bad luck I guess.

Encoding should not be a guessing game.
The odds are bad, <1% .

In retrospect I should perhaps have tried loading all the
common registers with the same value and tried all R/M
values until something worked.  On success it would be
a case of determining which register is the source, and
than look back at the instruction set to find a match -
and from it figure out what the/my mistake was.

x86 has quirky indirect addressing modes that
are unlikely to yield to trial-and-error.

-- Robert



Subject: Re: FPU (x87) code debugging.
From: R.Wieser
Newsgroups: comp.lang.asm.x86
Organization: Aioe.org NNTP Server
Date: Mon, 9 Aug 2021 16:11 UTC
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From: addr...@nospicedham.not.available (R.Wieser)
Newsgroups: comp.lang.asm.x86
Subject: Re: FPU (x87) code debugging.
Date: Mon, 9 Aug 2021 18:11:26 +0200
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Robert,

It is a purer memory test.

In what way ?     And mind you, I already adressed that.

I thought there was question of whether FXSAVE was available
or supported on your CPU.

As I could not get a working FXSAVE encoding I started to doubt.

This checks opcode encoding too.

No need for that, as those two bytes came from an opcode list.   The only
unknown part was the adressing of the target memory.

All GP registers should be available at all times.

Agreed.   But it is an extra factor, and as such interference.

Encoding should not be a guessing game.

What makes you think I was ?      I tried a few different R/M encodings
(while providing different registers), and none of them wanted to work.
Hence my (above) described doubt to if the command was available on my
'puter/processor. (read: I was quite certain I did it "by the book")

But when you /know/ something ought to work and you cannot make it so than a
pragmatic approach will be called for.  Which includes throwing everything
and the kitchen sink at it to see if /something/ will work.  And from that
try to reason back why it does and where you went wrong with the first
attempts.

x86 has quirky indirect addressing modes that
are unlikely to yield to trial-and-error.

True.  But I would not be looking for those.    Just a simple one that
/does/ function.  From that foot-in-the-door the rest often follows.

And that is effectivily what happened when Wolfgang supplied me with a
working encoding for FXSAVE [EDI] : while trying to match the 0x07 to the
mod,reg,r/m tables I had used I realized I had been using the wrong one.  It
was as simple as that.

Regards,
Rudy Wieser




Subject: Re: FPU (x87) code debugging.
From: Robert Prins
Newsgroups: comp.lang.asm.x86
Organization: A noiseless patient Spider
Date: Tue, 10 Aug 2021 15:54 UTC
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Path: i2pn2.org!i2pn.org!eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail
From: rob...@nospicedham.prino.org (Robert Prins)
Newsgroups: comp.lang.asm.x86
Subject: Re: FPU (x87) code debugging.
Date: Tue, 10 Aug 2021 15:54:47 +0000
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On 2021-08-09 16:11, R.Wieser wrote:

 > And that is effectivily what happened when Wolfgang supplied me with a
 > working encoding for FXSAVE [EDI] : while trying to match the 0x07 to the
 > mod,reg,r/m tables I had used I realized I had been using the wrong one.  It
 > was as simple as that.
Use

https://defuse.ca/online-x86-assembler.htm

for all your "db" needs. I use it "all the time" to get P5+ opcodes for Virtual Pascal in-line assembler, I've become a huge fan of using AVX instructions, and miraculously, most of the data structures I was using in 1985 (TP3), then 16-bit, now 32-bit, are almost perfectly suited for XMM and YMM code, go figure!

Robert
--
Robert AH Prins
robert(a)prino(d)org
The hitchhiking grandfather - https://prino.neocities.org/indez.html
Some REXX code for use on z/OS - https://prino.neocities.org/zOS/zOS-Tools.html



Subject: Re: FPU (x87) code debugging.
From: R.Wieser
Newsgroups: comp.lang.asm.x86
Organization: Aioe.org NNTP Server
Date: Tue, 10 Aug 2021 14:46 UTC
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From: addr...@nospicedham.not.available (R.Wieser)
Newsgroups: comp.lang.asm.x86
Subject: Re: FPU (x87) code debugging.
Date: Tue, 10 Aug 2021 16:46:26 +0200
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Robert,

Use

https://defuse.ca/online-x86-assembler.htm

for all your "db" needs.

Thank you very much. It will certainly come in handy. :-)

.... and it doesn't even need JS to "do its thing".  <thumbs up>

Regards,
Rudy Wieser




Subject: Re: FPU (x87) code debugging.
From: Kerr-Mudd, John
Newsgroups: comp.lang.asm.x86
Organization: Dis
Date: Tue, 10 Aug 2021 19:53 UTC
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From: adm...@nospicedham.127.0.0.1 (Kerr-Mudd, John)
Newsgroups: comp.lang.asm.x86
Subject: Re: FPU (x87) code debugging.
Date: Tue, 10 Aug 2021 20:53:41 +0100
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On Tue, 10 Aug 2021 16:46:26 +0200
"R.Wieser" <address@nospicedham.not.available> wrote:

Robert,

Use

https://defuse.ca/online-x86-assembler.htm

for all your "db" needs.

Thank you very much. It will certainly come in handy. :-)

... and it doesn't even need JS to "do its thing".  <thumbs up>

I tried mov ax,bx and got
6689D8 

I guess x86 means 32bit nowadays!

--
Bah, and indeed Humbug.



Subject: Re: FPU (x87) code debugging.
From: R.Wieser
Newsgroups: comp.lang.asm.x86
Organization: Aioe.org NNTP Server
Date: Wed, 11 Aug 2021 08:00 UTC
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Path: i2pn2.org!i2pn.org!eternal-september.org!reader02.eternal-september.org!.POSTED!not-for-mail
From: addr...@nospicedham.not.available (R.Wieser)
Newsgroups: comp.lang.asm.x86
Subject: Re: FPU (x87) code debugging.
Date: Wed, 11 Aug 2021 10:00:00 +0200
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John,

I tried mov ax,bx and got
6689D8

I guess x86 means 32bit nowadays!

Not for the people in this newsgroup perhaps, but for the majority of users
out there ?  Certainly.

But yes, I noticed that too.  A 16-bit option would have been nice to have.

Regards,
Rudy Wieser




Subject: Re: FPU (x87) code debugging.
From: Anton Ertl
Newsgroups: comp.lang.asm.x86
Organization: Institut fuer Computersprachen, Technische Universitaet Wien
Date: Wed, 11 Aug 2021 07:59 UTC
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From: ant...@nospicedham.mips.complang.tuwien.ac.at (Anton Ertl)
Newsgroups: comp.lang.asm.x86
Subject: Re: FPU (x87) code debugging.
Date: Wed, 11 Aug 2021 07:59:34 GMT
Organization: Institut fuer Computersprachen, Technische Universitaet Wien
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"Kerr-Mudd, John" <admin@nospicedham.127.0.0.1> writes:
I guess x86 means 32bit nowadays!

That's the problem with "x86": People use it to mean any of several
different ISAs.  So better avoid that term, and use:

8086 (rarely called IA-16) when you mean that instruction set.
IA-32 when you mean that instruction set (first implementation: 80386)
AMD64 when you mean that instruction set (first implementation: AMD K8
                                          (Opteron, Athlon 64))

And then there are extensions, like the additional 80186 and 80286
instructions (plus the 80286 offers protected mode), or SSE, SSE2,
AVX, ...

Now what does that mean for the name of this newsgroup.

- anton
--
M. Anton Ertl                    Some things have to be seen to be believed
anton@mips.complang.tuwien.ac.at Most things have to be believed to be seen
http://www.complang.tuwien.ac.at/anton/home.html



Subject: Re: FPU (x87) code debugging.
From: wolfgang kern
Newsgroups: comp.lang.asm.x86
Organization: Aioe.org NNTP Server
Date: Wed, 11 Aug 2021 08:34 UTC
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From: nowh...@nospicedham.never.at (wolfgang kern)
Newsgroups: comp.lang.asm.x86
Subject: Re: FPU (x87) code debugging.
Date: Wed, 11 Aug 2021 10:34:11 +0200
Organization: Aioe.org NNTP Server
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On 10.08.2021 21:53, Kerr-Mudd, John wrote:

https://defuse.ca/online-x86-assembler.htm

I tried mov ax,bx and got
6689D8
I guess x86 means 32bit nowadays!

:) of course!
16 bit code will soon just belong to history.

I'm happy to have my own 16/32/64bit disassembler although it already needs many updates now, but it saves me from internet access.

89 D8 is the STORE variant which should only be used for memory write.

8B c3 would be the correct LOAD opcode. I fight for this since decades but no one ever listened, so Intel and AMD will never get rid of this doubles and can't make space for 64 other instructions with 89 mod 3,
like the added valid opcodes for the former illegal 8F08 and 8F10.
__
wolfgang



Subject: Re: FPU (x87) code debugging.
From: wolfgang kern
Newsgroups: comp.lang.asm.x86
Organization: Aioe.org NNTP Server
Date: Wed, 11 Aug 2021 08:45 UTC
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From: nowh...@nospicedham.never.at (wolfgang kern)
Newsgroups: comp.lang.asm.x86
Subject: Re: FPU (x87) code debugging.
Date: Wed, 11 Aug 2021 10:45:44 +0200
Organization: Aioe.org NNTP Server
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On 11.08.2021 09:59, Anton Ertl wrote:
"Kerr-Mudd, John" <admin@nospicedham.127.0.0.1> writes:
I guess x86 means 32bit nowadays!

That's the problem with "x86": People use it to mean any of several
different ISAs.  So better avoid that term, and use:

8086 (rarely called IA-16) when you mean that instruction set.
IA-32 when you mean that instruction set (first implementation: 80386)
AMD64 when you mean that instruction set (first implementation: AMD K8
                                           (Opteron, Athlon 64))

And then there are extensions, like the additional 80186 and 80286
instructions (plus the 80286 offers protected mode), or SSE, SSE2,
AVX, ...

Now what does that mean for the name of this newsgroup.

I wont recommend to split our CLAX into several CPU-related groups.
all Intel/AMD 16 bit instruction sets are different for CPU families.
And almost all regular readers of this group are aware of this anyway.
__
wolfgang



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