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devel / comp.lang.forth / FPGA4th

FPGA4th

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https://www.novabbs.com/devel/article-flat.php?id=15338&group=comp.lang.forth#15338

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Subject: FPGA4th
From: johnroge...@gmail.com (John Hart)
Injection-Date: Thu, 25 Nov 2021 07:06:47 +0000
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 by: John Hart - Thu, 25 Nov 2021 07:06 UTC

\ Op Code File for MFX. Generated by MAKE-OPS v13

\ MODELS\RACE32\RACE32.ops

\ src dst codes J I H G F E D C B A 9 8 7 6 5 4 3 2 1 0
\ `--.--' `-.-' | | | | | | | | | | |
\ errors -------------' | | | | | | | | | | | |
\ constants -----------------' | | | | | | | | | | | - c8_6_5_3
\ stack ptr mem ---------------------' | | | | | | | | | | - S PM
\ loop ctr ----------------------------' | | | | | | | | | - L LC
\ return reg ----------------------------' | | | | | | | | - R RR
\ prog ctr --------------------------------' | | | | | | | - P PC
\ mem ads -----------------------------------' | | | | | | - F FLG
\ flag ----------------------------------------' | | | | | - M MA
\ carry -----------------------------------------' | | | | - C CRY
\ data reg ----------------------------------------' | | | - D DR
\ Treg high (sos) -----------------------------------' | | - T TH
\ Treg low (sos) --------------------------------------' | - t TL
\ accumulator (tos) -------------------------------------' - A AC

\ Deferred cmds:
\ Dsrc Ddst codes J I H G F E D C B A 9 8 7 6 5 4 3 2 1 0
\ `--.--' `-.-' | | | | | | |
\ errors -------------' | | | | | | | |
\ constants -----------------' | | | | | | |
\ i/o -------------------------------------' | | | | | |
\ static mem --------------------------------' | | | | |
\ dynamic mem ---------------------------------' | | | |
\ reg mem ---------------------------------------' | | |
\ Treg high (sos) -----------------------------------' | |
\ Treg low (sos) --------------------------------------' |
\ accumulator (tos) -------------------------------------'

\ now deferred now deferred
\ code type src dst Dsrc Ddst instr string emultion emulation operation
0 1 >XBCS tT D - - H" TR>DR" ' EMU_TR>DR ' NOP SIMPLE-OP: TR>DR
1 1 >XBCS D tT - - H" DR>TR" ' EMU_DR>TR ' NOP SIMPLE-OP: DR>TR
2 1 >XBCS A D - - H" AC>DR" ' EMU_AC>DR ' NOP SIMPLE-OP: AC>DR
3 1 >XBCS A F - - H" TR15>FLG" ' EMU_TR15>FLG ' NOP SIMPLE-OP: TR15>FLG
1 2 >XBCS - tT - - H" -1>TRL" ' EMU_-1>TRL ' NOP SIMPLE-OP: -1>TRL
2 2 >XBCS - tT - - H" -1>TRH" ' EMU_-1>TRH ' NOP SIMPLE-OP: -1>TRH
3 2 >XBCS - tT - - H" -1>TR" ' EMU_-1>TR ' NOP SIMPLE-OP: -1>TR
0 3 >XBCS - D - - H" 0>DR" ' EMU_0>DR ' NOP SIMPLE-OP: 0>DR
1 3 >XBCS - tT - - H" 0>TRL" ' EMU_0>TRL ' NOP SIMPLE-OP: 0>TRL
2 3 >XBCS - tT - - H" 0>TRH" ' EMU_0>TRH ' NOP SIMPLE-OP: 0>TRH
3 3 >XBCS - tT - - H" 0>TR" ' EMU_0>TR ' NOP SIMPLE-OP: 0>TR
0 4 >XBCS A D - - H" AC>DR" ' EMU_AC>DR ' NOP SIMPLE-OP: AC>DR
1 4 >XBCS A tT - - H" AC>TR" ' EMU_AC>TR ' NOP SIMPLE-OP: AC>TR
2 4 >XBCS AtT D - - H" AC_OR_TR>DR" ' EMU_AC_OR_TR>DR ' NOP SIMPLE-OP: AC_OR_TR>DR
3 4 >XBCS AD tT - - H" AC_AND_DR>TR" ' EMU_AC_AND_DR>TR ' NOP SIMPLE-OP: AC_AND_DR>TR
0 5 >XBCS - C - - H" 0>CRY" ' EMU_0>CRY ' NOP SIMPLE-OP: 0>CRY
1 5 >XBCS - C - - H" 1>CRY" ' EMU_1>CRY ' NOP SIMPLE-OP: 1>CRY
2 5 >XBCS C CF - - H" 0>CRY>FLG" ' EMU_0>CRY>FLG ' NOP SIMPLE-OP: 0>CRY>FLG
3 5 >XBCS CF CF - - H" CRY><FLG" ' EMU_CRY><FLG ' NOP SIMPLE-OP: CRY><FLG
\ code type src dst Dsrc Ddst instr string emultion emulation operation
0 6 >XBCS c6 L - - H" C6>REP" ' EMU_C6>REP ' NOP SIMPLE-OP: C6>REP
1 6 >XBCS Ac6 DL - - H" C6>REP~AC>DR" ' EMU_C6>REP~AC>DR ' NOP SIMPLE-OP: C6>REP~AC>DR
2 6 >XBCS tTc6 DL - - H" C6>REP~TR>DR" ' EMU_C6>REP~TR>DR ' NOP SIMPLE-OP: C6>REP~TR>DR
3 6 >XBCS tTDc6 tTDL - - H" C6>REP~TR><DR" ' EMU_C6>REP~TR><DR ' NOP SIMPLE-OP: C6>REP~TR><DR
0 7 >XBCS AtTc6 DL - - H" C6&AC>REP~0>DR" ' EMU_C6&AC>REP~0>DR ' NOP SIMPLE-OP: C6&AC>REP~0>DR
1 7 >XBCS AtTc6 DL - - H" C6&/AC>REP~0>DR" ' EMU_C6&/AC>REP~0>D ' NOP SIMPLE-OP: C6&/AC>REP~0>DR
2 7 >XBCS c6 L - - H" C6>LOOP" ' EMU_C6>LOOP ' NOP SIMPLE-OP: C6>LOOP
8 >CS - - A r H" AC>*MA_d" ' EMU_AC>*MA ' EMU_WE4 SIMPLE-OP: AC>*MA_d
9 >CS A tT - - H" AC>TRx" ' EMU_AC>TR ' NOP SIMPLE-OP: AC>TRx
1 A >XBCS - - A rds H" AC>*MA_BYT_d" ' EMU_AC>*MA_BYT ' EMU_WE1 SIMPLE-OP: AC>*MA_BYT_d
2 A >XBCS - - A rdso H" ACLW>*MA_d" ' EMU_ACLW>*MA ' EMU_WE2 SIMPLE-OP: ACLW>*MA_d
3 A >XBCS - - A rdso H" ACHW>*MA_d" ' EMU_ACHW>*MA ' EMU_WE3 SIMPLE-OP: ACHW>*MA_d
1 B >XBCS A tT A r H" AC>TR~AC>*MA_d" ' EMU_AC>TR ' EMU_WE4 SIMPLE-OP: AC>TR~AC>*MA_d
2 B >XBCS A D A r H" AC>DR~AC>*MA_d" ' EMU_AC>DR ' EMU_WE4 SIMPLE-OP: AC>DR~AC>*MA_d
3 B >XBCS - - A - H" AC>TR(CS)_d" ' EMU_AC>TR(CS) ' EMU_WE7 SIMPLE-OP: AC>TR(CS)_d
1 C >XBCS - tT ro tT H" *MA>TRL_d" ' EMU_*MA>TRL ' EMU_RE1 SIMPLE-OP: *MA>TRL_d
2 C >XBCS - tT rds tT H" *MA>TRH_d" ' EMU_*MA>TRH ' EMU_RE2 SIMPLE-OP: *MA>TRH_d
3 C >XBCS - tT r tT H" *MA>TR_d" ' EMU_*MA>TR ' EMU_RE3 SIMPLE-OP: *MA>TR_d
1 D >XBCS A tTD r tT H" AC>DR~*MA>TR_d" ' EMU_AC>DR ' EMU_RE3 SIMPLE-OP: AC>DR~*MA>TR_d
\ code type src dst Dsrc Ddst instr string emultion emulation operation
2 D >XBCS tT tTD r tT H" TR>DR~*MA>TR_d" ' EMU_TR>DR ' EMU_RE3 SIMPLE-OP: TR>DR~*MA>TR_d
F >CS - tT ro tT H" *MA>NXT_d" ' EMU_*MA>NXT ' EMU_RE4 SIMPLE-OP: *MA>NXT_d
0 10 >XBCS CPc6 P - - H" IF_CRY+JMP" ' EMU_IF_CRY+JMP ' NOP COUNT-OP: IF_CRY+JMP
1 10 >XBCS CPc6 P - - H" IF/CRY+JMP" ' EMU_IF/CRY+JMP ' NOP COUNT-OP: IF/CRY+JMP
2 10 >XBCS FPc6 P - - H" IF_FLG+JMP" ' EMU_IF_FLG+JMP ' NOP COUNT-OP: IF_FLG+JMP
3 10 >XBCS FPc6 P - - H" IF/FLG+JMP" ' EMU_IF/FLG+JMP ' NOP COUNT-OP: IF/FLG+JMP
0 11 >XBCS APc6 P - - H" IF_AC0+JMP" ' EMU_IF_AC0+JMP ' NOP COUNT-OP: IF_AC0+JMP
1 11 >XBCS APc6 P - - H" IF/AC0+JMP" ' EMU_IF/AC0+JMP ' NOP COUNT-OP: IF/AC0+JMP
2 11 >XBCS APc6 P - - H" IF_AC31+JMP" ' EMU_IF_AC31+JMP ' NOP COUNT-OP: IF_AC31+JMP
3 11 >XBCS APc6 P - - H" IF/AC31+JMP" ' EMU_IF/AC31+JMP ' NOP COUNT-OP: IF/AC31+JMP
0 12 >XBCS CPc6 P - - H" IF_CRY-JMP" ' EMU_IF_CRY-JMP ' NOP COUNT-OP: IF_CRY-JMP
1 12 >XBCS CPc6 P - - H" IF/CRY-JMP" ' EMU_IF/CRY-JMP ' NOP COUNT-OP: IF/CRY-JMP
2 12 >XBCS FPc6 P - - H" IF_FLG-JMP" ' EMU_IF_FLG-JMP ' NOP COUNT-OP: IF_FLG-JMP
3 12 >XBCS FPc6 P - - H" IF/FLG-JMP" ' EMU_IF/FLG-JMP ' NOP COUNT-OP: IF/FLG-JMP
0 13 >XBCS APc6 P - - H" IF_AC0-JMP" ' EMU_IF_AC0-JMP ' NOP COUNT-OP: IF_AC0-JMP
1 13 >XBCS APc6 P - - H" IF/AC0-JMP" ' EMU_IF/AC0-JMP ' NOP COUNT-OP: IF/AC0-JMP
2 13 >XBCS APc6 P - - H" IF_AC31-JMP" ' EMU_IF_AC31-JMP ' NOP COUNT-OP: IF_AC31-JMP
3 13 >XBCS APc6 P - - H" IF/AC31-JMP" ' EMU_IF/AC31-JMP ' NOP COUNT-OP: IF/AC31-JMP
0 14 >XBCS Pc8 P - - H" +JMP" ' EMU_+JMP ' NOP COUNT-OP: +JMP
\ code type src dst Dsrc Ddst instr string emultion emulation operation
1 14 >XBCS APc6 P - - H" IF/AC1+JMP" ' EMU_IF/AC1+JMP ' NOP COUNT-OP: IF/AC1+JMP
2 14 >XBCS APc6 P - - H" IF/AC2+JMP" ' EMU_IF/AC2+JMP ' NOP COUNT-OP: IF/AC2+JMP
3 14 >XBCS APc6 P - - H" IF/AC3+JMP" ' EMU_IF/AC3+JMP ' NOP COUNT-OP: IF/AC3+JMP
0 15 >XBCS APc6 P - - H" IF/AC4+JMP" ' EMU_IF/AC4+JMP ' NOP COUNT-OP: IF/AC4+JMP
1 15 >XBCS APc6 P - - H" IF/AC5+JMP" ' EMU_IF/AC5+JMP ' NOP COUNT-OP: IF/AC5+JMP
2 15 >XBCS APc6 P - - H" IF/AC6+JMP" ' EMU_IF/AC6+JMP ' NOP COUNT-OP: IF/AC6+JMP
3 15 >XBCS APc6 P - - H" IF/AC7+JMP" ' EMU_IF/AC7+JMP ' NOP COUNT-OP: IF/AC7+JMP
0 16 >XBCS Pc8 P - - H" -JMP" ' EMU_-JMP ' NOP COUNT-OP: -JMP
1 16 >XBCS PLc6 P - - H" IF_REP-JMP" ' EMU_IF_REP-JMP ' NOP COUNT-OP: IF_REP-JMP
2 16 >XBCS c8 P - - H" JMP&LINK" ' EMU_JMP&LINK ' NOP COUNT-OP: JMP&LINK
3 16 >XBCS R P - - H" RET_LINK" ' EMU_RET_LINK ' NOP COUNT-OP: RET_LINK
0 17 >XBCS t tT - - H" TR_RL" ' EMU_TR_RL ' NOP SIMPLE-OP: TR_RL
1 17 >XBCS At tT - - H" TR_RL_DR" ' EMU_TR_RL_DR ' NOP SIMPLE-OP: TR_RL_DR
2 17 >XBCS tD tT - - H" TR_RL_AC" ' EMU_TR_RL_AC ' NOP SIMPLE-OP: TR_RL_AC
3 17 >XBCS tTC tTC - - H" TR_RLC" ' EMU_TR_RLC ' NOP SIMPLE-OP: TR_RLC
0 18 >XBCS tT tT - - H" TR_RR" ' EMU_TR_RR ' NOP SIMPLE-OP: TR_RR
1 18 >XBCS tT tT - - H" TR_RR_DR" ' EMU_TR_RR_DR ' NOP SIMPLE-OP: TR_RR_DR
2 18 >XBCS tT tT - - H" TR_RR_AC" ' EMU_TR_RR_AC ' NOP SIMPLE-OP: TR_RR_AC
3 18 >XBCS tT tTC - - H" TR_RRC" ' EMU_TR_RRC ' NOP SIMPLE-OP: TR_RRC
\ code type src dst Dsrc Ddst instr string emultion emulation operation
0 19 >XBCS tT tT - - H" TR_RRB" ' EMU_TR_RRB ' NOP SIMPLE-OP: TR_RRB
1 19 >XBCS tT tT - - H" TR_RRB_DR" ' EMU_TR_RRB_DR ' NOP SIMPLE-OP: TR_RRB_DR
2 19 >XBCS tT tT - - H" TR_RRB_AC" ' EMU_TR_RRB_AC ' NOP SIMPLE-OP: TR_RRB_AC
3 19 >XBCS tT tT - - H" TR_SRB" ' EMU_TR_SRB ' NOP SIMPLE-OP: TR_SRB
0 1A >XBCS D D - - H" DR_RL" ' EMU_DR_RL ' NOP SIMPLE-OP: DR_RL
1 1A >XBCS D D - - H" DR_RL" ' EMU_DR_RL ' NOP SIMPLE-OP: DR_RL
2 1A >XBCS tD D - - H" DR_RL-TR" ' EMU_DR_RL_TR ' NOP SIMPLE-OP: DR_RL-TR
3 1A >XBCS DC DC - - H" DR_RLC" ' EMU_DR_RLC ' NOP SIMPLE-OP: DR_RLC
0 1B >XBCS D D - - H" DR_RR" ' EMU_DR_RR ' NOP SIMPLE-OP: DR_RR
1 1B >XBCS AD D - - H" DR_RR_AC" ' EMU_DR_RR_AC ' NOP SIMPLE-OP: DR_RR_AC
2 1B >XBCS TD D - - H" DR_RR_TR" ' EMU_DR_RR_TR ' NOP SIMPLE-OP: DR_RR_TR
3 1B >XBCS DC DC - - H" DR_RRC" ' EMU_DR_RRC ' NOP SIMPLE-OP: DR_RRC
0 1C >XBCS D D - - H" DR_RRB" ' EMU_DR_RRB ' NOP SIMPLE-OP: DR_RRB
1 1C >XBCS AD D - - H" DR_RRB_AC" ' EMU_DR_RRB_AC ' NOP SIMPLE-OP: DR_RRB_AC
2 1C >XBCS tD D - - H" DR_RRB_TR" ' EMU_DR_RRB_TR ' NOP SIMPLE-OP: DR_RRB_TR
3 1C >XBCS D D - - H" DR_SRB" ' EMU_DR_SRB ' NOP SIMPLE-OP: DR_SRB
2 1D >XBCS tD tTD - - H" TR_DR_RL_AC" ' EMU_TR_DR_RL_AC ' NOP SIMPLE-OP: TR_DR_RL_AC
0 1E >XBCS tTD tTD - - H" TR_DR_RR" ' EMU_TR_DR_RR ' NOP SIMPLE-OP: TR_DR_RR
2 1E >XBCS AtTD tTD - - H" TR_DR_RR_AC" ' EMU_TR_DR_RR_AC ' NOP SIMPLE-OP: TR_DR_RR_AC
\ code type src dst Dsrc Ddst instr string emultion emulation operation
2 1F >XBCS tTD tTD - - H" TR_DR_RRB_AC" ' EMU_TR_DR_RRB_AC ' NOP SIMPLE-OP: TR_DR_RRB_AC
0 >MA - M - - H" hold" ' EMU_MA>MA ' NOP JMPL-OP: hold
1 0 >MAPT A M - - H" IP>MA" ' EMU_PM>MA ' NOP JMPL-OP: IP>MA
1 1 >MAPT A M - - H" RP>MA" ' EMU_PM>MA ' NOP JMPL-OP: RP>MA
1 2 >MAPT A M - - H" SP>MA" ' EMU_PM>MA ' NOP JMPL-OP: SP>MA
1 3 >MAPT A M - - H" DP>MA" ' EMU_PM>MA ' NOP JMPL-OP: DP>MA
1 4 >MAPT Sc5 M - - H" MA+C>MA" ' EMU_MA+C>MA ' NOP JMPL-OP: MA+C>MA
1 5 >MAPT Sc5 M - - H" MA-C>MA" ' EMU_MA-C>MA ' NOP JMPL-OP: MA-C>MA
1 6 >MAPT Sc5 M - - H" MA+C>MAu" ' EMU_MA+C>MA ' NOP JMPL-OP: MA+C>MAu
1 7 >MAPT Sc5 M - - H" MA-C>MAu" ' EMU_MA-C>MA ' NOP JMPL-OP: MA-C>MAu
2 >MA M M - - H" AC>MA" ' EMU_AC>MA ' NOP JMPL-OP: AC>MA
3 >MA tTS M - - H" MA-TR>MAu" ' EMU_MA-TR>MA ' NOP JMPL-OP: MA-TR>MAu
4 >MA Mc6 M - - H" AC+C8>MA" ' EMU_AC+C8>MA ' NOP JMPL-OP: AC+C8>MA
5 0 >MAPT A M - - H" IP+2>MAu" ' EMU_PM+2>MA ' NOP JMPL-OP: IP+2>MAu
5 1 >MAPT tT M - - H" TR>MAu" ' EMU_TR>MA ' NOP JMPL-OP: TR>MAu
5 2 >MAPT tT M - - H" TR+2>MAu" ' EMU_TR+2>MA ' NOP JMPL-OP: TR+2>MAu
5 5 >MAPT tT M - - H" TR>MA" ' EMU_TR>MA ' NOP JMPL-OP: TR>MA
5 6 >MAPT tT M - - H" TR+2>MA" ' EMU_TR+2>MA ' NOP JMPL-OP: TR+2>MA
5 7 >MAPT S M - - H" MA+4>MA" ' EMU_MA+4>MA ' NOP JMPL-OP: MA+4>MA
\ code type src dst Dsrc Ddst instr string emultion emulation operation
6 0 >MAPT Ac5 M - - H" IP+C>MA" ' EMU_PM+C>MA ' NOP JMPL-OP: IP+C>MA
6 1 >MAPT Ac5 M - - H" RP+C>MA" ' EMU_PM+C>MA ' NOP JMPL-OP: RP+C>MA
6 2 >MAPT Ac5 M - - H" SP+C>MA" ' EMU_PM+C>MA ' NOP JMPL-OP: SP+C>MA
6 3 >MAPT Ac3 M - - H" DP+C5>MA" ' EMU_PM+C5>MA ' NOP JMPL-OP: DP+C5>MA
6 4 >MAPT Ac5 M - - H" IP+C>MAu" ' EMU_PM+C>MA ' NOP JMPL-OP: IP+C>MAu
6 5 >MAPT Ac5 M - - H" RP+C>MAu" ' EMU_PM+C>MA ' NOP JMPL-OP: RP+C>MAu
6 6 >MAPT Ac5 M - - H" SP+C>MAu" ' EMU_PM+C>MA ' NOP JMPL-OP: SP+C>MAu
6 7 >MAPT Ac3 M - - H" DP+C5>MAu" ' EMU_PM+C5>MA ' NOP JMPL-OP: DP+C5>MAu
7 0 >MAPT Ac5 M - - H" IP-C>MA" ' EMU_PM-C>MA ' NOP JMPL-OP: IP-C>MA
7 1 >MAPT Ac5 M - - H" RP-C>MA" ' EMU_PM-C>MA ' NOP JMPL-OP: RP-C>MA
7 2 >MAPT Ac5 M - - H" SP-C>MA" ' EMU_PM-C>MA ' NOP JMPL-OP: SP-C>MA
7 3 >MAPT Ac3 M - - H" DP-C5>MA" ' EMU_PM-C5>MA ' NOP JMPL-OP: DP-C5>MA
7 4 >MAPT Ac5 M - - H" IP-C>MAu" ' EMU_PM-C>MA ' NOP JMPL-OP: IP-C>MAu
7 5 >MAPT Ac5 M - - H" RP-C>MAu" ' EMU_PM-C>MA ' NOP JMPL-OP: RP-C>MAu
7 6 >MAPT Ac5 M - - H" SP-C>MAu" ' EMU_PM-C>MA ' NOP JMPL-OP: SP-C>MAu
7 7 >MAPT Ac3 M - - H" DP-C5>MAu" ' EMU_PM-C5>MA ' NOP JMPL-OP: DP-C5>MAu
1 >AC AM0 FM A - - H" MA>AC" ' EMU_MA>AC ' NOP SIMPLE-OP: MA>AC
2 0 >ACRA AM0 A AC - - H" AC-1>ACC" ' EMU_AC-1>ACC ' NOP SIMPLE-OP: AC-1>ACC
2 1 >ACRA AM0 A AC - - H" AC+1>ACC" ' EMU_AC+1>ACC ' NOP SIMPLE-OP: AC+1>ACC
\ code type src dst Dsrc Ddst instr string emultion emulation operation
2 2 >ACRA AM0 A A - - H" AC-1>AC" ' EMU_AC-1>AC ' NOP SIMPLE-OP: AC-1>AC
2 3 >ACRA AM0 A A - - H" AC+1>AC" ' EMU_AC+1>AC ' NOP SIMPLE-OP: AC+1>AC
2 4 >ACRA AM0 AC A - - H" AC+CRY>AC" ' EMU_AC+CRY>AC ' NOP SIMPLE-OP: AC+CRY>AC
2 5 >ACRA AM0 AC A - - H" AC+CRY>AC" ' EMU_AC+CRY>AC ' NOP SIMPLE-OP: AC+CRY>AC
2 7 >ACRA AM0 tT A - - H" TR+1>AC" ' EMU_TR+1>AC ' NOP SIMPLE-OP: TR+1>AC
3 1 >ACRA AM0 - A - - H" 0>AC" ' EMU_0>AC ' NOP SIMPLE-OP: 0>AC
3 2 >ACRA AM0 tT A - - H" TR>AC" ' EMU_TR>AC ' NOP SIMPLE-OP: TR>AC
3 3 >ACRA AM0 D A - - H" DR>AC" ' EMU_DR>AC ' NOP SIMPLE-OP: DR>AC
1 >AC AM1 C A - - H" CRY>AC" ' EMU_CRY>AC ' NOP SIMPLE-OP: CRY>AC
2 >AC AM1 tT A - - H" TR>ACx" ' EMU_TR>AC ' NOP SIMPLE-OP: TR>ACx
3 >AC AM1 D A - - H" DR>ACx" ' EMU_DR>AC ' NOP SIMPLE-OP: DR>ACx
1 >AC AM2 c8 A - - H" C8>AC" ' EMU_C8>AC ' NOP SIMPLE-OP: C8>AC
2 1 >ACRA AM2 AD A - - H" AC_XOR_DR>AC" ' EMU_AC_XOR_DR>AC ' NOP SIMPLE-OP: AC_XOR_DR>AC
2 2 >ACRA AM2 tT A - - H" TR+1>ACx" ' EMU_TR+1>AC ' NOP SIMPLE-OP: TR+1>ACx
2 4 >ACRA AM2 AtT AC - - H" AC-TR>ACC" ' EMU_AC-TR>ACC ' NOP SIMPLE-OP: AC-TR>ACC
2 5 >ACRA AM2 AtT AC - - H" AC+TR>ACC" ' EMU_AC+TR>ACC ' NOP SIMPLE-OP: AC+TR>ACC
2 6 >ACRA AM2 AtT A - - H" AC-TR>AC" ' EMU_AC-TR>AC ' NOP SIMPLE-OP: AC-TR>AC
2 7 >ACRA AM2 AtT A - - H" AC+TR>AC" ' EMU_AC+TR>AC ' NOP SIMPLE-OP: AC+TR>AC
1 0 >ACPT AM3 A A - - H" AC_SL" ' EMU_AC_SL ' NOP SIMPLE-OP: AC_SL
\ code type src dst Dsrc Ddst instr string emultion emulation operation
2 0 >ACPT AM3 AC AC - - H" AC_RLC" ' EMU_AC_RLC ' NOP SIMPLE-OP: AC_RLC
1 1 >ACPT AM3 A A - - H" AC_RL" ' EMU_AC_RL ' NOP SIMPLE-OP: AC_RL
2 1 >ACPT AM3 At A - - H" AC_RL_TR" ' EMU_AC_RL_TR ' NOP SIMPLE-OP: AC_RL_TR
3 1 >ACPT AM3 AD A - - H" AC_RL_DR" ' EMU_AC_RL_DR ' NOP SIMPLE-OP: AC_RL_DR
1 2 >ACPT AM3 A A - - H" AC_SR" ' EMU_AC_SR ' NOP SIMPLE-OP: AC_SR
2 2 >ACPT AM3 AC AC - - H" AC_RRC" ' EMU_AC_RRC ' NOP SIMPLE-OP: AC_RRC
1 3 >ACPT AM3 A A - - H" AC_RR" ' EMU_AC_RR ' NOP SIMPLE-OP: AC_RR
2 3 >ACPT AM3 AT A - - H" AC_RR_TR" ' EMU_AC_RR_TR ' NOP SIMPLE-OP: AC_RR_TR
3 3 >ACPT AM3 AD A - - H" AC_RR_DR" ' EMU_AC_RR_DR ' NOP SIMPLE-OP: AC_RR_DR
1 4 >ACPT AM3 A A - - H" AC_SRB" ' EMU_AC_SRB ' NOP SIMPLE-OP: AC_SRB
2 4 >ACPT AM3 A A - - H" AC_RRB" ' EMU_AC_RRB ' NOP SIMPLE-OP: AC_RRB
3 4 >ACPT AM3 AD A - - H" AC_RRB_AC" ' EMU_AC_RRB_AC ' NOP SIMPLE-OP: AC_RRB_AC
1 5 >ACPT AM3 At A - - H" AC_RRB_TR" ' EMU_AC_RRB_TR ' NOP SIMPLE-OP: AC_RRB_TR
2 5 >ACPT AM3 AD A - - H" AC_RRB_DR" ' EMU_AC_RRB_DR ' NOP SIMPLE-OP: AC_RRB_DR
1 6 >ACPT AM3 AtT A - - H" MPY>AC" ' EMU_MPY>AC ' NOP SIMPLE-OP: MPY>AC
2 6 >ACPT AM3 AtTDC A - - H" DIV>AC" ' EMU_DIV>AC ' NOP SIMPLE-OP: DIV>AC
7 5 2 >MAPTR - - - - H" RP-4>MAu" ' EMU_RP-4>MAu ' NOP SIMPLE-OP: RP-4>MAu
5 4 0 >MAPTR - - - - H" TR>MAu" ' EMU_TR>MAu ' NOP SIMPLE-OP: TR>MAu
6 5 2 >MAPTR - - - - H" RP+4>MAu" ' EMU_RP+4>MAu ' NOP SIMPLE-OP: RP+4>MAu
\ code type src dst Dsrc Ddst instr string emultion emulation operation
5 4 1 >MAPTR - - - - H" TR+2>MAu" ' EMU_TR+2>MAu ' NOP SIMPLE-OP: TR+2>MAu
6 4 1 >MAPTR - - - - H" IP+2>MAu" ' EMU_IP+2>MAu ' NOP SIMPLE-OP: IP+2>MAu
1 6 1 >MAPTR - - - - H" MA+2>MAu" ' EMU_MA+2>MAu ' NOP SIMPLE-OP: MA+2>MAu
6 6 2 >MAPTR - - - - H" SP+4>MAu" ' EMU_SP+4>MAu ' NOP SIMPLE-OP: SP+4>MAu
6 6 4 >MAPTR - - - - H" SP+8>MAu" ' EMU_SP+8>MAu ' NOP SIMPLE-OP: SP+8>MAu
7 5 4 >MAPTR - - - - H" RP-8>MAu" ' EMU_RP-8>MAu ' NOP SIMPLE-OP: RP-8>MAu
7 6 2 >MAPTR - - - - H" SP-4>MAu" ' EMU_SP-4>MAu ' NOP SIMPLE-OP: SP-4>MAu
7 2 2 >MAPTR - - - - H" SP-4>MA" ' EMU_SP-4>MA ' NOP SIMPLE-OP: SP-4>MA
6 1 2 >MAPTR - - - - H" RP+4>MA" ' EMU_RP+4>MA ' NOP SIMPLE-OP: RP+4>MA
6 5 4 >MAPTR - - - - H" RP+8>MAu" ' EMU_RP+8>MAu ' NOP SIMPLE-OP: RP+8>MAu
\ comment - - - - H" (SOS>TR)" ' EMU_(SOS>TR) ' NOP SIMPLE-OP: (SOS>TR)
\ comment - - - - H" (PUSH}" ' EMU_(PUSH} ' NOP SIMPLE-OP: (PUSH}
\ comment - - - - H" (POP)" ' EMU_(POP) ' NOP SIMPLE-OP: (POP)
\ comment - - - - H" (RP@>TR)" ' EMU_(RP@>TR) ' NOP SIMPLE-OP: (RP@>TR)
0 >XB - - - - H" AMD0_d" ' EMU_AMD0 ' EMU_dfr SIMPLE-OP: AMD0_d
1 >XB - - - - H" AMD1_d" ' EMU_AMD1 ' EMU_dfr SIMPLE-OP: AMD1_d
2 >XB - - - - H" AMD2_d" ' EMU_AMD2 ' EMU_dfr SIMPLE-OP: AMD2_d
3 >XB - - - - H" AMD3_d" ' EMU_AMD3 ' EMU_dfr SIMPLE-OP: AMD3_d
Done

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o FPGA4th

By: John Hart on Thu, 25 Nov 2021

129John Hart
server_pubkey.txt

rocksolid light 0.9.8
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