On Saturday, December 11, 2021 at 4:43:52 AM UTC+10, Paul Rubin wrote:
> Rick C <gnuarm.del...@gmail.com> writes:
> > the GA144 ... It's an embedded computer, an MCU which has a very
> > different application space. Unfortunately, the GA144 has no
> > identified application space, so it has no market and no sales to
> > speak of. I bought three of them. Does that count?
> If you bought 3 chips that's 432 processors, so it's a start ;-).
>
> More srsly an MCU with ~128 bytes of ram (like the midrange ATTinys) is
> perfectly useful and respectable. I've been programming those things a
> little bit recently. But, they usually have 4K or more of program store
> on the MCU. Having to use the GA144 ram as program memory (sharing it
> with application data), or being limited to the 64 words (= 144 bytes)
> of mask rom at each node, is horribly constricting, as the code on the
> GA site shows. They had to do crazy things to make even simple programs
> fit.

If they had 4 cores with 1MB each, with one having access to all MB, and shared memory in between (either as part of the 4MB, or in-between the 1MB areas) 20 years ago, we would go yahoo! The data passing would be really quick, even just pointer passing or just that a preknown area is now free, and to swap from the other area when you are finished with it. and The main cpu could use the other CPUs for parallel processing. It would look like either a big memory segment on the middle, with 4 cores around it, or 4 cores in a pool of memory )sea of memory). We can see twenty of years ago, that would be revolutionary, for us, but this also applies to how the current chips could have been designed, with their shared memory in between the chips for quick message passing, and substantial code and data space. Using dual memory access techniques, every inner core has direct access to 16 cores of memory. If only the energy could be low enough, a large amount of energy beats the existing cons scheme, when used. I would make it so that any segment of memory is not used, it is turned off. But, in this scheme, a simple come file system could use unused segments as long term storage for data not requiring high speed use or access, put aside. With the data with higher need being parked close to where it's to be used, preferably in the processors prime memory space, if any left (for efficiency). But, you can change your ratio here, to suite potential applications. At the moment, you combine present memory, for a high compatibility version at virtually the same energy requirements. Going a step up, you take all that plus drop every second core, to divert to memory, to enlarge that memory pool. With both, you can use the existing communications, or memory message passing, with existing comparability. You have the processors and memory stripped, but you could do rows, where a CPU can reach 6 memory spaces. Still not much memory, but easier. Now, if you replace more cores, you get to a processors surrounded by memory. This might be small or as large as required.

Now, if we step back. We realise we can have one core with a large memory access, passing work to the array. But, the array can still accept data directly off chip, independently of the main processor, and process it across the chip and pas it out, and still maintain soft compatibility with the current chip. But, here, we can see there is a further opportunity. The main chip could have access to all memory on chip, and the ability to use an attached memory die in a cheap multi chip module type. Which memory that is addressed, is based on what part of the address space which is used. Slow down only happens when there is conflicting access requests, but proper programming only does that when needed. If you have to depend on compensating for the programmer doing the wrong thing, you reduce fine efficiency. You should depend on the programmer normally doing the right thing (outside of errors). Now, performance from the off memory die can be based on the memory being serialed in from off chip into a memory segment that the processor then performs as it loads, in n associative memory model. In cheap mass memory models, they rely on this serial segment nature, so, you are still going have to wait for that memory to perform anyway. Here, if you do it right, you only really pay if you branch forwards. In other words, the segment is a little cache. But, the present misc memory is within these sorts of memory chip segment ranges. Now, you have a chip you can package with or without extra memory.

Now, one other great improvement, is to switch to phase signalling, even for on chip inter processor communications. You still maintain some comparability, but greatly expand usability and programming ease.

The memory as the wire.

Anyway, why can't we do memory as a grid, using silicon on insulator capacitive memory techniques. No transistors needed in the grid, greater density.. Speed and reliability? But, there are a lot of things which have to hang around before they are used.
How come they weren't doing stuff like this?

> It also didn't help that the Polyforth VM that they include in the rom
> on 3 the of the GA144 nodes is completely undocumented. They were very
> eager for someone to target a C compiler to the GA144, so I remember
> looking at the code for that VM but finding it more confusing than I was
> willing to deal with.

Yes, those were some obvious advancements. But, again, a single processor with a big memory, could have done that at speed. Passing out work to the array. An interrupt being replaced by a communications from a processor that either receives a pull on a pin, or decided it needs one. In geoworks, they used a simple control passing model. Being the programmer with a single code set, you control a the responses, so it's not a problem. The main processor can perform units of work, occasionally checking if a message is to be serviced. The processor sending the message, can already be working on a response and parallel, or even have surrounding processors contributing. You are at liberty to make it work as best as you can.

...

> So if they replaced half the GA144's nodes with ram, they might have
> been better off.

...

> Wayne Morellini is right that we don't have ironclad mathematical proof
> that GA isn't getting billion-dollar deals from hush-hush customers and
> keeping quiet about them. But, in the real world, such deals would
> result in financial expansion of the company, that would be visible as
> new hiring, new products, carefully worded announcements, GA staff
> driving Ferraris around, etc. So there is decent practical inference
> that such deals aren't happening.

Lol! They should be signing deals worth billions, but the indication is, they have been surviving, which means they are maybe doing little more than what we already know, tech development demos for companies looking at using their products. But, then we don't know about other funding. I, in no way, think there are billions flowing around. However, maybe under SF or GA, they were over here doing stuff with the bionic ear mob, and after they announced a super hearing aid (not to mention the existing internal hearing aid could benefit) and received some advise ce how it could be fine easier, and a cheaper version came out.

Where this is a big market, is as an alternative to arm. AMD, had multiple times tried to do it with mips (or was it SPARC). You could approach such a company with a sweet heart of the sweet heart deals. A separate company owned by AMD mostly. Joint development of an advanced ARM alternative. They contribute, GA designs, they contribute to the design, and GA contributes a better design, and so on, until you reach a very good design that AMD is very happy with on performance. You may still offer custom design, you offer something for the current GA market, the MCU market, and the ARM market. AMD, gets three new product lines they don't service very much, and a custom design facility for big customers, that say Google could approach to design a new device. AMD staff learn how to design this stuff, and current staff, can retire. Then the AMD staff design increasingly better stuff to compete with arm etc. AMD can then archive the sort of portable device penetration they always wanted. Notice, here I'm saying, the main design to sell on, is the advanced 32 bit+ design.

On Sat, 11 Dec 2021, 13:51 Hugh Aguilar, <hughaguilar96@gmail.com> wrote:
On Friday, December 10, 2021 at 11:43:52 AM UTC-7, Paul Rubin wrote:
> Wayne Morellini is right that we don't have ironclad mathematical proof
> that GA isn't getting billion-dollar deals from hush-hush customers and
> keeping quiet about them. But, in the real world, such deals would
> result in financial expansion of the company, that would be visible as
> new hiring, new products, carefully worded announcements, GA staff
> driving Ferraris around, etc. So there is decent practical inference
> that such deals aren't happening.

When I first heard about the GA144, my assumption was that the
"killer app" was encryption cracking. This involves trying out a lot of
possible keys --- the keys are chosen by some heuristic to hopefully
try out the more likely ones first --- the try-out keys still have to be
tested though, and this can be done in parallel.

As for Charles Moore driving a Ferrari, this seems unlikely.
If he is making money from the NSA, he would want to keep a low profile.
Most people would consider this to be dirty money.

Apart from encryption, you know, a lot of gpu's go to crypto currency schemes. Both of these apps, as special purpose funding apps. One allows Chuck to drive around a red Tesla utility truck. But seriously, server stuff is a big market. Communications too.