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programming / comp.lang.vhdl / latest

Re: Components in if-else statement (thread)

comp.lang.vhdl

Posted: 8 Days 16 Hours ago by: Nicolas Matringe

[...] You can not use the "if <...> generate" with a signal. It doesn't make any sense. Your code doesn't make much sense either. It looks like you're using VHDL as a programming language, which it is definitely not. Nicolas

Components in if-else statement

comp.lang.vhdl

Posted: 14 Days 17 Hours ago by: tushar sharma

--------------MAIN FILE------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.ALL; entity major_8_bit is port( N: in std_logic_vector(7 downto 0); Result: out std_logic_vecto

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