Rocksolid Light

Welcome to novaBBS (click a section below)

mail  files  register  nodelist  faq  

If it has syntax, it isn't user friendly.


programming / comp.lang.vhdl

1
SubjectRepliesLast Message
o How to manage multiple testcases in a testbench

By: Benjamin Couillard on Mon, 19 Jul 2021

2

3 Days 17 Hours ago

By: KJ

o flipflop testbenech

By: Dương Dương on Wed, 12 May 2021

1

2 Months 18 Days ago

By: Michael Kellett

o accumulator

By: Dương Dương on Wed, 12 May 2021

0

2 Months 19 Days ago

By: Dương Dương

o 3 bit comparator

By: Dương Dương on Sun, 28 Mar 2021

3

3 Months 30 Days ago

By: Charles Bailey

o Kudos to Sigasi

By: HT-Lab on Thu, 18 Mar 2021

2

4 Months 1 Day ago

By: Jim Lewis

o Multiple Drive Error

By: Ceyhun_Sarıkaya on Thu, 18 Mar 2021

1

4 Months 13 Days ago

By: Buzz McCool

o Re: FIGLIO DI PUTTANONA PAOLO BARRAI ("IL PEDOFILO DEL BITCOIN": COME

By: Andreas Nigg on Sun, 31 Jan 2021

0

6 Months ago

By: Andreas Nigg

o Re: FIGLIO DI PUTTANONA PAOLO BARRAI ("IL PEDOFILO DEL BITCOIN": COME

By: FRANCESCO CARBONE US on Wed, 18 Nov 2020

2

7 Months 10 Days ago

By: LUIGI ROTUNNO GRUPO

o For_example,_with_the_swap_input_in_it,_"from_0x45F3

By: Aykut Yıldız on Wed, 2 Dec 2020

1

7 Months 10 Days ago

By: gnuarm.del...@gmail.

o use IEEE.STD_LOGIC_UNSIGNED.ALL;

By: gnuarm.del...@gmail. on Mon, 14 Dec 2020

2

7 Months 16 Days ago

By: gnuarm.del...@gmail.

o User Defined Operators

By: gnuarm.del...@gmail. on Tue, 15 Dec 2020

0

7 Months 16 Days ago

By: gnuarm.del...@gmail.

o Re: 'image of Enumerated Types

By: Jim Lewis on Mon, 16 Nov 2020

1

8 Months 13 Days ago

By: gnuarm.del...@gmail.

o Re: printf() function like C in VHDL ?

By: francis cagney on Fri, 13 Nov 2020

0

8 Months 18 Days ago

By: francis cagney

o Attribute default

By: Rick C on Sun, 8 Nov 2020

2

8 Months 21 Days ago

By: Rick C

o Re: "Non-static aggregate with multiple choices has non-static others choi

By: Rick C on Sat, 7 Nov 2020

0

8 Months 24 Days ago

By: Rick C

o Active-HDL issues with another VHDL-2008 construct

By: Rick C on Fri, 30 Oct 2020

3

8 Months 27 Days ago

By: Rick C

o "Missing one or more actuals for elements of formal "a_b"."

By: Hugo Souza on Mon, 2 Nov 2020

1

8 Months 29 Days ago

By: Anssi Saari

o integer_vector

By: Rick C on Sun, 25 Oct 2020

2

9 Months 4 Days ago

By: Rick C

o Implementing entity from a different library

By: Andrey Kapustin on Sat, 24 Oct 2020

0

9 Months 7 Days ago

By: Andrey Kapustin

o Aggregates on the Left Side of the Assignment

By: Rick C on Sat, 17 Oct 2020

4

9 Months 9 Days ago

By: Rick C

o Time

By: Rick C on Fri, 16 Oct 2020

0

9 Months 16 Days ago

By: Rick C

o Re: VHDL compiler and simulator for student

By: rezaul karim on Mon, 5 Oct 2020

2

9 Months 26 Days ago

By: Charles Bailey

o VHDL Don't Care

By: Rick C on Thu, 1 Oct 2020

3

9 Months 28 Days ago

By: KJ

o 64 Bit Integers

By: Rick C on Tue, 29 Sep 2020

3

9 Months 30 Days ago

By: Rick C

o Variable Registers

By: Rick C on Tue, 29 Sep 2020

0

10 Months 2 Days ago

By: Rick C

o VHDL, easy peasy, right?

By: Rick C on Thu, 24 Sep 2020

6

10 Months 5 Days ago

By: Rick C

o vhdl help project

By: Babyla on Fri, 25 Sep 2020

2

10 Months 6 Days ago

By: Rick C

o Error of IP of CI 7483

By: Victor Salazar on Tue, 22 Sep 2020

6

10 Months 8 Days ago

By: KJ

o VHDL Static Signals

By: Rick C on Mon, 21 Sep 2020

2

10 Months 9 Days ago

By: Rick C

o VHDL Real Rounding

By: Rick C on Fri, 18 Sep 2020

7

10 Months 10 Days ago

By: Rick C

o Clocked Process, but Outside of the Clocked IF

By: Rick C on Tue, 15 Sep 2020

9

10 Months 11 Days ago

By: Rick C

o Crikey!

By: Rick C on Fri, 18 Sep 2020

5

10 Months 13 Days ago

By: gtwrek

o TCL Error

By: Kr. Sheelvardhan Ban on Thu, 17 Sep 2020

3

10 Months 14 Days ago

By: HT-Lab

o Reverse ?? Operator

By: Rick C on Tue, 8 Sep 2020

9

10 Months 14 Days ago

By: HT-Lab

o Generics Default vs.

By: Rick C on Sun, 13 Sep 2020

2

10 Months 18 Days ago

By: Rick C

o Active HDL

By: Rick C on Wed, 9 Sep 2020

3

10 Months 21 Days ago

By: Rick C

o What is a Processor and Software in Context of Reliability Analysis?

By: Rick C on Thu, 3 Sep 2020

0

10 Months 28 Days ago

By: Rick C

o System Verilog

By: avanikvh123 on Wed, 20 May 2020

3

11 Months 6 Days ago

By: Rick C

o Code Review: SPI Transmitter

By: Rob Gaddi on Mon, 17 Jun 2019

10

11 Months 20 Days ago

By: Rob Anderson

o VHDL2019 info

By: HT-Lab on Thu, 25 Jun 2020

0

1 Year 1 Month ago

By: HT-Lab

o process problem in VHDL

By: albert.pierre1000 on Tue, 23 Jun 2020

0

1 Year 1 Month ago

By: albert.pierre1000

o breaking an image into blocks and compute histogram of each block

By: rsdeshwal on Fri, 15 May 2020

4

1 Year 1 Month ago

By: Nikolaos Kavvadias

o Newbee in VHDL ... why is this not working?

By: Christoph Linden on Thu, 14 May 2020

13

1 Year 2 Months ago

By: Rick C

o fixed point tools

By: zack sheffield on Thu, 7 May 2020

0

1 Year 2 Months ago

By: zack_sheffield

o Re: free waveform drawing tool

By: gabriel.kudishevich on Wed, 29 Apr 2020

0

1 Year 3 Months ago

By: gabriel.kudishevich

o PipelineC - Autopipeline your VHDL and more! Help wanted!

By: Julian Kemmerer on Mon, 23 Mar 2020

0

1 Year 4 Months ago

By: Julian Kemmerer

o Kickstart your FPGA or ASIC verification with free, open source VHDL i

By: espen.tallaksen@bitv on Fri, 20 Mar 2020

0

1 Year 4 Months ago

By: espen.tallaksen@bitv

o Re: Memory Initialization Files in Modelsim

By: gemmagilmore on Thu, 19 Mar 2020

0

1 Year 4 Months ago

By: gemmagilmore

o Std_logic_vector assignment with variable length

By: taylor.cj39 on Fri, 6 Mar 2020

12

1 Year 4 Months ago

By: Rick C

o Open Source Silicon IP Survey

By: mag on Fri, 28 Feb 2020

0

1 Year 5 Months ago

By: mag

o Re: VHDL to schematic conversion

By: historytimes on Tue, 25 Feb 2020

0

1 Year 5 Months ago

By: historytimes

o Can you look into your design using an assert statement?

By: Volker Kriszeit on Mon, 17 Feb 2020

6

1 Year 5 Months ago

By: Volker Kriszeit

o vhdl code not working

By: sweetymalutty on Thu, 6 Feb 2020

7

1 Year 5 Months ago

By: Rick C

o Re: 2 digit dice (random counter 1 - 6)

By: dil91255 on Sat, 15 Feb 2020

0

1 Year 5 Months ago

By: dil91255

o Re: Squaring of a binary number

By: favouriteangels45 on Mon, 3 Feb 2020

0

1 Year 5 Months ago

By: favouriteangels45

o needs help with vhdl coding

By: sweetymalutty on Fri, 31 Jan 2020

2

1 Year 6 Months ago

By: Thomas Stanka

o Array of std_logic_vector

By: digitalguy33 on Tue, 28 Jan 2020

4

1 Year 6 Months ago

By: KJ

o International Journal of Embedded Systems and Applications (IJESA)

By: ranulflambard20 on Fri, 3 Jan 2020

0

1 Year 6 Months ago

By: ranulflambard20

o vhdl port connection length error

By: silverace99 on Mon, 2 Dec 2019

7

1 Year 7 Months ago

By: HT-Lab

o Error in vhdl code

By: sweetymalutty on Sun, 8 Dec 2019

3

1 Year 7 Months ago

By: sweetymalutty

o VHDL'2019 is ratified !

By: the.yasep on Sat, 7 Sep 2019

8

1 Year 7 Months ago

By: kevin.m.neilson

o É_SATANISTA_BASTARDAMENTE_ASSASSINA:_ELISA_COGNO_DI

By: ANTONIO BINNI - BAST on Tue, 12 Nov 2019

0

1 Year 8 Months ago

By: ANTONIO BINNI - BAST

o Insert transient voltage on internal signal of a module - Verilog

By: Raphael Viera on Tue, 22 Oct 2019

1

1 Year 9 Months ago

By: HT-Lab

o Insert stimulus internal module signal

By: Raphael Viera on Tue, 22 Oct 2019

0

1 Year 9 Months ago

By: Raphael Viera

o Bit vs. std_logic for description of internal structures

By: Maciej Sobczak on Mon, 7 Oct 2019

9

1 Year 9 Months ago

By: cmelias

o How to write a correct code to do 2 writes to an array on same cycle?

By: Weng Tianxiang on Tue, 24 Sep 2019

2

1 Year 10 Months ago

By: Rick C

o The meaning of code coverage in VHDL

By: Maciej Sobczak on Tue, 24 Sep 2019

10

1 Year 10 Months ago

By: HT-Lab

o IEEE Std 1076-2019

By: HT-Lab on Fri, 6 Sep 2019

6

1 Year 10 Months ago

By: Rick C

o PipelineC (again), dct example, looking for help/interest

By: Julian Kemmerer on Sat, 7 Sep 2019

0

1 Year 10 Months ago

By: Julian Kemmerer

o What happened to the osvvm website!?

By: Reuven on Fri, 23 Aug 2019

3

1 Year 10 Months ago

By: HT-Lab

o Re: Microsemi Libero on Linux

By: the.yasep on Sun, 1 Sep 2019

0

1 Year 10 Months ago

By: the.yasep

o Re: GALs and VHDL

By: silverdr on Sun, 1 Sep 2019

0

1 Year 10 Months ago

By: silverdr

o Chdl 8 bit counter

By: kadir284197 on Tue, 20 Aug 2019

1

1 Year 11 Months ago

By: Rick C

o HDLC Clocking

By: digitalguy33 on Sat, 17 Aug 2019

2

1 Year 11 Months ago

By: Richard Damon

o Why differences between Merly-type and Moore-type clock-gated state

By: Weng Tianxiang on Fri, 9 Aug 2019

27

1 Year 11 Months ago

By: Rick C

o Re: FIGLIO DI PUTTANONA PAOLO BARRAI ("IL PEDOFILO DEL BITCOIN": COME

By: INCULAIBAMBINI PAOLO on Wed, 14 Aug 2019

0

1 Year 11 Months ago

By: INCULAIBAMBINI PAOLO

o Codewright Setup Files

By: Rick C on Sat, 10 Aug 2019

0

1 Year 11 Months ago

By: Rick C

o attribute of a record member

By: daltonj on Sat, 3 Aug 2019

1

1 Year 11 Months ago

By: Rob Gaddi

o Replacing xilinx "ASYNC_REG" directive with a TCL script method.

By: Edward Fisher on Mon, 15 Jul 2019

4

2 Years ago

By: HT-Lab

o Re: FIGLIO DI PUTTANONA PAOLO BARRAI ("IL PEDOFILO DEL BITCOIN": COME

By: RICICLASOLDIMAFIOSI on Mon, 15 Jul 2019

0

2 Years ago

By: RICICLASOLDIMAFIOSI

o Re: Cadence Simvision question

By: pursh012 on Sat, 22 Jun 2019

0

2 Years 1 Month ago

By: pursh012

o output <= registers(to_integer(address)) and intentional meta values

By: a.fiergolski on Tue, 18 Jun 2019

7

2 Years 1 Month ago

By: a.fiergolski

o IL VERME CRIMINALE PAOLO BARRAI (LINKEDIN) E' STATO IL REGISTA

By: INCULAIBAMBINI PAOLO on Fri, 14 Jun 2019

0

2 Years 1 Month ago

By: INCULAIBAMBINI PAOLO

o Safe State Machine with Conditional when others

By: digitalguy33 on Sat, 1 Jun 2019

4

2 Years 1 Month ago

By: Rick C

o Re: METHOD: TestBench How to? Verification over "Generic" parameters

By: Thomas Stanka on Mon, 3 Jun 2019

0

2 Years 1 Month ago

By: Thomas Stanka

o SD slave with Samsung flash.

By: pini on Tue, 28 May 2019

0

2 Years 2 Months ago

By: pini

1

There are currently 399 users online
Total messages: 1,694,757

rocksolid light 0.7.0
clearneti2ptor