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tech / sci.electronics.design / really slow PLL

SubjectAuthor
* really slow PLLJohn Larkin
+* Re: really slow PLLPhil Hobbs
|`* Re: really slow PLLJohn Larkin
| +* Re: really slow PLLPhil Hobbs
| |`* Re: really slow PLLjlarkin
| | `* Re: really slow PLLPhil Hobbs
| |  +* Re: really slow PLLjlarkin
| |  |`* Re: really slow PLLPhil Hobbs
| |  | `- Re: really slow PLLjlarkin
| |  `* Re: really slow PLLLes Cargill
| |   `- Re: really slow PLLJohn Larkin
| +* Re: really slow PLLbitrex
| |+- Re: really slow PLLjlarkin
| |`* Re: really slow PLLLes Cargill
| | `* Re: really slow PLLLasse Langwadt Christensen
| |  +- Re: really slow PLLbitrex
| |  `- Re: really slow PLLLes Cargill
| `* Re: really slow PLLMartin Brown
|  +* Re: really slow PLLjlarkin
|  |`* Re: really slow PLLMartin Brown
|  | `- Re: really slow PLLjlarkin
|  +* Re: really slow PLLPhil Hobbs
|  |`- Re: really slow PLLjlarkin
|  `* Re: really slow PLLbitrex
|   +* Re: really slow PLLLasse Langwadt Christensen
|   |`* Re: really slow PLLbitrex
|   | `* Re: really slow PLLJohn Walliker
|   |  +* Re: really slow PLLMartin Brown
|   |  |+* Re: really slow PLLbitrex
|   |  ||+* Re: really slow PLLbitrex
|   |  |||`* Re: really slow PLLLasse Langwadt Christensen
|   |  ||| `- Re: really slow PLLbitrex
|   |  ||+- Re: really slow PLLDon Y
|   |  ||`* Re: really slow PLLMartin Brown
|   |  || `* Re: really slow PLLDon Y
|   |  ||  `* Re: really slow PLLJohn Walliker
|   |  ||   `- Re: really slow PLLDon Y
|   |  |`* Re: really slow PLLJohn Larkin
|   |  | `* Re: really slow PLLMartin Brown
|   |  |  `- Re: really slow PLLPhil Hobbs
|   |  `- Re: really slow PLLDon Y
|   +* Re: really slow PLLPhil Hobbs
|   |`* Re: really slow PLLbitrex
|   | `* Re: really slow PLLPhil Hobbs
|   |  `* Re: really slow PLLjlarkin
|   |   `* Re: really slow PLLLes Cargill
|   |    `* Re: really slow PLLjlarkin
|   |     `* Re: really slow PLLLes Cargill
|   |      +* Re: really slow PLLjlarkin
|   |      |`- Re: really slow PLLLes Cargill
|   |      `* Re: really slow PLLDon
|   |       `- Re: really slow PLLLes Cargill
|   `* Re: really slow PLLDon Y
|    +* Re: really slow PLLbitrex
|    |`- Re: really slow PLLDon Y
|    +* Re: really slow PLLDon
|    |`* Re: really slow PLLDon Y
|    | `* Re: really slow PLLDon
|    |  `* Re: really slow PLLDon Y
|    |   +* Re: really slow PLLDon
|    |   |`* Re: really slow PLLDon Y
|    |   | `* Re: really slow PLLDon
|    |   |  +- Re: really slow PLLDon Y
|    |   |  `* Re: really slow PLLClifford Heath
|    |   |   `- Re: really slow PLLGerhard Hoffmann
|    |   `* Re: really slow PLLLasse Langwadt Christensen
|    |    `* Re: really slow PLLJoe Gwinn
|    |     `* Re: really slow PLLDon Y
|    |      `* Re: really slow PLLLasse Langwadt Christensen
|    |       `* Re: really slow PLLDon Y
|    |        `* Re: really slow PLLLasse Langwadt Christensen
|    |         `* Re: really slow PLLDon Y
|    |          `- Re: really slow PLLDon Y
|    `* Re: really slow PLLjlarkin
|     +- Re: really slow PLLJan Panteltje
|     `* Re: really slow PLLJohn Walliker
|      +- Re: really slow PLLDon Y
|      `- Re: really slow PLLClifford Heath
+- Re: really slow PLLJan Panteltje
+* Re: really slow PLLGerhard Hoffmann
|`* Re: really slow PLLjlarkin
| +* Re: really slow PLLGerhard Hoffmann
| |+* Re: really slow PLLPhil Hobbs
| ||`* Re: really slow PLLGerhard Hoffmann
| || `* Re: really slow PLLPhil Hobbs
| ||  `* Re: really slow PLLClifford Heath
| ||   `* Re: really slow PLLMartin Brown
| ||    `* Re: really slow PLLPhil Hobbs
| ||     `* Re: really slow PLLJoe Gwinn
| ||      `* Re: really slow PLLGerhard Hoffmann
| ||       +* Re: really slow PLLJoe Gwinn
| ||       |+* Re: really slow PLLGerhard Hoffmann
| ||       ||`* Re: really slow PLLJoe Gwinn
| ||       || `* Re: really slow PLLPhil Hobbs
| ||       ||  `- Re: really slow PLLGerhard Hoffmann
| ||       |`* Re: really slow PLLPhil Hobbs
| ||       | `* Re: really slow PLLJoe Gwinn
| ||       |  `* Re: really slow PLLPhil Hobbs
| ||       |   `- Re: really slow PLLGerhard Hoffmann
| ||       `* Re: really slow PLLPhil Hobbs
| ||        +* Re: really slow PLLjlarkin
| ||        `* Re: really slow PLLMartin Brown
| |+- Re: really slow PLLJan Panteltje
| |`- Re: really slow PLLClifford Heath
| `* Re: really slow PLLCydrome Leader
+* Re: really slow PLLwhit3rd
+- Re: really slow PLLClive Arthur
+* Re: really slow PLLLasse Langwadt Christensen
+- Re: really slow PLLLes Cargill
+- Re: really slow PLLjlarkin
`- Re: really slow PLLJasen Betts

Pages:1234567
really slow PLL

<qd2hdhhs6bnndjs4likrvlq9jt6q5deebo@4ax.com>

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https://www.novabbs.com/tech/article-flat.php?id=101854&group=sci.electronics.design#101854

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From: jlar...@highland_atwork_technology.com (John Larkin)
Newsgroups: sci.electronics.design
Subject: really slow PLL
Date: Wed, 20 Jul 2022 16:20:57 -0700
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 by: John Larkin - Wed, 20 Jul 2022 23:20 UTC

Suppose I have several rackmount boxes and each has a BNC connector on
the back. Each of them has an open-drain mosfet, a weak pullup, and a
lowpass filtered schmitt gate back into our FPGA.

I can daisy-chain several boxes with BNC cables and tees.

Each box has a 40 MHz VCXO and I want to phase-lock them, or at least
time-align them to always be the same within a few microseconds,
longterm.

I could call one the leader (not "master") and make the others
followers (not "slaves") and have the leader make an active low pulse
maybe once a second. A follower would use her (not "his") clock to
measure the incoming period and tweak its local VCXO in the right
direction. That should work.

Don't GPS receivers lock their 10 MHz oscillators to a 1 PPS pulse
from the satellites?

My system should work from a 1 PPS GPS pulse too, all boxes as
followers.

The PLL algorithm might be interesting.

Re: really slow PLL

<daf0c8cf-07ea-241b-2e4e-bfe2bbaa6f63@electrooptical.net>

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https://www.novabbs.com/tech/article-flat.php?id=101855&group=sci.electronics.design#101855

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From: pcdhSpam...@electrooptical.net (Phil Hobbs)
Newsgroups: sci.electronics.design
Subject: Re: really slow PLL
Date: Wed, 20 Jul 2022 19:32:20 -0400
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 by: Phil Hobbs - Wed, 20 Jul 2022 23:32 UTC

John Larkin wrote:
>
>
> Suppose I have several rackmount boxes and each has a BNC connector on
> the back. Each of them has an open-drain mosfet, a weak pullup, and a
> lowpass filtered schmitt gate back into our FPGA.
>
> I can daisy-chain several boxes with BNC cables and tees.
>
> Each box has a 40 MHz VCXO and I want to phase-lock them, or at least
> time-align them to always be the same within a few microseconds,
> longterm.
>
> I could call one the leader (not "master") and make the others
> followers (not "slaves") and have the leader make an active low pulse
> maybe once a second. A follower would use her (not "his") clock to
> measure the incoming period and tweak its local VCXO in the right
> direction. That should work.
>
> Don't GPS receivers lock their 10 MHz oscillators to a 1 PPS pulse
> from the satellites?
>
> My system should work from a 1 PPS GPS pulse too, all boxes as
> followers.
>
> The PLL algorithm might be interesting.
>

It's certainly possible. However, within whatever tiny loop bandwidth
you wound up with, the lockers would still have

20 log(40e6) = 152 dB

higher phase noise than the lockee.

It would be interesting to do the math to see whether it's possible to
generate a concensus lock for the group: if you get everybody close
enough, just sum their sine wave outputs and lock each one of them to
that, with some bit of AC coupling or something so that they don't all
wander together off to the edge of the tuning range.

Maybe have one doing the locking with a phase shifter and the others
with VCOs, or something like that.

Definitely a partly-baked idea, but surely one could do better than 152 dB!

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

Re: really slow PLL

<pq5hdh9oeleu54rljjk3r1bk3vfgj9dni0@4ax.com>

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From: jlar...@highland_atwork_technology.com (John Larkin)
Newsgroups: sci.electronics.design
Subject: Re: really slow PLL
Date: Wed, 20 Jul 2022 17:22:49 -0700
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 by: John Larkin - Thu, 21 Jul 2022 00:22 UTC

On Wed, 20 Jul 2022 19:32:20 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>John Larkin wrote:
>>
>>
>> Suppose I have several rackmount boxes and each has a BNC connector on
>> the back. Each of them has an open-drain mosfet, a weak pullup, and a
>> lowpass filtered schmitt gate back into our FPGA.
>>
>> I can daisy-chain several boxes with BNC cables and tees.
>>
>> Each box has a 40 MHz VCXO and I want to phase-lock them, or at least
>> time-align them to always be the same within a few microseconds,
>> longterm.
>>
>> I could call one the leader (not "master") and make the others
>> followers (not "slaves") and have the leader make an active low pulse
>> maybe once a second. A follower would use her (not "his") clock to
>> measure the incoming period and tweak its local VCXO in the right
>> direction. That should work.
>>
>> Don't GPS receivers lock their 10 MHz oscillators to a 1 PPS pulse
>> from the satellites?
>>
>> My system should work from a 1 PPS GPS pulse too, all boxes as
>> followers.
>>
>> The PLL algorithm might be interesting.
>>
>
>It's certainly possible. However, within whatever tiny loop bandwidth
>you wound up with, the lockers would still have
>
>20 log(40e6) = 152 dB
>
>higher phase noise than the lockee.

GPS has that problem too.

>
>It would be interesting to do the math to see whether it's possible to
>generate a concensus lock for the group: if you get everybody close
>enough, just sum their sine wave outputs and lock each one of them to
>that, with some bit of AC coupling or something so that they don't all
>wander together off to the edge of the tuning range.
>
>Maybe have one doing the locking with a phase shifter and the others
>with VCOs, or something like that.
>
>Definitely a partly-baked idea, but surely one could do better than 152 dB!
>
>Cheers
>
>Phil Hobbs

Each box is basically a multichannel power supply, but channels can be
programmed to do stuff in timed sequences. I want different box
outputs to time align within, say, one millisecond longterm once
programs are kicked off together. So, many microseconds of equivalent
RMS phase noise is OK as long as we stay time aligned longterm.

If a follower is told to start locking, it could timestamp the first
incoming 1 PPS with a giant counter clocked by its local 40 MHz VCO.
If a later 1 PPS edge appears to arrive too soon, we could speed up
our VCXO by, say, 1 PPM, and vice versa. So longterm it walks into
alignment with the 1 PPS and eventually dithers a microsecond per
second. Noise on the coax gets fixed over time too.

That's better than just measuring the 1 Hz period once a second,
tweaking the clock, and then throwing away that measurement. I want a
time lock, not a frequency lock.

Re: really slow PLL

<8f21a4c4-bf22-2a5b-4355-ef5397fe86dc@electrooptical.net>

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https://www.novabbs.com/tech/article-flat.php?id=101858&group=sci.electronics.design#101858

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Subject: Re: really slow PLL
Newsgroups: sci.electronics.design
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 by: Phil Hobbs - Thu, 21 Jul 2022 00:28 UTC

John Larkin wrote:
> On Wed, 20 Jul 2022 19:32:20 -0400, Phil Hobbs
> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>
>> John Larkin wrote:
>>>
>>>
>>> Suppose I have several rackmount boxes and each has a BNC connector on
>>> the back. Each of them has an open-drain mosfet, a weak pullup, and a
>>> lowpass filtered schmitt gate back into our FPGA.
>>>
>>> I can daisy-chain several boxes with BNC cables and tees.
>>>
>>> Each box has a 40 MHz VCXO and I want to phase-lock them, or at least
>>> time-align them to always be the same within a few microseconds,
>>> longterm.
>>>
>>> I could call one the leader (not "master") and make the others
>>> followers (not "slaves") and have the leader make an active low pulse
>>> maybe once a second. A follower would use her (not "his") clock to
>>> measure the incoming period and tweak its local VCXO in the right
>>> direction. That should work.
>>>
>>> Don't GPS receivers lock their 10 MHz oscillators to a 1 PPS pulse
>>> from the satellites?
>>>
>>> My system should work from a 1 PPS GPS pulse too, all boxes as
>>> followers.
>>>
>>> The PLL algorithm might be interesting.
>>>
>>
>> It's certainly possible. However, within whatever tiny loop bandwidth
>> you wound up with, the lockers would still have
>>
>> 20 log(40e6) = 152 dB
>>
>> higher phase noise than the lockee.
>
> GPS has that problem too.
>
>>
>> It would be interesting to do the math to see whether it's possible to
>> generate a concensus lock for the group: if you get everybody close
>> enough, just sum their sine wave outputs and lock each one of them to
>> that, with some bit of AC coupling or something so that they don't all
>> wander together off to the edge of the tuning range.
>>
>> Maybe have one doing the locking with a phase shifter and the others
>> with VCOs, or something like that.
>>
>> Definitely a partly-baked idea, but surely one could do better than 152 dB!
>>
>> Cheers
>>
>> Phil Hobbs
>
> Each box is basically a multichannel power supply, but channels can be
> programmed to do stuff in timed sequences. I want different box
> outputs to time align within, say, one millisecond longterm once
> programs are kicked off together. So, many microseconds of equivalent
> RMS phase noise is OK as long as we stay time aligned longterm.
>
> If a follower is told to start locking, it could timestamp the first
> incoming 1 PPS with a giant counter clocked by its local 40 MHz VCO.
> If a later 1 PPS edge appears to arrive too soon, we could speed up
> our VCXO by, say, 1 PPM, and vice versa. So longterm it walks into
> alignment with the 1 PPS and eventually dithers a microsecond per
> second. Noise on the coax gets fixed over time too.
>
> That's better than just measuring the 1 Hz period once a second,
> tweaking the clock, and then throwing away that measurement. I want a
> time lock, not a frequency lock.
>

Absolutely. The scary 152 dB number doesn't mean that doing something
like that is automatically a bad idea.

Being an old RF and ultrastable laser guy, though, it does make my ears
perk up. ;)

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

Re: really slow PLL

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 by: bitrex - Thu, 21 Jul 2022 01:49 UTC

On 7/20/2022 8:22 PM, John Larkin wrote:
> On Wed, 20 Jul 2022 19:32:20 -0400, Phil Hobbs
> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>
>> John Larkin wrote:
>>>
>>>
>>> Suppose I have several rackmount boxes and each has a BNC connector on
>>> the back. Each of them has an open-drain mosfet, a weak pullup, and a
>>> lowpass filtered schmitt gate back into our FPGA.
>>>
>>> I can daisy-chain several boxes with BNC cables and tees.
>>>
>>> Each box has a 40 MHz VCXO and I want to phase-lock them, or at least
>>> time-align them to always be the same within a few microseconds,
>>> longterm.
>>>
>>> I could call one the leader (not "master") and make the others
>>> followers (not "slaves") and have the leader make an active low pulse
>>> maybe once a second. A follower would use her (not "his") clock to
>>> measure the incoming period and tweak its local VCXO in the right
>>> direction. That should work.
>>>
>>> Don't GPS receivers lock their 10 MHz oscillators to a 1 PPS pulse
>>> from the satellites?
>>>
>>> My system should work from a 1 PPS GPS pulse too, all boxes as
>>> followers.
>>>
>>> The PLL algorithm might be interesting.
>>>
>>
>> It's certainly possible. However, within whatever tiny loop bandwidth
>> you wound up with, the lockers would still have
>>
>> 20 log(40e6) = 152 dB
>>
>> higher phase noise than the lockee.
>
> GPS has that problem too.
>
>>
>> It would be interesting to do the math to see whether it's possible to
>> generate a concensus lock for the group: if you get everybody close
>> enough, just sum their sine wave outputs and lock each one of them to
>> that, with some bit of AC coupling or something so that they don't all
>> wander together off to the edge of the tuning range.
>>
>> Maybe have one doing the locking with a phase shifter and the others
>> with VCOs, or something like that.
>>
>> Definitely a partly-baked idea, but surely one could do better than 152 dB!
>>
>> Cheers
>>
>> Phil Hobbs
>
> Each box is basically a multichannel power supply, but channels can be
> programmed to do stuff in timed sequences. I want different box
> outputs to time align within, say, one millisecond longterm once
> programs are kicked off together. So, many microseconds of equivalent
> RMS phase noise is OK as long as we stay time aligned longterm.

It sounds like you're looking for a protocol like DMX if what you want
is to trigger sequences of events across boxes to within a millisecond,
I don't understand what this lock-the-40 MHz across boxes is about.

<https://en.wikipedia.org/wiki/DMX512>

Re: really slow PLL

<evdhdh9l1chbd0qh4et8cm2kt6hdmudufs@4ax.com>

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From: jlar...@highlandsniptechnology.com
Newsgroups: sci.electronics.design
Subject: Re: really slow PLL
Date: Wed, 20 Jul 2022 19:28:25 -0700
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 by: jlar...@highlandsniptechnology.com - Thu, 21 Jul 2022 02:28 UTC

On Wed, 20 Jul 2022 20:28:35 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>John Larkin wrote:
>> On Wed, 20 Jul 2022 19:32:20 -0400, Phil Hobbs
>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>
>>> John Larkin wrote:
>>>>
>>>>
>>>> Suppose I have several rackmount boxes and each has a BNC connector on
>>>> the back. Each of them has an open-drain mosfet, a weak pullup, and a
>>>> lowpass filtered schmitt gate back into our FPGA.
>>>>
>>>> I can daisy-chain several boxes with BNC cables and tees.
>>>>
>>>> Each box has a 40 MHz VCXO and I want to phase-lock them, or at least
>>>> time-align them to always be the same within a few microseconds,
>>>> longterm.
>>>>
>>>> I could call one the leader (not "master") and make the others
>>>> followers (not "slaves") and have the leader make an active low pulse
>>>> maybe once a second. A follower would use her (not "his") clock to
>>>> measure the incoming period and tweak its local VCXO in the right
>>>> direction. That should work.
>>>>
>>>> Don't GPS receivers lock their 10 MHz oscillators to a 1 PPS pulse
>>>> from the satellites?
>>>>
>>>> My system should work from a 1 PPS GPS pulse too, all boxes as
>>>> followers.
>>>>
>>>> The PLL algorithm might be interesting.
>>>>
>>>
>>> It's certainly possible. However, within whatever tiny loop bandwidth
>>> you wound up with, the lockers would still have
>>>
>>> 20 log(40e6) = 152 dB
>>>
>>> higher phase noise than the lockee.
>>
>> GPS has that problem too.
>>
>>>
>>> It would be interesting to do the math to see whether it's possible to
>>> generate a concensus lock for the group: if you get everybody close
>>> enough, just sum their sine wave outputs and lock each one of them to
>>> that, with some bit of AC coupling or something so that they don't all
>>> wander together off to the edge of the tuning range.
>>>
>>> Maybe have one doing the locking with a phase shifter and the others
>>> with VCOs, or something like that.
>>>
>>> Definitely a partly-baked idea, but surely one could do better than 152 dB!
>>>
>>> Cheers
>>>
>>> Phil Hobbs
>>
>> Each box is basically a multichannel power supply, but channels can be
>> programmed to do stuff in timed sequences. I want different box
>> outputs to time align within, say, one millisecond longterm once
>> programs are kicked off together. So, many microseconds of equivalent
>> RMS phase noise is OK as long as we stay time aligned longterm.
>>
>> If a follower is told to start locking, it could timestamp the first
>> incoming 1 PPS with a giant counter clocked by its local 40 MHz VCO.
>> If a later 1 PPS edge appears to arrive too soon, we could speed up
>> our VCXO by, say, 1 PPM, and vice versa. So longterm it walks into
>> alignment with the 1 PPS and eventually dithers a microsecond per
>> second. Noise on the coax gets fixed over time too.
>>
>> That's better than just measuring the 1 Hz period once a second,
>> tweaking the clock, and then throwing away that measurement. I want a
>> time lock, not a frequency lock.
>>
>
>Absolutely. The scary 152 dB number doesn't mean that doing something
>like that is automatically a bad idea.
>
>Being an old RF and ultrastable laser guy, though, it does make my ears
>perk up. ;)
>
>Cheers
>
>Phil Hobbs

I like thermostats, single-bit-feedback control loops.

We have a couple of boxes that do fan control based on interior
temperature. Once a second, if it's above the setpoint, ratchet fan
speed up some fixed amount, 1% maybe. If it's cooler than the
setpoint, step fan speed down. There's no acoustic drama and it's
perfectly stable.

It dithers around the setpoint but nobody notices.

This is immune to classic control theory so the concept annoys some
people but it works great.

Re: really slow PLL

<5fehdht2cbvi2kgek4qllj3ga8jofrkc7n@4ax.com>

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From: jlar...@highlandsniptechnology.com
Newsgroups: sci.electronics.design
Subject: Re: really slow PLL
Date: Wed, 20 Jul 2022 19:35:13 -0700
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 by: jlar...@highlandsniptechnology.com - Thu, 21 Jul 2022 02:35 UTC

On Wed, 20 Jul 2022 21:49:32 -0400, bitrex <user@example.net> wrote:

>On 7/20/2022 8:22 PM, John Larkin wrote:
>> On Wed, 20 Jul 2022 19:32:20 -0400, Phil Hobbs
>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>
>>> John Larkin wrote:
>>>>
>>>>
>>>> Suppose I have several rackmount boxes and each has a BNC connector on
>>>> the back. Each of them has an open-drain mosfet, a weak pullup, and a
>>>> lowpass filtered schmitt gate back into our FPGA.
>>>>
>>>> I can daisy-chain several boxes with BNC cables and tees.
>>>>
>>>> Each box has a 40 MHz VCXO and I want to phase-lock them, or at least
>>>> time-align them to always be the same within a few microseconds,
>>>> longterm.
>>>>
>>>> I could call one the leader (not "master") and make the others
>>>> followers (not "slaves") and have the leader make an active low pulse
>>>> maybe once a second. A follower would use her (not "his") clock to
>>>> measure the incoming period and tweak its local VCXO in the right
>>>> direction. That should work.
>>>>
>>>> Don't GPS receivers lock their 10 MHz oscillators to a 1 PPS pulse
>>>> from the satellites?
>>>>
>>>> My system should work from a 1 PPS GPS pulse too, all boxes as
>>>> followers.
>>>>
>>>> The PLL algorithm might be interesting.
>>>>
>>>
>>> It's certainly possible. However, within whatever tiny loop bandwidth
>>> you wound up with, the lockers would still have
>>>
>>> 20 log(40e6) = 152 dB
>>>
>>> higher phase noise than the lockee.
>>
>> GPS has that problem too.
>>
>>>
>>> It would be interesting to do the math to see whether it's possible to
>>> generate a concensus lock for the group: if you get everybody close
>>> enough, just sum their sine wave outputs and lock each one of them to
>>> that, with some bit of AC coupling or something so that they don't all
>>> wander together off to the edge of the tuning range.
>>>
>>> Maybe have one doing the locking with a phase shifter and the others
>>> with VCOs, or something like that.
>>>
>>> Definitely a partly-baked idea, but surely one could do better than 152 dB!
>>>
>>> Cheers
>>>
>>> Phil Hobbs
>>
>> Each box is basically a multichannel power supply, but channels can be
>> programmed to do stuff in timed sequences. I want different box
>> outputs to time align within, say, one millisecond longterm once
>> programs are kicked off together. So, many microseconds of equivalent
>> RMS phase noise is OK as long as we stay time aligned longterm.
>
>It sounds like you're looking for a protocol like DMX if what you want
>is to trigger sequences of events across boxes to within a millisecond,
>I don't understand what this lock-the-40 MHz across boxes is about.
>
><https://en.wikipedia.org/wiki/DMX512>
>
>

Each box runs a bunch of timed processes. If they are triggered to
start together, I don't want their timings to drift apart. Locking
their clocks works.

My loop will also lock my boxes to a 1 PPS GPS source, so we can
synchronize within a bigger system.

It's easy to explain 1 PPS pulses on BNC connectors.

Re: really slow PLL

<tbaoic$260q5$1@dont-email.me>

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From: pNaonStp...@yahoo.com (Jan Panteltje)
Newsgroups: sci.electronics.design
Subject: Re: really slow PLL
Date: Thu, 21 Jul 2022 05:24:55 GMT
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 by: Jan Panteltje - Thu, 21 Jul 2022 05:24 UTC

On a sunny day (Wed, 20 Jul 2022 16:20:57 -0700) it happened John Larkin
<jlarkin@highland_atwork_technology.com> wrote in
<qd2hdhhs6bnndjs4likrvlq9jt6q5deebo@4ax.com>:

>
>
>Suppose I have several rackmount boxes and each has a BNC connector on
>the back. Each of them has an open-drain mosfet, a weak pullup, and a
>lowpass filtered schmitt gate back into our FPGA.
>
>I can daisy-chain several boxes with BNC cables and tees.
>
>Each box has a 40 MHz VCXO and I want to phase-lock them, or at least
>time-align them to always be the same within a few microseconds,
>longterm.
>
>I could call one the leader (not "master") and make the others
>followers (not "slaves") and have the leader make an active low pulse
>maybe once a second. A follower would use her (not "his") clock to
>measure the incoming period and tweak its local VCXO in the right
>direction. That should work.
>
>Don't GPS receivers lock their 10 MHz oscillators to a 1 PPS pulse
>from the satellites?
>
>My system should work from a 1 PPS GPS pulse too, all boxes as
>followers.
>
>The PLL algorithm might be interesting.

So why not use a RGB 24 bit 0xffffff master clock board that drives all slave modules
those then need no local oscillator.
For event 'sync' sent a DC step every now and then on the same
coax and filter it out at the slave sides, to make the slaves jump to action.

Re: really slow PLL

<tbap1m$h0d7$1@solani.org>

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From: dk4...@arcor.de (Gerhard Hoffmann)
Newsgroups: sci.electronics.design
Subject: Re: really slow PLL
Date: Thu, 21 Jul 2022 07:43:18 +0200
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 by: Gerhard Hoffmann - Thu, 21 Jul 2022 05:43 UTC

Am 21.07.22 um 01:20 schrieb John Larkin:
>
>
> Suppose I have several rackmount boxes and each has a BNC connector on
> the back. Each of them has an open-drain mosfet, a weak pullup, and a
> lowpass filtered schmitt gate back into our FPGA.
>
> I can daisy-chain several boxes with BNC cables and tees.
>
> Each box has a 40 MHz VCXO and I want to phase-lock them, or at least
> time-align them to always be the same within a few microseconds,
> longterm.

I have a backburner project of locking 16 MTI-260 oscillators
slooowy to another one, and when they are in sync, combine
them with an array of Wilkinsons. That should have a nice
effect on phase noise by averaging over 16.
The CPLD has enough resources to implement that as a delay
locked loop with 1 pps, but low hanging fruit first.

>
> I could call one the leader (not "master") and make the others
> followers (not "slaves") and have the leader make an active low pulse
> maybe once a second. A follower would use her (not "his") clock to
> measure the incoming period and tweak its local VCXO in the right
> direction. That should work.
>
> Don't GPS receivers lock their 10 MHz oscillators to a 1 PPS pulse
> from the satellites?

No. There is no 1PPS pulse from the sat nor the need for exactly 10 MHz.
The sats transmit a pseudo noise sequence that is
aligned to the second of their local clock source.
The GPS receiver knows the polynomial and runs a local copy of
the polynomial. It knows by cross correlation if the local
pseudo noise is the same as that of the sat and therefore knows
the start of the second. Usually that won't be the case.
Then the receiver delays its own polynomial by omitting a
clock to the shift register that generates it and tries again.
Sooner or later it will fit.

One needs at least reception of 4 sats to get a set of (x, y, z,
t) that fits together, usually more. Once one has a lock to
one sat, it is possible to get the data of the current
constellation of all sats. That helps to speed up the lock
to the others by providing a guess of a better starting point
for the search.

There is still a long way from synced polynomials to a good fix,
for example removal of the Faraday effect by comparing the
flight time difference for sats on different frequency bands.

95% of a GPS receiver is software. The 1PPS out of a typical
GPS receiver used to be only a port bit of the CPU, synchronous
to the second only in the very long run.

If the receiver delivers a nice 10 MHz, the CPU has better
information to adjust it.

Gerhard

Re: really slow PLL

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Subject: Re: really slow PLL
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 by: whit3rd - Thu, 21 Jul 2022 06:49 UTC

On Wednesday, July 20, 2022 at 4:21:08 PM UTC-7, John Larkin wrote:
> Suppose I have several rackmount boxes and each has a BNC connector on
> the back. Each of them has an open-drain mosfet, a weak pullup, and a
> lowpass filtered schmitt gate back into our FPGA.
>
> I can daisy-chain several boxes with BNC cables and tees.
>
> Each box has a 40 MHz VCXO and I want to phase-lock them, or at least
> time-align them to always be the same within a few microseconds,
> longterm.

If you can tolerate 'a few microseconds' on a 40 MHz signal, that's not a phase-lock
problem, it's a frequency-lock problem. Why not just run an up/down counter
to generate a correction voltage for each non-leading VCO?

Re: really slow PLL

<f415cd82-40ba-412c-9226-b0bdf2385e7bn@googlegroups.com>

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Subject: Re: really slow PLL
From: jrwalli...@gmail.com (John Walliker)
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 by: John Walliker - Thu, 21 Jul 2022 08:33 UTC

On Thursday, 21 July 2022 at 07:49:43 UTC+1, whit3rd wrote:
> On Wednesday, July 20, 2022 at 4:21:08 PM UTC-7, John Larkin wrote:
> > Suppose I have several rackmount boxes and each has a BNC connector on
> > the back. Each of them has an open-drain mosfet, a weak pullup, and a
> > lowpass filtered schmitt gate back into our FPGA.
> >
> > I can daisy-chain several boxes with BNC cables and tees.
> >
> > Each box has a 40 MHz VCXO and I want to phase-lock them, or at least
> > time-align them to always be the same within a few microseconds,
> > longterm.
> If you can tolerate 'a few microseconds' on a 40 MHz signal, that's not a phase-lock
> problem, it's a frequency-lock problem. Why not just run an up/down counter
> to generate a correction voltage for each non-leading VCO?

If you have an ethernet interface to each unit then Precision Time Protocol
should do exactly what you want.
https://en.wikipedia.org/wiki/Precision_Time_Protocol
John

Re: really slow PLL

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From: '''newsp...@nonad.co.uk (Martin Brown)
Newsgroups: sci.electronics.design
Subject: Re: really slow PLL
Date: Thu, 21 Jul 2022 12:06:26 +0100
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 by: Martin Brown - Thu, 21 Jul 2022 11:06 UTC

On 21/07/2022 01:22, John Larkin wrote:
> On Wed, 20 Jul 2022 19:32:20 -0400, Phil Hobbs
> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>
>> John Larkin wrote:
>>>
>>>
>>> Suppose I have several rackmount boxes and each has a BNC connector on
>>> the back. Each of them has an open-drain mosfet, a weak pullup, and a
>>> lowpass filtered schmitt gate back into our FPGA.
>>>
>>> I can daisy-chain several boxes with BNC cables and tees.
>>>
>>> Each box has a 40 MHz VCXO and I want to phase-lock them, or at least
>>> time-align them to always be the same within a few microseconds,
>>> longterm.
>>>
>>> I could call one the leader (not "master") and make the others
>>> followers (not "slaves") and have the leader make an active low pulse
>>> maybe once a second. A follower would use her (not "his") clock to
>>> measure the incoming period and tweak its local VCXO in the right
>>> direction. That should work.
>>>
>>> Don't GPS receivers lock their 10 MHz oscillators to a 1 PPS pulse
>>> from the satellites?
>>>
>>> My system should work from a 1 PPS GPS pulse too, all boxes as
>>> followers.
>>>
>>> The PLL algorithm might be interesting.
>>>
>>
>> It's certainly possible. However, within whatever tiny loop bandwidth
>> you wound up with, the lockers would still have
>>
>> 20 log(40e6) = 152 dB
>>
>> higher phase noise than the lockee.
>
> GPS has that problem too.
>
>>
>> It would be interesting to do the math to see whether it's possible to
>> generate a concensus lock for the group: if you get everybody close
>> enough, just sum their sine wave outputs and lock each one of them to
>> that, with some bit of AC coupling or something so that they don't all
>> wander together off to the edge of the tuning range.
>>
>> Maybe have one doing the locking with a phase shifter and the others
>> with VCOs, or something like that.
>>
>> Definitely a partly-baked idea, but surely one could do better than 152 dB!
>>
>> Cheers
>>
>> Phil Hobbs
>
> Each box is basically a multichannel power supply, but channels can be
> programmed to do stuff in timed sequences. I want different box
> outputs to time align within, say, one millisecond longterm once
> programs are kicked off together. So, many microseconds of equivalent
> RMS phase noise is OK as long as we stay time aligned longterm.

You really need to define longterm before the problem becomes well
posed. Do you mean hours, days, weeks or months of runtime?

> If a follower is told to start locking, it could timestamp the first
> incoming 1 PPS with a giant counter clocked by its local 40 MHz VCO.
> If a later 1 PPS edge appears to arrive too soon, we could speed up
> our VCXO by, say, 1 PPM, and vice versa. So longterm it walks into
> alignment with the 1 PPS and eventually dithers a microsecond per
> second. Noise on the coax gets fixed over time too.

Have a free running counter on each of the followers and use the value
of that after 1s, 10s, 100s to determine the correct tweak to apply
locally. Tweaks of 1ppm at a time is rather crude you should be able to
determine the right amount to tweak it by better than that.
(especially over longer timebases)

> That's better than just measuring the 1 Hz period once a second,
> tweaking the clock, and then throwing away that measurement. I want a
> time lock, not a frequency lock.

Then you probably want to measure the cumulative error over many
seconds. Each unit can work out how long it can free run without
exceeding tolerance once it has the rough and ready count from the first
second. After that you have a good idea of how many seconds you can free
run for without having any ambiguities from residual drift.

This is an ancient trick from physics which avoids the smartest students
from having to laboriously count every pendulum swing when determining g
to maximum possible precision in a given time. It used to be (and
probably still is a favourite exam practical). Components needed are
very cheap and the whole thing is a good test of experimental technique.

--
Regards,
Martin Brown

Re: really slow PLL

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From: jlar...@highlandsniptechnology.com
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Subject: Re: really slow PLL
Date: Thu, 21 Jul 2022 04:17:14 -0700
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 by: jlar...@highlandsniptechnology.com - Thu, 21 Jul 2022 11:17 UTC

On Wed, 20 Jul 2022 23:49:40 -0700 (PDT), whit3rd <whit3rd@gmail.com>
wrote:

>On Wednesday, July 20, 2022 at 4:21:08 PM UTC-7, John Larkin wrote:
>> Suppose I have several rackmount boxes and each has a BNC connector on
>> the back. Each of them has an open-drain mosfet, a weak pullup, and a
>> lowpass filtered schmitt gate back into our FPGA.
>>
>> I can daisy-chain several boxes with BNC cables and tees.
>>
>> Each box has a 40 MHz VCXO and I want to phase-lock them, or at least
>> time-align them to always be the same within a few microseconds,
>> longterm.
>
>If you can tolerate 'a few microseconds' on a 40 MHz signal, that's not a phase-lock
>problem, it's a frequency-lock problem. Why not just run an up/down counter
>to generate a correction voltage for each non-leading VCO?

It's actually a time lock problem. If a follower box starts up and
sees its first 1 PPS input, it can thereafter declare 1 PPS internal
events, based on its local VCO, and then do successive early/late
comparisons to the external pulses. And trim its VCXO accordingly.

Re: really slow PLL

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Subject: Re: really slow PLL
Date: Thu, 21 Jul 2022 04:19:14 -0700
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 by: jlar...@highlandsniptechnology.com - Thu, 21 Jul 2022 11:19 UTC

On Thu, 21 Jul 2022 07:43:18 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
wrote:

>Am 21.07.22 um 01:20 schrieb John Larkin:
>>
>>
>> Suppose I have several rackmount boxes and each has a BNC connector on
>> the back. Each of them has an open-drain mosfet, a weak pullup, and a
>> lowpass filtered schmitt gate back into our FPGA.
>>
>> I can daisy-chain several boxes with BNC cables and tees.
>>
>> Each box has a 40 MHz VCXO and I want to phase-lock them, or at least
>> time-align them to always be the same within a few microseconds,
>> longterm.
>
>I have a backburner project of locking 16 MTI-260 oscillators
>slooowy to another one, and when they are in sync, combine
>them with an array of Wilkinsons. That should have a nice
>effect on phase noise by averaging over 16.
>The CPLD has enough resources to implement that as a delay
>locked loop with 1 pps, but low hanging fruit first.
>
>>
>> I could call one the leader (not "master") and make the others
>> followers (not "slaves") and have the leader make an active low pulse
>> maybe once a second. A follower would use her (not "his") clock to
>> measure the incoming period and tweak its local VCXO in the right
>> direction. That should work.
>>
>> Don't GPS receivers lock their 10 MHz oscillators to a 1 PPS pulse
>> from the satellites?
>
>No. There is no 1PPS pulse from the sat nor the need for exactly 10 MHz.
>The sats transmit a pseudo noise sequence that is
>aligned to the second of their local clock source.
>The GPS receiver knows the polynomial and runs a local copy of
>the polynomial. It knows by cross correlation if the local
>pseudo noise is the same as that of the sat and therefore knows
>the start of the second. Usually that won't be the case.
>Then the receiver delays its own polynomial by omitting a
>clock to the shift register that generates it and tries again.
>Sooner or later it will fit.

Where does the 10 MHz come from?

Re: really slow PLL

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From: cli...@nowaytoday.co.uk (Clive Arthur)
Newsgroups: sci.electronics.design
Subject: Re: really slow PLL
Date: Thu, 21 Jul 2022 12:29:10 +0100
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 by: Clive Arthur - Thu, 21 Jul 2022 11:29 UTC

On 21/07/2022 00:20, John Larkin wrote:
>
>
> Suppose I have several rackmount boxes and each has a BNC connector on
> the back. Each of them has an open-drain mosfet, a weak pullup, and a
> lowpass filtered schmitt gate back into our FPGA.
>
> I can daisy-chain several boxes with BNC cables and tees.
>
> Each box has a 40 MHz VCXO and I want to phase-lock them, or at least
> time-align them to always be the same within a few microseconds,
> longterm.
>
> I could call one the leader (not "master") and make the others
> followers (not "slaves") and have the leader make an active low pulse
> maybe once a second. A follower would use her (not "his") clock to
> measure the incoming period and tweak its local VCXO in the right
> direction. That should work.
>
> Don't GPS receivers lock their 10 MHz oscillators to a 1 PPS pulse
> from the satellites?
>
> My system should work from a 1 PPS GPS pulse too, all boxes as
> followers.
>
> The PLL algorithm might be interesting.

Each box has a 40.0something MHz oscillator. Some simple logic triggers
on the 1 second GPS pulse and allows 40 million of these clocks through
to the rest of the circuit, then waits for the next pulse, rinse and repeat.

Of course, this will only work in circumstances where it's ok to stop
for a few cycles every second.

--
Cheers
Clive

Re: really slow PLL

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Subject: Re: really slow PLL
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 by: jlar...@highlandsniptechnology.com - Thu, 21 Jul 2022 11:42 UTC

On Thu, 21 Jul 2022 12:06:26 +0100, Martin Brown
<'''newspam'''@nonad.co.uk> wrote:

>On 21/07/2022 01:22, John Larkin wrote:
>> On Wed, 20 Jul 2022 19:32:20 -0400, Phil Hobbs
>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>
>>> John Larkin wrote:
>>>>
>>>>
>>>> Suppose I have several rackmount boxes and each has a BNC connector on
>>>> the back. Each of them has an open-drain mosfet, a weak pullup, and a
>>>> lowpass filtered schmitt gate back into our FPGA.
>>>>
>>>> I can daisy-chain several boxes with BNC cables and tees.
>>>>
>>>> Each box has a 40 MHz VCXO and I want to phase-lock them, or at least
>>>> time-align them to always be the same within a few microseconds,
>>>> longterm.
>>>>
>>>> I could call one the leader (not "master") and make the others
>>>> followers (not "slaves") and have the leader make an active low pulse
>>>> maybe once a second. A follower would use her (not "his") clock to
>>>> measure the incoming period and tweak its local VCXO in the right
>>>> direction. That should work.
>>>>
>>>> Don't GPS receivers lock their 10 MHz oscillators to a 1 PPS pulse
>>>> from the satellites?
>>>>
>>>> My system should work from a 1 PPS GPS pulse too, all boxes as
>>>> followers.
>>>>
>>>> The PLL algorithm might be interesting.
>>>>
>>>
>>> It's certainly possible. However, within whatever tiny loop bandwidth
>>> you wound up with, the lockers would still have
>>>
>>> 20 log(40e6) = 152 dB
>>>
>>> higher phase noise than the lockee.
>>
>> GPS has that problem too.
>>
>>>
>>> It would be interesting to do the math to see whether it's possible to
>>> generate a concensus lock for the group: if you get everybody close
>>> enough, just sum their sine wave outputs and lock each one of them to
>>> that, with some bit of AC coupling or something so that they don't all
>>> wander together off to the edge of the tuning range.
>>>
>>> Maybe have one doing the locking with a phase shifter and the others
>>> with VCOs, or something like that.
>>>
>>> Definitely a partly-baked idea, but surely one could do better than 152 dB!
>>>
>>> Cheers
>>>
>>> Phil Hobbs
>>
>> Each box is basically a multichannel power supply, but channels can be
>> programmed to do stuff in timed sequences. I want different box
>> outputs to time align within, say, one millisecond longterm once
>> programs are kicked off together. So, many microseconds of equivalent
>> RMS phase noise is OK as long as we stay time aligned longterm.
>
>You really need to define longterm before the problem becomes well
>posed. Do you mean hours, days, weeks or months of runtime?
>
>> If a follower is told to start locking, it could timestamp the first
>> incoming 1 PPS with a giant counter clocked by its local 40 MHz VCO.
>> If a later 1 PPS edge appears to arrive too soon, we could speed up
>> our VCXO by, say, 1 PPM, and vice versa. So longterm it walks into
>> alignment with the 1 PPS and eventually dithers a microsecond per
>> second. Noise on the coax gets fixed over time too.
>
>Have a free running counter on each of the followers and use the value
>of that after 1s, 10s, 100s to determine the correct tweak to apply
>locally. Tweaks of 1ppm at a time is rather crude you should be able to
>determine the right amount to tweak it by better than that.
>(especially over longer timebases)

I wouldn't expect my VCXO to be more than 10 PPM off at the start of
the lock request. So I can walk it to within 1 PPM, namely 1
microsecond error, in at most 10 seconds using 1 PPM jogs. If the osc
were 50 PPM off, it would take 50 seconds to catch up to the external
pulse.

>
>> That's better than just measuring the 1 Hz period once a second,
>> tweaking the clock, and then throwing away that measurement. I want a
>> time lock, not a frequency lock.
>
>Then you probably want to measure the cumulative error over many
>seconds. Each unit can work out how long it can free run without
>exceeding tolerance once it has the rough and ready count from the first
>second. After that you have a good idea of how many seconds you can free
>run for without having any ambiguities from residual drift.

Yes, I don't want to measure period once a second. I want to compare
time alignment forever after receiving the first 1 pps pulse.

It's actually simple: first received pulse, start a mod 40 million
counter. Every time it rolls over, do an early/late compare to the 1
PPS input, and jog the 40 MHz VCXO 1 PPM in the right direction.

The compare is a dflop, d is the msb of the counter, clock is the 1
PPS input. Occasional metastability is fine; it indicates success.

It doesn't even need to be a 40 million counter. Something a fraction
of that will do. 10,000 maybe.

Maybe the counter can just free-run, never get initialized. Gotta do
the math on that after I wake up.

Re: really slow PLL

<tbbi6s$ghm7$1@solani.org>

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From: dk4...@arcor.de (Gerhard Hoffmann)
Newsgroups: sci.electronics.design
Subject: Re: really slow PLL
Date: Thu, 21 Jul 2022 14:52:44 +0200
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 by: Gerhard Hoffmann - Thu, 21 Jul 2022 12:52 UTC

Am 21.07.22 um 13:19 schrieb jlarkin@highlandsniptechnology.com:

>
> Where does the 10 MHz come from?

Choise of implementer. One local clock generator is needed.
This clock determines short term stabiity and phase noise.

My Lucent KS24361 uses 5 MHz MTI-260 double ovens; for
redundancy/holdover it has a 2nd unit with another crystal
oven without a receiver.

The redundancy units were really hard to sell without the
receiver; that's why I have 20 of these MTI-260, got a good
price. :-)

They were new old stock built by HP/Agilent for Lucent as
replacement parts. They have never been on a telecom tower
in China like most of those one gets on ebay.

I have expanded the Lucent to 10 MHZ and with a distribution
amplifier:

< http://www.hoffmann-hochfrequenz.de/downloads/DoubDist.pdf >

cheers, Gerhard

Re: really slow PLL

<2c736f29-6de2-32e7-d389-4b4c48b8600f@electrooptical.net>

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Subject: Re: really slow PLL
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From: pcdhSpam...@electrooptical.net (Phil Hobbs)
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 by: Phil Hobbs - Thu, 21 Jul 2022 13:27 UTC

jlarkin@highlandsniptechnology.com wrote:
> On Wed, 20 Jul 2022 20:28:35 -0400, Phil Hobbs
> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>
>> John Larkin wrote:
>>> On Wed, 20 Jul 2022 19:32:20 -0400, Phil Hobbs
>>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>>
>>>> John Larkin wrote:
>>>>>
>>>>>
>>>>> Suppose I have several rackmount boxes and each has a BNC connector on
>>>>> the back. Each of them has an open-drain mosfet, a weak pullup, and a
>>>>> lowpass filtered schmitt gate back into our FPGA.
>>>>>
>>>>> I can daisy-chain several boxes with BNC cables and tees.
>>>>>
>>>>> Each box has a 40 MHz VCXO and I want to phase-lock them, or at least
>>>>> time-align them to always be the same within a few microseconds,
>>>>> longterm.
>>>>>
>>>>> I could call one the leader (not "master") and make the others
>>>>> followers (not "slaves") and have the leader make an active low pulse
>>>>> maybe once a second. A follower would use her (not "his") clock to
>>>>> measure the incoming period and tweak its local VCXO in the right
>>>>> direction. That should work.
>>>>>
>>>>> Don't GPS receivers lock their 10 MHz oscillators to a 1 PPS pulse
>>>>> from the satellites?
>>>>>
>>>>> My system should work from a 1 PPS GPS pulse too, all boxes as
>>>>> followers.
>>>>>
>>>>> The PLL algorithm might be interesting.
>>>>>
>>>>
>>>> It's certainly possible. However, within whatever tiny loop bandwidth
>>>> you wound up with, the lockers would still have
>>>>
>>>> 20 log(40e6) = 152 dB
>>>>
>>>> higher phase noise than the lockee.
>>>
>>> GPS has that problem too.
>>>
>>>>
>>>> It would be interesting to do the math to see whether it's possible to
>>>> generate a concensus lock for the group: if you get everybody close
>>>> enough, just sum their sine wave outputs and lock each one of them to
>>>> that, with some bit of AC coupling or something so that they don't all
>>>> wander together off to the edge of the tuning range.
>>>>
>>>> Maybe have one doing the locking with a phase shifter and the others
>>>> with VCOs, or something like that.
>>>>
>>>> Definitely a partly-baked idea, but surely one could do better than 152 dB!
>>>>
>>>> Cheers
>>>>
>>>> Phil Hobbs
>>>
>>> Each box is basically a multichannel power supply, but channels can be
>>> programmed to do stuff in timed sequences. I want different box
>>> outputs to time align within, say, one millisecond longterm once
>>> programs are kicked off together. So, many microseconds of equivalent
>>> RMS phase noise is OK as long as we stay time aligned longterm.
>>>
>>> If a follower is told to start locking, it could timestamp the first
>>> incoming 1 PPS with a giant counter clocked by its local 40 MHz VCO.
>>> If a later 1 PPS edge appears to arrive too soon, we could speed up
>>> our VCXO by, say, 1 PPM, and vice versa. So longterm it walks into
>>> alignment with the 1 PPS and eventually dithers a microsecond per
>>> second. Noise on the coax gets fixed over time too.
>>>
>>> That's better than just measuring the 1 Hz period once a second,
>>> tweaking the clock, and then throwing away that measurement. I want a
>>> time lock, not a frequency lock.
>>>
>>
>> Absolutely. The scary 152 dB number doesn't mean that doing something
>> like that is automatically a bad idea.
>>
>> Being an old RF and ultrastable laser guy, though, it does make my ears
>> perk up. ;)
>>
>> Cheers
>>
>> Phil Hobbs
>
> I like thermostats, single-bit-feedback control loops.
>
> We have a couple of boxes that do fan control based on interior
> temperature. Once a second, if it's above the setpoint, ratchet fan
> speed up some fixed amount, 1% maybe. If it's cooler than the
> setpoint, step fan speed down. There's no acoustic drama and it's
> perfectly stable.
>
> It dithers around the setpoint but nobody notices.
>
> This is immune to classic control theory so the concept annoys some
> people but it works great.

A real old time control guy like Tim Wescott would probably be a fan
too--the great virtue of a bang-bang controller is that (as you say)
it's highly resistant to variations in the _plant_.

Your furnace doesn't go nuts when you have a Christmas party, even
though all those people generate a lot of heat, and there's lots of
opening and closing of doors and ovens.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

Re: really slow PLL

<4bfb5c5a-33d0-e8e5-8b54-06503aeb8734@electrooptical.net>

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Subject: Re: really slow PLL
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 by: Phil Hobbs - Thu, 21 Jul 2022 13:36 UTC

Martin Brown wrote:
> On 21/07/2022 01:22, John Larkin wrote:
>> On Wed, 20 Jul 2022 19:32:20 -0400, Phil Hobbs
>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>
>>> John Larkin wrote:
>>>>
>>>>
>>>> Suppose I have several rackmount boxes and each has a BNC connector on
>>>> the back. Each of them has an open-drain mosfet, a weak pullup, and a
>>>> lowpass filtered schmitt gate back into our FPGA.
>>>>
>>>> I can daisy-chain several boxes with BNC cables and tees.
>>>>
>>>> Each box has a 40 MHz VCXO and I want to phase-lock them, or at least
>>>> time-align them to always be the same within a few microseconds,
>>>> longterm.
>>>>
>>>> I could call one the leader (not "master") and make the others
>>>> followers (not "slaves") and have the leader make an active low pulse
>>>> maybe once a second. A follower would use her (not "his") clock to
>>>> measure the incoming period and tweak its local VCXO in the right
>>>> direction. That should work.
>>>>
>>>> Don't GPS receivers lock their 10 MHz oscillators to a 1 PPS pulse
>>>> from the satellites?
>>>>
>>>> My system should work from a 1 PPS GPS pulse too, all boxes as
>>>> followers.
>>>>
>>>> The PLL algorithm might be interesting.
>>>>
>>>
>>> It's certainly possible.  However, within whatever tiny loop bandwidth
>>> you wound up with, the lockers would still have
>>>
>>> 20 log(40e6) = 152 dB
>>>
>>> higher phase noise than the lockee.
>>
>> GPS has that problem too.
>>
>>>
>>> It would be interesting to do the math to see whether it's possible to
>>> generate a concensus lock for the group: if you get everybody close
>>> enough, just sum their sine wave outputs and lock each one of them to
>>> that, with some bit of AC coupling or something so that they don't all
>>> wander together off to the edge of the tuning range.
>>>
>>> Maybe have one doing the locking with a phase shifter and the others
>>> with VCOs, or something like that.
>>>
>>> Definitely a partly-baked idea, but surely one could do better than
>>> 152 dB!
>>>
>>> Cheers
>>>
>>> Phil Hobbs
>>
>> Each box is basically a multichannel power supply, but channels can be
>> programmed to do stuff in timed sequences. I want different box
>> outputs to time align within, say, one millisecond longterm once
>> programs are kicked off together. So, many microseconds of equivalent
>> RMS phase noise is OK as long as we stay time aligned longterm.
>
> You really need to define longterm before the problem becomes well
> posed. Do you mean hours, days, weeks or months of runtime?
>
>> If a follower is told to start locking, it could timestamp the first
>> incoming 1 PPS with a giant counter clocked by its local 40 MHz VCO.
>> If a later 1 PPS edge appears to arrive too soon, we could speed up
>> our VCXO by, say, 1 PPM, and vice versa. So longterm it walks into
>> alignment with the 1 PPS and eventually dithers a microsecond per
>> second. Noise on the coax gets fixed over time too.
>
> Have a free running counter on each of the followers and use the value
> of that after 1s, 10s, 100s to determine the correct tweak to apply
> locally. Tweaks of 1ppm at a time is rather crude you should be able to
> determine the right amount to tweak it by better than that.
> (especially over longer timebases)
>
>> That's better than just measuring the 1 Hz period once a second,
>> tweaking the clock, and then throwing away that measurement. I want a
>> time lock, not a frequency lock.
>
> Then you probably want to measure the cumulative error over many
> seconds. Each unit can work out how long it can free run without
> exceeding tolerance once it has the rough and ready count from the first
> second. After that you have a good idea of how many seconds you can free
> run for without having any ambiguities from residual drift.
>
> This is an ancient trick from physics which avoids the smartest students
> from having to laboriously count every pendulum swing when determining g
> to maximum possible precision in a given time. It used to be (and
> probably still is a favourite exam practical). Components needed are
> very cheap and the whole thing is a good test of experimental technique.
>

It's not as efficient as 'dry labbing'. ;)

The tradeoffs are sort of different when you have a $3 CPLD watching
things rather than a student.

Cheers

Phil Hobbs
(who didn't work that cheap even back when he was a student)

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

Re: really slow PLL

<T1dCK.48233$vd2.40244@fx39.iad>

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 by: bitrex - Thu, 21 Jul 2022 14:04 UTC

On 7/21/2022 7:06 AM, Martin Brown wrote:
> On 21/07/2022 01:22, John Larkin wrote:
>> On Wed, 20 Jul 2022 19:32:20 -0400, Phil Hobbs
>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>
>>> John Larkin wrote:
>>>>
>>>>
>>>> Suppose I have several rackmount boxes and each has a BNC connector on
>>>> the back. Each of them has an open-drain mosfet, a weak pullup, and a
>>>> lowpass filtered schmitt gate back into our FPGA.
>>>>
>>>> I can daisy-chain several boxes with BNC cables and tees.
>>>>
>>>> Each box has a 40 MHz VCXO and I want to phase-lock them, or at least
>>>> time-align them to always be the same within a few microseconds,
>>>> longterm.
>>>>
>>>> I could call one the leader (not "master") and make the others
>>>> followers (not "slaves") and have the leader make an active low pulse
>>>> maybe once a second. A follower would use her (not "his") clock to
>>>> measure the incoming period and tweak its local VCXO in the right
>>>> direction. That should work.
>>>>
>>>> Don't GPS receivers lock their 10 MHz oscillators to a 1 PPS pulse
>>>> from the satellites?
>>>>
>>>> My system should work from a 1 PPS GPS pulse too, all boxes as
>>>> followers.
>>>>
>>>> The PLL algorithm might be interesting.
>>>>
>>>
>>> It's certainly possible.  However, within whatever tiny loop bandwidth
>>> you wound up with, the lockers would still have
>>>
>>> 20 log(40e6) = 152 dB
>>>
>>> higher phase noise than the lockee.
>>
>> GPS has that problem too.
>>
>>>
>>> It would be interesting to do the math to see whether it's possible to
>>> generate a concensus lock for the group: if you get everybody close
>>> enough, just sum their sine wave outputs and lock each one of them to
>>> that, with some bit of AC coupling or something so that they don't all
>>> wander together off to the edge of the tuning range.
>>>
>>> Maybe have one doing the locking with a phase shifter and the others
>>> with VCOs, or something like that.
>>>
>>> Definitely a partly-baked idea, but surely one could do better than
>>> 152 dB!
>>>
>>> Cheers
>>>
>>> Phil Hobbs
>>
>> Each box is basically a multichannel power supply, but channels can be
>> programmed to do stuff in timed sequences. I want different box
>> outputs to time align within, say, one millisecond longterm once
>> programs are kicked off together. So, many microseconds of equivalent
>> RMS phase noise is OK as long as we stay time aligned longterm.
>
> You really need to define longterm before the problem becomes well
> posed. Do you mean hours, days, weeks or months of runtime?

Yeah I don't quite get it, either. My rack of synthesizers can each play
one voice of the Maple Leaf Rag via MIDI and they all stay synced
together really well, at least over a timespan of several
minutes...superficially at least it sounds like he wants a sequencer.

Using the nuts & bolts system clock for synchronization of "user tasks"
also makes me uncomfortable, if the device behavior only need to align
to the millisecond why not trigger them using some simple network
protocol and let their hardware figure out how long a millisecond is
independently. Do the timings of these boxes need to be tighter than the
Maple Leaf Rag?

Re: really slow PLL

<H9dCK.589973$5fVf.18746@fx09.iad>

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 by: bitrex - Thu, 21 Jul 2022 14:12 UTC

On 7/21/2022 4:33 AM, John Walliker wrote:
> On Thursday, 21 July 2022 at 07:49:43 UTC+1, whit3rd wrote:
>> On Wednesday, July 20, 2022 at 4:21:08 PM UTC-7, John Larkin wrote:
>>> Suppose I have several rackmount boxes and each has a BNC connector on
>>> the back. Each of them has an open-drain mosfet, a weak pullup, and a
>>> lowpass filtered schmitt gate back into our FPGA.
>>>
>>> I can daisy-chain several boxes with BNC cables and tees.
>>>
>>> Each box has a 40 MHz VCXO and I want to phase-lock them, or at least
>>> time-align them to always be the same within a few microseconds,
>>> longterm.
>> If you can tolerate 'a few microseconds' on a 40 MHz signal, that's not a phase-lock
>> problem, it's a frequency-lock problem. Why not just run an up/down counter
>> to generate a correction voltage for each non-leading VCO?
>
> If you have an ethernet interface to each unit then Precision Time Protocol
> should do exactly what you want.
> https://en.wikipedia.org/wiki/Precision_Time_Protocol
> John

Yeah, that sounds like the ticket to me also. Trying to use each box's
system clock for purposes of keeping "user-space" tasks in sync across
boxes makes me uncomfortable, sounds like a srs hack.

If you need to tightly synchronize events between physically separate
hardware why not use a standard designed for the task rather than some
roll-your-own shit

Re: really slow PLL

<YbdCK.589974$5fVf.167665@fx09.iad>

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 by: bitrex - Thu, 21 Jul 2022 14:15 UTC

On 7/21/2022 10:12 AM, bitrex wrote:
> On 7/21/2022 4:33 AM, John Walliker wrote:
>> On Thursday, 21 July 2022 at 07:49:43 UTC+1, whit3rd wrote:
>>> On Wednesday, July 20, 2022 at 4:21:08 PM UTC-7, John Larkin wrote:
>>>> Suppose I have several rackmount boxes and each has a BNC connector on
>>>> the back. Each of them has an open-drain mosfet, a weak pullup, and a
>>>> lowpass filtered schmitt gate back into our FPGA.
>>>>
>>>> I can daisy-chain several boxes with BNC cables and tees.
>>>>
>>>> Each box has a 40 MHz VCXO and I want to phase-lock them, or at least
>>>> time-align them to always be the same within a few microseconds,
>>>> longterm.
>>> If you can tolerate 'a few microseconds' on a 40 MHz signal, that's
>>> not a phase-lock
>>> problem, it's a frequency-lock problem. Why not just run an up/down
>>> counter
>>> to generate a correction voltage for each non-leading VCO?
>>
>> If you have an ethernet interface to each unit then Precision Time
>> Protocol
>> should do exactly what you want.
>> https://en.wikipedia.org/wiki/Precision_Time_Protocol
>> John
>
> Yeah, that sounds like the ticket to me also. Trying to use each box's
> system clock for purposes of keeping "user-space" tasks in sync across
> boxes makes me uncomfortable, sounds like a srs hack.

At minimum it likely won't scale very well. Why implicitly discourage
one's customers from buying only a limited number of units

Re: really slow PLL

<749c3c03-5765-9bfe-a6e6-6b9be06fc84d@electrooptical.net>

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Subject: Re: really slow PLL
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From: pcdhSpam...@electrooptical.net (Phil Hobbs)
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 by: Phil Hobbs - Thu, 21 Jul 2022 14:15 UTC

Gerhard Hoffmann wrote:
> Am 21.07.22 um 13:19 schrieb jlarkin@highlandsniptechnology.com:
>
>>
>> Where does the 10 MHz come from?
>
> Choise of implementer. One local clock generator is needed.
> This clock determines short term stabiity and phase noise.
>
> My Lucent KS24361 uses 5 MHz MTI-260 double ovens; for
> redundancy/holdover it has a 2nd unit with another crystal
> oven without a receiver.
>
> The redundancy units were really hard to sell without the
> receiver; that's why I have 20 of these MTI-260, got a good
> price. :-)
>
> They were new old stock built by HP/Agilent for Lucent as
> replacement parts. They have never been on a telecom tower
> in China like most of those one gets on ebay.
>
> I have expanded the Lucent to 10 MHZ and with a distribution
> amplifier:
>
> <   http://www.hoffmann-hochfrequenz.de/downloads/DoubDist.pdf  >
>
> cheers, Gerhard

I wonder if there's an advantage to using the closure phase for an array
that large. With 17 oscillators you've got 136 independent phase
differences, so maybe there's a way to get 22 dB instead of 12 dB
improvement.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

Re: really slow PLL

<d3f52888-9988-4c6f-bf55-25cc748dc3a1n@googlegroups.com>

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Subject: Re: really slow PLL
From: langw...@fonz.dk (Lasse Langwadt Christensen)
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 by: Lasse Langwadt Chris - Thu, 21 Jul 2022 14:21 UTC

torsdag den 21. juli 2022 kl. 16.04.42 UTC+2 skrev bitrex:
> On 7/21/2022 7:06 AM, Martin Brown wrote:
> > On 21/07/2022 01:22, John Larkin wrote:
> >> On Wed, 20 Jul 2022 19:32:20 -0400, Phil Hobbs
> >> <pcdhSpamM...@electrooptical.net> wrote:
> >>
> >>> John Larkin wrote:
> >>>>
> >>>>
> >>>> Suppose I have several rackmount boxes and each has a BNC connector on
> >>>> the back. Each of them has an open-drain mosfet, a weak pullup, and a
> >>>> lowpass filtered schmitt gate back into our FPGA.
> >>>>
> >>>> I can daisy-chain several boxes with BNC cables and tees.
> >>>>
> >>>> Each box has a 40 MHz VCXO and I want to phase-lock them, or at least
> >>>> time-align them to always be the same within a few microseconds,
> >>>> longterm.
> >>>>
> >>>> I could call one the leader (not "master") and make the others
> >>>> followers (not "slaves") and have the leader make an active low pulse
> >>>> maybe once a second. A follower would use her (not "his") clock to
> >>>> measure the incoming period and tweak its local VCXO in the right
> >>>> direction. That should work.
> >>>>
> >>>> Don't GPS receivers lock their 10 MHz oscillators to a 1 PPS pulse
> >>>> from the satellites?
> >>>>
> >>>> My system should work from a 1 PPS GPS pulse too, all boxes as
> >>>> followers.
> >>>>
> >>>> The PLL algorithm might be interesting.
> >>>>
> >>>
> >>> It's certainly possible. However, within whatever tiny loop bandwidth
> >>> you wound up with, the lockers would still have
> >>>
> >>> 20 log(40e6) = 152 dB
> >>>
> >>> higher phase noise than the lockee.
> >>
> >> GPS has that problem too.
> >>
> >>>
> >>> It would be interesting to do the math to see whether it's possible to
> >>> generate a concensus lock for the group: if you get everybody close
> >>> enough, just sum their sine wave outputs and lock each one of them to
> >>> that, with some bit of AC coupling or something so that they don't all
> >>> wander together off to the edge of the tuning range.
> >>>
> >>> Maybe have one doing the locking with a phase shifter and the others
> >>> with VCOs, or something like that.
> >>>
> >>> Definitely a partly-baked idea, but surely one could do better than
> >>> 152 dB!
> >>>
> >>> Cheers
> >>>
> >>> Phil Hobbs
> >>
> >> Each box is basically a multichannel power supply, but channels can be
> >> programmed to do stuff in timed sequences. I want different box
> >> outputs to time align within, say, one millisecond longterm once
> >> programs are kicked off together. So, many microseconds of equivalent
> >> RMS phase noise is OK as long as we stay time aligned longterm.
> >
> > You really need to define longterm before the problem becomes well
> > posed. Do you mean hours, days, weeks or months of runtime?
> Yeah I don't quite get it, either. My rack of synthesizers can each play
> one voice of the Maple Leaf Rag via MIDI and they all stay synced
> together really well, at least over a timespan of several
> minutes.

but they are anot free runnign are they? they are all reacting to midi

Re: really slow PLL

<fef9280b-a7fb-b351-d65f-780d294f02a4@electrooptical.net>

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From: pcdhSpam...@electrooptical.net (Phil Hobbs)
Newsgroups: sci.electronics.design
Subject: Re: really slow PLL
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 by: Phil Hobbs - Thu, 21 Jul 2022 14:26 UTC

bitrex wrote:
> On 7/21/2022 7:06 AM, Martin Brown wrote:
>> On 21/07/2022 01:22, John Larkin wrote:
>>> On Wed, 20 Jul 2022 19:32:20 -0400, Phil Hobbs
>>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>>
>>>> John Larkin wrote:
>>>>>
>>>>>
>>>>> Suppose I have several rackmount boxes and each has a BNC connector on
>>>>> the back. Each of them has an open-drain mosfet, a weak pullup, and a
>>>>> lowpass filtered schmitt gate back into our FPGA.
>>>>>
>>>>> I can daisy-chain several boxes with BNC cables and tees.
>>>>>
>>>>> Each box has a 40 MHz VCXO and I want to phase-lock them, or at least
>>>>> time-align them to always be the same within a few microseconds,
>>>>> longterm.
>>>>>
>>>>> I could call one the leader (not "master") and make the others
>>>>> followers (not "slaves") and have the leader make an active low pulse
>>>>> maybe once a second. A follower would use her (not "his") clock to
>>>>> measure the incoming period and tweak its local VCXO in the right
>>>>> direction. That should work.
>>>>>
>>>>> Don't GPS receivers lock their 10 MHz oscillators to a 1 PPS pulse
>>>>> from the satellites?
>>>>>
>>>>> My system should work from a 1 PPS GPS pulse too, all boxes as
>>>>> followers.
>>>>>
>>>>> The PLL algorithm might be interesting.
>>>>>
>>>>
>>>> It's certainly possible.  However, within whatever tiny loop bandwidth
>>>> you wound up with, the lockers would still have
>>>>
>>>> 20 log(40e6) = 152 dB
>>>>
>>>> higher phase noise than the lockee.
>>>
>>> GPS has that problem too.
>>>
>>>>
>>>> It would be interesting to do the math to see whether it's possible to
>>>> generate a concensus lock for the group: if you get everybody close
>>>> enough, just sum their sine wave outputs and lock each one of them to
>>>> that, with some bit of AC coupling or something so that they don't all
>>>> wander together off to the edge of the tuning range.
>>>>
>>>> Maybe have one doing the locking with a phase shifter and the others
>>>> with VCOs, or something like that.
>>>>
>>>> Definitely a partly-baked idea, but surely one could do better than
>>>> 152 dB!
>>>>
>>>> Cheers
>>>>
>>>> Phil Hobbs
>>>
>>> Each box is basically a multichannel power supply, but channels can be
>>> programmed to do stuff in timed sequences. I want different box
>>> outputs to time align within, say, one millisecond longterm once
>>> programs are kicked off together. So, many microseconds of equivalent
>>> RMS phase noise is OK as long as we stay time aligned longterm.
>>
>> You really need to define longterm before the problem becomes well
>> posed. Do you mean hours, days, weeks or months of runtime?
>
> Yeah I don't quite get it, either. My rack of synthesizers can each play
> one voice of the Maple Leaf Rag via MIDI and they all stay synced
> together really well, at least over a timespan of several
> minutes...superficially at least it sounds like he wants a sequencer.
>
> Using the nuts & bolts system clock for synchronization of "user tasks"
> also makes me uncomfortable, if the device behavior only need to align
> to the millisecond why not trigger them using some simple network
> protocol and let their hardware figure out how long a millisecond is
> independently. Do the timings of these boxes need to be tighter than the
> Maple Leaf Rag?
>
>
Given that it's so simple to do it right, why not do that?

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

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